CoCalc -- rk3328

GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/dev/clk/rockchip/rk3328_cru.c
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/*-
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 * SPDX-License-Identifier: BSD-2-Clause
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 *
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 * Copyright (c) 2018-2021 Emmanuel Vadot <[email protected]>
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * 1. Redistributions of source code must retain the above copyright
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 *    notice, this list of conditions and the following disclaimer.
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 * 2. Redistributions in binary form must reproduce the above copyright
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 *    notice, this list of conditions and the following disclaimer in the
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 *    documentation and/or other materials provided with the distribution.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
35

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#include <dev/fdt/simplebus.h>
37

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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
40

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#include <dev/clk/clk_div.h>
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#include <dev/clk/clk_fixed.h>
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#include <dev/clk/clk_mux.h>
44

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#include <dev/clk/rockchip/rk_cru.h>
46

47
#define	CRU_CLKSEL_CON(x)	(0x100 + (x) * 0x4)
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#define	CRU_CLKGATE_CON(x)	(0x200 + (x) * 0x4)
49

50
/* Registers */
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#define	RK3328_GRF_SOC_CON4	0x410
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#define	RK3328_GRF_MAC_CON1	0x904
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#define	RK3328_GRF_MAC_CON2	0x908
54

55
/* Exported clocks */
56

57
#define	PLL_APLL		1
58
#define	PLL_DPLL		2
59
#define	PLL_CPLL		3
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#define	PLL_GPLL		4
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#define	PLL_NPLL		5
62
#define	ARMCLK			6
63

64
/* SCLK */
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#define	SCLK_RTC32K		30
66
#define	SCLK_SDMMC_EXT		31
67
#define	SCLK_SPI		32
68
#define	SCLK_SDMMC		33
69
#define	SCLK_SDIO		34
70
#define	SCLK_EMMC		35
71
#define	SCLK_TSADC		36
72
#define	SCLK_SARADC		37
73
#define	SCLK_UART0		38
74
#define	SCLK_UART1		39
75
#define	SCLK_UART2		40
76
#define	SCLK_I2S0		41
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#define	SCLK_I2S1		42
78
#define	SCLK_I2S2		43
79
#define	SCLK_I2S1_OUT		44
80
#define	SCLK_I2S2_OUT		45
81
#define	SCLK_SPDIF		46
82
#define	SCLK_TIMER0		47
83
#define	SCLK_TIMER1		48
84
#define	SCLK_TIMER2		49
85
#define	SCLK_TIMER3		50
86
#define	SCLK_TIMER4		51
87
#define	SCLK_TIMER5		52
88
#define	SCLK_WIFI		53
89
#define	SCLK_CIF_OUT		54
90
#define	SCLK_I2C0		55
91
#define	SCLK_I2C1		56
92
#define	SCLK_I2C2		57
93
#define	SCLK_I2C3		58
94
#define	SCLK_CRYPTO		59
95
#define	SCLK_PWM		60
96
#define	SCLK_PDM		61
97
#define	SCLK_EFUSE		62
98
#define	SCLK_OTP		63
99
#define	SCLK_DDRCLK		64
100
#define	SCLK_VDEC_CABAC		65
101
#define	SCLK_VDEC_CORE		66
102
#define	SCLK_VENC_DSP		67
103
#define	SCLK_VENC_CORE		68
104
#define	SCLK_RGA		69
105
#define	SCLK_HDMI_SFC		70
106
#define	SCLK_HDMI_CEC		71	/* Unused ? */
107
#define	SCLK_USB3_REF		72
108
#define	SCLK_USB3_SUSPEND	73
109
#define	SCLK_SDMMC_DRV		74
110
#define	SCLK_SDIO_DRV		75
111
#define	SCLK_EMMC_DRV		76
112
#define	SCLK_SDMMC_EXT_DRV	77
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#define	SCLK_SDMMC_SAMPLE	78
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#define	SCLK_SDIO_SAMPLE	79
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#define	SCLK_EMMC_SAMPLE	80
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#define	SCLK_SDMMC_EXT_SAMPLE	81
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#define	SCLK_VOP		82
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#define	SCLK_MAC2PHY_RXTX	83
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#define	SCLK_MAC2PHY_SRC	84
120
#define	SCLK_MAC2PHY_REF	85
121
#define	SCLK_MAC2PHY_OUT	86
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#define	SCLK_MAC2IO_RX		87
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#define	SCLK_MAC2IO_TX		88
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#define	SCLK_MAC2IO_REFOUT	89
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#define	SCLK_MAC2IO_REF		90
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#define	SCLK_MAC2IO_OUT		91
127
#define	SCLK_TSP		92
128
#define	SCLK_HSADC_TSP		93
129
#define	SCLK_USB3PHY_REF	94
130
#define	SCLK_REF_USB3OTG	95
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#define	SCLK_USB3OTG_REF	96
132
#define	SCLK_USB3OTG_SUSPEND	97
133
#define	SCLK_REF_USB3OTG_SRC	98
134
#define	SCLK_MAC2IO_SRC		99
135
#define	SCLK_MAC2IO		100
136
#define	SCLK_MAC2PHY		101
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#define	SCLK_MAC2IO_EXT		102
138

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/* DCLK */
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#define	DCLK_LCDC		120
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#define	DCLK_HDMIPHY		121
142
#define	HDMIPHY			122
143
#define	USB480M			123
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#define	DCLK_LCDC_SRC		124
145

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/* ACLK */
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#define	ACLK_AXISRAM		130	/* Unused */
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#define	ACLK_VOP_PRE		131
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#define	ACLK_USB3OTG		132
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#define	ACLK_RGA_PRE		133
151
#define	ACLK_DMAC		134	/* Unused */
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#define	ACLK_GPU		135
153
#define	ACLK_BUS_PRE		136
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#define	ACLK_PERI_PRE		137
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#define	ACLK_RKVDEC_PRE		138
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#define	ACLK_RKVDEC		139
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#define	ACLK_RKVENC		140
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#define	ACLK_VPU_PRE		141
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#define	ACLK_VIO_PRE		142
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#define	ACLK_VPU		143
161
#define	ACLK_VIO		144
162
#define	ACLK_VOP		145
163
#define	ACLK_GMAC		146
164
#define	ACLK_H265		147
165
#define	ACLK_H264		148
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#define	ACLK_MAC2PHY		149
167
#define	ACLK_MAC2IO		150
168
#define	ACLK_DCF		151
169
#define	ACLK_TSP		152
170
#define	ACLK_PERI		153
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#define	ACLK_RGA		154
172
#define	ACLK_IEP		155
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#define	ACLK_CIF		156
174
#define	ACLK_HDCP		157
175

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/* PCLK */
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#define	PCLK_GPIO0		200
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#define	PCLK_GPIO1		201
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#define	PCLK_GPIO2		202
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#define	PCLK_GPIO3		203
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#define	PCLK_GRF		204
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#define	PCLK_I2C0		205
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#define	PCLK_I2C1		206
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#define	PCLK_I2C2		207
185
#define	PCLK_I2C3		208
186
#define	PCLK_SPI		209
187
#define	PCLK_UART0		210
188
#define	PCLK_UART1		211
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#define	PCLK_UART2		212
190
#define	PCLK_TSADC		213
191
#define	PCLK_PWM		214
192
#define	PCLK_TIMER		215
193
#define	PCLK_BUS_PRE		216
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#define	PCLK_PERI_PRE		217	/* Unused */
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#define	PCLK_HDMI_CTRL		218	/* Unused */
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#define	PCLK_HDMI_PHY		219	/* Unused */
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#define	PCLK_GMAC		220
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#define	PCLK_H265		221
199
#define	PCLK_MAC2PHY		222
200
#define	PCLK_MAC2IO		223
201
#define	PCLK_USB3PHY_OTG	224
202
#define	PCLK_USB3PHY_PIPE	225
203
#define	PCLK_USB3_GRF		226
204
#define	PCLK_USB2_GRF		227
205
#define	PCLK_HDMIPHY		228
206
#define	PCLK_DDR		229
207
#define	PCLK_PERI		230
208
#define	PCLK_HDMI		231
209
#define	PCLK_HDCP		232
210
#define	PCLK_DCF		233
211
#define	PCLK_SARADC		234
212
#define	PCLK_ACODECPHY		235
213
#define	PCLK_WDT		236	/* Controlled from the secure GRF */
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/* HCLK */
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#define	HCLK_PERI		308
217
#define	HCLK_TSP		309
218
#define	HCLK_GMAC		310	/* Unused */
219
#define	HCLK_I2S0_8CH		311
220
#define	HCLK_I2S1_8CH		312
221
#define	HCLK_I2S2_2CH		313
222
#define	HCLK_SPDIF_8CH		314
223
#define	HCLK_VOP		315
224
#define	HCLK_NANDC		316	/* Unused */
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#define	HCLK_SDMMC		317
226
#define	HCLK_SDIO		318
227
#define	HCLK_EMMC		319
228
#define	HCLK_SDMMC_EXT		320
229
#define	HCLK_RKVDEC_PRE		321
230
#define	HCLK_RKVDEC		322
231
#define	HCLK_RKVENC		323
232
#define	HCLK_VPU_PRE		324
233
#define	HCLK_VIO_PRE		325
234
#define	HCLK_VPU		326
235
/* 327 doesn't exists */
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#define	HCLK_BUS_PRE		328
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#define	HCLK_PERI_PRE		329	/* Unused */
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#define	HCLK_H264		330
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#define	HCLK_CIF		331
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#define	HCLK_OTG_PMU		332
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#define	HCLK_OTG		333
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#define	HCLK_HOST0		334
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#define	HCLK_HOST0_ARB		335
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#define	HCLK_CRYPTO_MST		336
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#define	HCLK_CRYPTO_SLV		337
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#define	HCLK_PDM		338
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#define	HCLK_IEP		339
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#define	HCLK_RGA		340
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#define	HCLK_HDCP		341
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static struct rk_cru_gate rk3328_gates[] = {
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	/* CRU_CLKGATE_CON0 */
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	GATE(0, "core_apll_clk", "apll", 0, 0),
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	GATE(0, "core_dpll_clk", "dpll", 0, 1),
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	GATE(0, "core_gpll_clk", "gpll", 0, 2),
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	/* Bit 3 bus_src_clk_en */
257
	/* Bit 4 clk_ddrphy_src_en */
258
	/* Bit 5 clk_ddrpd_src_en */
259
	/* Bit 6 clk_ddrmon_en */
260
	/* Bit 7-8 unused */
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	/* Bit 9 testclk_en */
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	GATE(SCLK_WIFI, "sclk_wifi", "sclk_wifi_c", 0, 10),
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	GATE(SCLK_RTC32K, "clk_rtc32k", "clk_rtc32k_c", 0, 11),
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	GATE(0, "core_npll_clk", "npll", 0, 12),
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	/* Bit 13-15 unused */
266

267
	/* CRU_CLKGATE_CON1 */
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	/* Bit 0 unused */
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	GATE(0, "clk_i2s0_div", "clk_i2s0_div_c", 1, 1),
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	GATE(0, "clk_i2s0_frac", "clk_i2s0_frac_f", 1, 2),
271
	GATE(SCLK_I2S0, "clk_i2s0", "clk_i2s0_mux", 1, 3),
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	GATE(0, "clk_i2s1_div", "clk_i2s1_div_c", 1, 4),
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	GATE(0, "clk_i2s1_frac", "clk_i2s1_frac_f", 1, 5),
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	GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", 1, 6),
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	GATE(0, "clk_i2s1_out", "clk_i2s1_mux", 1, 7),
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	GATE(0, "clk_i2s2_div", "clk_i2s2_div_c", 1, 8),
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	GATE(0, "clk_i2s2_frac", "clk_i2s2_frac_f", 1, 9),
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	GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", 1, 10),
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	GATE(0, "clk_i2s2_out", "clk_i2s2_mux", 1, 11),
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	GATE(0, "clk_spdif_div", "clk_spdif_div_c", 1, 12),
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	GATE(0, "clk_spdif_frac", "clk_spdif_frac_f", 1, 13),
282
	GATE(0, "clk_uart0_div", "clk_uart0_div_c", 1, 14),
283
	GATE(0, "clk_uart0_frac", "clk_uart0_frac_f", 1, 15),
284

285
	/* CRU_CLKGATE_CON2 */
286
	GATE(0, "clk_uart1_div", "clk_uart1_div_c", 2, 0),
287
	GATE(0, "clk_uart1_frac", "clk_uart1_frac_f", 2, 1),
288
	GATE(0, "clk_uart2_div", "clk_uart2_div_c", 2, 2),
289
	GATE(0, "clk_uart2_frac", "clk_uart2_frac_f", 2, 3),
290
	GATE(SCLK_CRYPTO, "clk_crypto", "clk_crypto_c", 2, 4),
291
	GATE(SCLK_TSP, "clk_tsp", "clk_tsp_c", 2, 5),
292
	GATE(SCLK_TSADC, "clk_tsadc_src", "clk_tsadc_c", 2, 6),
293
	GATE(SCLK_SPI, "clk_spi", "clk_spi_c", 2, 7),
294
	GATE(SCLK_PWM, "clk_pwm", "clk_pwm_c", 2, 8),
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	GATE(SCLK_I2C0, "clk_i2c0_src", "clk_i2c0_c", 2, 9),
296
	GATE(SCLK_I2C1, "clk_i2c1_src", "clk_i2c1_c", 2, 10),
297
	GATE(SCLK_I2C2, "clk_i2c2_src", "clk_i2c2_c", 2, 11),
298
	GATE(SCLK_I2C3, "clk_i2c3_src", "clk_i2c3_c", 2, 12),
299
	GATE(SCLK_EFUSE, "clk_efuse", "clk_efuse_c", 2, 13),
300
	GATE(SCLK_SARADC, "clk_saradc", "clk_saradc_c", 2, 14),
301
	GATE(SCLK_PDM, "clk_pdm", "clk_pdm_c", 2, 15),
302

303
	/* CRU_CLKGATE_CON3 */
304
	GATE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", "clk_mac2phy_src_c", 3, 0),
305
	GATE(SCLK_MAC2IO_SRC, "clk_mac2io_src", "clk_mac2io_src_c", 3, 1),
306
	GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_c", 3, 2),
307
	/* Bit 3 gmac_gpll_src_en Unused ? */
308
	/* Bit 4 gmac_vpll_src_en Unused ? */
309
	GATE(SCLK_MAC2IO_OUT, "clk_mac2io_out", "clk_mac2io_out_c", 3, 5),
310
	/* Bit 6-7 unused */
311
	GATE(SCLK_OTP, "clk_otp", "clk_otp_c", 3, 8),
312
	/* Bit 9-15 unused */
313

314
	/* CRU_CLKGATE_CON4 */
315
	GATE(0, "periph_gclk_src", "gpll", 4, 0),
316
	GATE(0, "periph_cclk_src", "cpll", 4, 1),
317
	GATE(0, "hdmiphy_peri", "hdmiphy", 4, 2),
318
	GATE(SCLK_SDMMC, "clk_mmc0_src", "clk_sdmmc_c", 4, 3),
319
	GATE(SCLK_SDIO, "clk_sdio_src", "clk_sdio_c", 4, 4),
320
	GATE(SCLK_EMMC, "clk_emmc_src", "clk_emmc_c", 4, 5),
321
	GATE(SCLK_REF_USB3OTG_SRC, "clk_ref_usb3otg_src", "clk_ref_usb3otg_src_c", 4, 6),
322
	GATE(SCLK_USB3OTG_REF, "clk_usb3_otg0_ref", "xin24m", 4, 7),
323
	GATE(SCLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", "clk_usb3otg_suspend_c", 4, 8),
324
	/* Bit 9 clk_usb3phy_ref_25m_en */
325
	GATE(SCLK_SDMMC_EXT, "clk_sdmmc_ext", "clk_sdmmc_ext_c", 4, 10),
326
	/* Bit 11-15 unused */
327

328
	/* CRU_CLKGATE_CON5 */
329
	GATE(ACLK_RGA_PRE, "aclk_rga_pre", "aclk_rga_pre_c", 5, 0),
330
	GATE(SCLK_RGA, "sclk_rga", "sclk_rga_c", 5, 0),
331
	GATE(ACLK_VIO_PRE, "aclk_vio_pre", "aclk_vio_pre_c", 5, 2),
332
	GATE(SCLK_CIF_OUT, "clk_cif_src", "clk_cif_src_c", 5, 3),
333
	GATE(SCLK_HDMI_SFC, "clk_hdmi_sfc", "xin24m", 5, 4),
334
	GATE(ACLK_VOP_PRE, "aclk_vop_pre", "aclk_vop_pre_c", 5, 5),
335
	GATE(DCLK_LCDC_SRC, "vop_dclk_src", "vop_dclk_src_c", 5, 6),
336
	/* Bit 7-15 unused */
337

338
	/* CRU_CLKGATE_CON6 */
339
	GATE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", "aclk_rkvdec_c", 6, 0),
340
	GATE(SCLK_VDEC_CABAC, "sclk_cabac", "sclk_cabac_c", 6, 1),
341
	GATE(SCLK_VDEC_CORE, "sclk_vdec_core", "sclk_vdec_core_c", 6, 2),
342
	GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_c", 6, 3),
343
	GATE(SCLK_VENC_CORE, "sclk_venc", "sclk_venc_c", 6, 4),
344
	GATE(ACLK_VPU_PRE, "aclk_vpu_pre", "aclk_vpu_pre_c", 6, 5),
345
	GATE(0, "aclk_gpu_pre", "aclk_gpu_pre_c", 6, 6),
346
	GATE(SCLK_VENC_DSP, "sclk_venc_dsp", "sclk_venc_dsp_c", 6, 7),
347
	/* Bit 8-15 unused */
348

349
	/* CRU_CLKGATE_CON7 */
350
	/* Bit 0 aclk_core_en */
351
	/* Bit 1 clk_core_periph_en */
352
	/* Bit 2 clk_jtag_en */
353
	/* Bit 3 unused */
354
	/* Bit 4 pclk_ddr_en */
355
	/* Bit 5-15 unused */
356

357
	/* CRU_CLKGATE_CON8 */
358
	GATE(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_pre_c", 8, 0),
359
	GATE(HCLK_BUS_PRE, "hclk_bus_pre", "hclk_bus_pre_c", 8, 1),
360
	GATE(PCLK_BUS_PRE, "pclk_bus_pre", "pclk_bus_pre_c", 8, 2),
361
	GATE(0, "pclk_bus", "pclk_bus_pre", 8, 3),
362
	GATE(0, "pclk_phy", "pclk_bus_pre", 8, 4),
363
	GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 8, 5),
364
	GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 8, 6),
365
	GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 8, 7),
366
	GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 8, 8),
367
	GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 8, 9),
368
	GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 8, 10),
369
	/* Bit 11-15 unused */
370

371
	/* CRU_CLKGATE_CON9 */
372
	GATE(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 9, 0),
373
	GATE(SCLK_MAC2PHY_RXTX, "clk_gmac2phy_rx", "clk_mac2phy", 9, 1),
374
	GATE(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy_out_c", 9, 2),
375
	GATE(SCLK_MAC2PHY_REF, "clk_gmac2phy_ref", "clk_mac2phy", 9, 3),
376
	GATE(SCLK_MAC2IO_RX, "clk_gmac2io_rx", "clk_mac2io", 9, 4),
377
	GATE(SCLK_MAC2IO_TX, "clk_gmac2io_tx", "clk_mac2io", 9, 5),
378
	GATE(SCLK_MAC2IO_REFOUT, "clk_gmac2io_refout", "clk_mac2io", 9, 6),
379
	GATE(SCLK_MAC2IO_REF, "clk_gmac2io_ref", "clk_mac2io", 9, 7),
380
	/* Bit 8-15 unused */
381

382
	/* CRU_CLKGATE_CON10 */
383
	GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 10, 0),
384
	GATE(HCLK_PERI, "hclk_peri", "hclk_peri_c", 10, 1),
385
	GATE(PCLK_PERI, "pclk_peri", "pclk_peri_c", 10, 2),
386
	/* Bit 3-15 unused */
387

388
	/* CRU_CLKGATE_CON11 */
389
	GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 11, 0),
390
	/* Bit 1-3 unused */
391
	GATE(HCLK_RKVENC, "hclk_rkvenc", "aclk_rkvenc", 11, 4),
392
	/* Bit 5-7 unused */
393
	GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 11, 8),
394
	/* Bit 9-15 unused */
395

396
	/* CRU_CLKGATE_CON12 */
397
	/* unused */
398

399
	/* CRU_CLKGATE_CON13 */
400
	/* Bit 0 aclk_core_niu_en */
401
	/* Bit 1 aclk_gic400_en */
402
	/* Bit 2-15 unused */
403

404
	/* CRU_CLKGATE_CON14 */
405
	GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 14, 0),
406
	GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 14, 1),
407
	/* Bit 2-15 unused */
408

409
	/* CRU_CLKGATE_CON15*/
410
	/* Bit 0 aclk_intmem_en Unused */
411
	/* Bit 1 aclk_dmac_bus_en Unused */
412
	/* Bit 2 hclk_rom_en Unused */
413
	GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 15, 3),
414
	GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_bus_pre", 15, 4),
415
	GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 15, 5),
416
	GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_bus_pre", 15, 6),
417
	GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 15, 7),
418
	GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 15, 8),
419
	GATE(0, "pclk_efuse", "pclk_bus", 15, 9),
420
	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 15, 10),
421
	GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 15, 11),
422
	GATE(0, "aclk_bus_niu", "aclk_bus_pre", 15, 12),
423
	GATE(0, "hclk_bus_niu", "hclk_bus_pre", 15, 13),
424
	GATE(0, "pclk_bus_niu", "pclk_bus_pre", 15, 14),
425
	GATE(0, "pclk_phy_niu", "pclk_phy", 15, 14),
426
	/* Bit 15 pclk_phy_niu_en */
427

428
	/* CRU_CLKGATE_CON16 */
429
	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 16, 0),
430
	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 16, 1),
431
	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 16, 2),
432
	GATE(PCLK_TIMER, "pclk_timer0", "pclk_bus", 16, 3),
433
	GATE(0, "pclk_stimer", "pclk_bus", 16, 4),
434
	GATE(PCLK_SPI, "pclk_spi", "pclk_bus", 16, 5),
435
	GATE(PCLK_PWM, "pclk_pwm", "pclk_bus", 16, 6),
436
	GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 16, 7),
437
	GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 16, 8),
438
	GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 16, 9),
439
	GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 16, 10),
440
	GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 16, 11),
441
	GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 16, 12),
442
	GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 16, 13),
443
	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 16, 14),
444
	GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 16, 15),
445

446
	/* CRU_CLKGATE_CON17 */
447
	GATE(PCLK_GRF, "pclk_grf", "pclk_bus", 17, 0),
448
	/* Bit 1 unused */
449
	GATE(PCLK_USB3_GRF, "pclk_usb3grf", "pclk_phy", 17, 2),
450
	GATE(0, "pclk_ddrphy", "pclk_phy", 17, 3),
451
	GATE(0, "pclk_cru", "pclk_bus", 17, 4),
452
	GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy", 17, 5),
453
	GATE(0, "pclk_sgrf", "pclk_bus", 17, 6),
454
	GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy", 17, 7),
455
	GATE(0, "pclk_vdacphy", "pclk_bus", 17, 8),
456
	/* Bit 9 unused */
457
	GATE(0, "pclk_sim", "pclk_bus", 17, 10),
458
	GATE(HCLK_TSP, "hclk_tsp", "hclk_bus_pre", 17, 11),
459
	GATE(ACLK_TSP, "aclk_tsp", "aclk_bus_pre", 17, 12),
460
	/* Bit 13 clk_hsadc_0_tsp_en Depend on a gpio clock ? */
461
	GATE(PCLK_USB2_GRF, "pclk_usb2grf", "pclk_phy", 17, 14),
462
	GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 17, 15),
463

464
	/* CRU_CLKGATE_CON18 */
465
	/* Bit 0 unused */
466
	/* Bit 1 pclk_ddr_upctl_en */
467
	/* Bit 2 pclk_ddr_msch_en */
468
	/* Bit 3 pclk_ddr_mon_en */
469
	/* Bit 4 aclk_ddr_upctl_en */
470
	/* Bit 5 clk_ddr_upctl_en */
471
	/* Bit 6 clk_ddr_msch_en */
472
	/* Bit 7 pclk_ddrstdby_en */
473
	/* Bit 8-15 unused */
474

475
	/* CRU_CLKGATE_CON19 */
476
	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 19, 0),
477
	GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 19, 1),
478
	GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 19, 2),
479
	/* Bit 3-5 unused */
480
	GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 19, 6),
481
	GATE(HCLK_HOST0_ARB, "hclk_host0_arg", "hclk_peri", 19, 7),
482
	GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 19, 8),
483
	GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 19, 9),
484
	/* Bit 10 unused */
485
	GATE(0, "aclk_peri_niu", "aclk_peri", 19, 11),
486
	GATE(0, "hclk_peri_niu", "hclk_peri", 19, 12),
487
	GATE(0, "pclk_peri_niu", "hclk_peri", 19, 13),
488
	GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 19, 14),
489
	GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 19, 15),
490

491
	/* CRU_CLKGATE_CON20 */
492
	/* unused */
493

494
	/* CRU_CLKGATE_CON21 */
495
	/* Bit 0-1 unused */
496
	GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 21, 2),
497
	GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 21, 3),
498
	GATE(0, "aclk_vop_niu", "aclk_vop_pre", 21, 4),
499
	GATE(0, "hclk_vop_niu", "hclk_vio_pre", 21, 5),
500
	GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 21, 6),
501
	GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 21, 7),
502
	GATE(ACLK_CIF, "aclk_cif", "aclk_vio_pre", 21, 8),
503
	GATE(HCLK_CIF, "hclk_cif", "hclk_vio_pre", 21, 9),
504
	GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 21, 10),
505
	GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 21, 11),
506
	GATE(0, "hclk_ahb1tom", "hclk_vio_pre", 21, 12),
507
	GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 21, 13),
508
	GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 21, 14),
509
	GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vio_pre", 21, 15),
510

511
	/* CRU_CLKGATE_CON22 */
512
	GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 22, 0),
513
	GATE(0, "hclk_vio_niu", "hclk_vio_pre", 22, 1),
514
	GATE(0, "aclk_vio_niu", "aclk_vio_pre", 22, 2),
515
	GATE(0, "aclk_rga_niu", "aclk_rga_pre", 22, 3),
516
	GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 22, 4),
517
	GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 22, 5),
518
	/* Bit 6-15 unused */
519

520
	/* CRU_CLKGATE_CON23 */
521
	GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 23, 0),
522
	GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 23, 1),
523
	GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", 23, 2),
524
	GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", 23, 3),
525
	/* Bit 4-15 unused */
526

527
	/* CRU_CLKGATE_CON24 */
528
	GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 24, 0),
529
	GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 24, 1),
530
	GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", 24, 2),
531
	GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", 24, 3),
532
	/* Bit 4-15 unused */
533

534
	/* CRU_CLKGATE_CON25 */
535
	GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", 25, 0),
536
	GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 25, 1),
537
	GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 25, 2),
538
	GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 25, 3),
539
	GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 25, 4),
540
	GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 25, 5),
541
	GATE(0, "aclk_axisram", "hclk_rkvenc", 25, 6),
542
	/* Bit 7-15 unused */
543

544
	/* CRU_CLKGATE_CON26 */
545
	GATE(ACLK_MAC2PHY, "aclk_gmac2phy", "aclk_gmac", 26, 0),
546
	GATE(PCLK_MAC2PHY, "pclk_gmac2phy", "pclk_gmac", 26, 1),
547
	GATE(ACLK_MAC2IO, "aclk_gmac2io", "aclk_gmac", 26, 2),
548
	GATE(PCLK_MAC2IO, "pclk_gmac2io", "pclk_gmac", 26, 3),
549
	GATE(0, "aclk_gmac_niu", "aclk_gmac", 26, 4),
550
	GATE(0, "pclk_gmac_niu", "pclk_gmac", 26, 5),
551
	/* Bit 6-15 unused */
552

553
	/* CRU_CLKGATE_CON27 */
554
	/* Bit 0 clk_ddrphy_en */
555
	/* Bit 1 clk4x_ddrphy_en */
556

557
	/* CRU_CLKGATE_CON28 */
558
	GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 28, 0),
559
	GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy", 28, 1),
560
	GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy", 28, 2),
561
	GATE(0, "pclk_pmu", "pclk_bus", 28, 3),
562
	GATE(0, "pclk_otp", "pclk_bus", 28, 4)
563
	/* Bit 5-15 unused */
564
};
565

566
/*
567
 * PLLs
568
 */
569

570
#define PLL_RATE(_hz, _ref, _fb, _post1, _post2, _dspd, _frac)		\
571
{									\
572
	.freq = _hz,							\
573
	.refdiv = _ref,							\
574
	.fbdiv = _fb,							\
575
	.postdiv1 = _post1,						\
576
	.postdiv2 = _post2,						\
577
	.dsmpd = _dspd,							\
578
	.frac = _frac,							\
579
}
580

581
static struct rk_clk_pll_rate rk3328_pll_rates[] = {
582
	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
583
	PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
584
	PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
585
	PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
586
	PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
587
	PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
588
	PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
589
	PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
590
	PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
591
	PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
592
	PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
593
	PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
594
	PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
595
	PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
596
	PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
597
	PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
598
	PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
599
	PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
600
	PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
601
	PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
602
	PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
603
	PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
604
	PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
605
	PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
606
	PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
607
	PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
608
	PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
609
	PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
610
	PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
611
	PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
612
	PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
613
	PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
614
	PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
615
	PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
616
	PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
617
	PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
618
	PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
619
	PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
620
	PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
621
	PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
622
	PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
623
	PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
624
	PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
625
	{},
626
};
627

628
static struct rk_clk_pll_rate rk3328_pll_frac_rates[] = {
629
	PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134217),
630
	PLL_RATE(983040000, 24, 983, 1, 1, 0, 671088),
631
	PLL_RATE(491520000, 24, 983, 2, 1, 0, 671088),
632
	PLL_RATE(61440000, 6, 215, 7, 2, 0, 671088),
633
	PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797894),
634
	PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066329),
635
	{},
636
};
637

638
/* Clock parents */
639
PLIST(pll_src_p) = {"xin24m"};
640
PLIST(xin24m_rtc32k_p) = {"xin24m", "clk_rtc32k"};
641

642
PLIST(pll_src_cpll_gpll_p) = {"cpll", "gpll"};
643
PLIST(pll_src_cpll_gpll_apll_p) = {"cpll", "gpll", "apll"};
644
PLIST(pll_src_cpll_gpll_xin24m_p) = {"cpll", "gpll", "xin24m", "xin24m" /* Dummy */};
645
PLIST(pll_src_cpll_gpll_usb480m_p) = {"cpll", "gpll", "usb480m"};
646
PLIST(pll_src_cpll_gpll_hdmiphy_p) = {"cpll", "gpll", "hdmi_phy"};
647
PLIST(pll_src_cpll_gpll_hdmiphy_usb480m_p) = {"cpll", "gpll", "hdmi_phy", "usb480m"};
648
PLIST(pll_src_apll_gpll_dpll_npll_p) = {"apll", "gpll", "dpll", "npll"};
649
PLIST(pll_src_cpll_gpll_xin24m_usb480m_p) = {"cpll", "gpll", "xin24m", "usb480m"};
650
PLIST(mux_ref_usb3otg_p) = { "xin24m", "clk_usb3_otg0_ref" };
651
PLIST(mux_mac2io_p) = { "clk_mac2io_src", "gmac_clkin" };
652
PLIST(mux_mac2io_ext_p) = { "clk_mac2io", "gmac_clkin" };
653
PLIST(mux_mac2phy_p) = { "clk_mac2phy_src", "phy_50m_out" };
654
PLIST(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac", "xin12m", "xin12m" };
655
PLIST(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac", "clkin_i2s1", "xin12m" };
656
PLIST(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac", "clkin_i2s2", "xin12m" };
657
PLIST(mux_dclk_lcdc_p) = {"hdmiphy", "vop_dclk_src"};
658
PLIST(mux_hdmiphy_p) = {"hdmi_phy", "xin24m"};
659
PLIST(mux_usb480m_p) = {"usb480m_phy", "xin24m"};
660
PLIST(mux_uart0_p) = {"clk_uart0_div", "clk_uart0_frac", "xin24m", "xin24m"};
661
PLIST(mux_uart1_p) = {"clk_uart1_div", "clk_uart1_frac", "xin24m", "xin24m"};
662
PLIST(mux_uart2_p) = {"clk_uart2_div", "clk_uart2_frac", "xin24m", "xin24m"};
663
PLIST(mux_spdif_p) = {"clk_spdif_div", "clk_spdif_frac", "xin12m", "xin12m"};
664
PLIST(mux_cif_p) = {"clk_cif_pll", "xin24m"};
665

666
static struct rk_clk_pll_def apll = {
667
	.clkdef = {
668
		.id = PLL_APLL,
669
		.name = "apll",
670
		.parent_names = pll_src_p,
671
		.parent_cnt = nitems(pll_src_p),
672
	},
673
	.base_offset = 0x00,
674
	.gate_offset = 0x200,
675
	.gate_shift = 0,
676
	.mode_reg = 0x80,
677
	.mode_shift = 1,
678
	.flags = RK_CLK_PLL_HAVE_GATE,
679
	.frac_rates = rk3328_pll_frac_rates,
680
};
681

682
static struct rk_clk_pll_def dpll = {
683
	.clkdef = {
684
		.id = PLL_DPLL,
685
		.name = "dpll",
686
		.parent_names = pll_src_p,
687
		.parent_cnt = nitems(pll_src_p),
688
	},
689
	.base_offset = 0x20,
690
	.gate_offset = 0x200,
691
	.gate_shift = 1,
692
	.mode_reg = 0x80,
693
	.mode_shift = 4,
694
	.flags = RK_CLK_PLL_HAVE_GATE,
695
};
696

697
static struct rk_clk_pll_def cpll = {
698
	.clkdef = {
699
		.id = PLL_CPLL,
700
		.name = "cpll",
701
		.parent_names = pll_src_p,
702
		.parent_cnt = nitems(pll_src_p),
703
	},
704
	.base_offset = 0x40,
705
	.mode_reg = 0x80,
706
	.mode_shift = 8,
707
	.rates = rk3328_pll_rates,
708
};
709

710
static struct rk_clk_pll_def gpll = {
711
	.clkdef = {
712
		.id = PLL_GPLL,
713
		.name = "gpll",
714
		.parent_names = pll_src_p,
715
		.parent_cnt = nitems(pll_src_p),
716
	},
717
	.base_offset = 0x60,
718
	.gate_offset = 0x200,
719
	.gate_shift = 2,
720
	.mode_reg = 0x80,
721
	.mode_shift = 12,
722
	.flags = RK_CLK_PLL_HAVE_GATE,
723
	.frac_rates = rk3328_pll_frac_rates,
724
};
725

726
static struct rk_clk_pll_def npll = {
727
	.clkdef = {
728
		.id = PLL_NPLL,
729
		.name = "npll",
730
		.parent_names = pll_src_p,
731
		.parent_cnt = nitems(pll_src_p),
732
	},
733
	.base_offset = 0xa0,
734
	.gate_offset = 0x200,
735
	.gate_shift = 12,
736
	.mode_reg = 0x80,
737
	.mode_shift = 1,
738
	.flags = RK_CLK_PLL_HAVE_GATE,
739
	.rates = rk3328_pll_rates,
740
};
741

742
static struct rk_clk_armclk_rates rk3328_armclk_rates[] = {
743
	{
744
		.freq = 1296000000,
745
		.div = 1,
746
	},
747
	{
748
		.freq = 1200000000,
749
		.div = 1,
750
	},
751
	{
752
		.freq = 1104000000,
753
		.div = 1,
754
	},
755
	{
756
		.freq = 1008000000,
757
		.div = 1,
758
	},
759
	{
760
		.freq = 912000000,
761
		.div = 1,
762
	},
763
	{
764
		.freq = 816000000,
765
		.div = 1,
766
	},
767
	{
768
		.freq = 696000000,
769
		.div = 1,
770
	},
771
	{
772
		.freq = 600000000,
773
		.div = 1,
774
	},
775
	{
776
		.freq = 408000000,
777
		.div = 1,
778
	},
779
	{
780
		.freq = 312000000,
781
		.div = 1,
782
	},
783
	{
784
		.freq = 216000000,
785
		.div = 1,
786
	},
787
	{
788
		.freq = 96000000,
789
		.div = 1,
790
	},
791
};
792

793
static struct rk_clk_armclk_def armclk = {
794
	.clkdef = {
795
		.id = ARMCLK,
796
		.name = "armclk",
797
		.parent_names = pll_src_apll_gpll_dpll_npll_p,
798
		.parent_cnt = nitems(pll_src_apll_gpll_dpll_npll_p),
799
	},
800
	.muxdiv_offset = 0x100,
801
	.mux_shift = 6,
802
	.mux_width = 2,
803

804
	.div_shift = 0,
805
	.div_width = 5,
806

807
	.flags = RK_CLK_COMPOSITE_HAVE_MUX,
808
	.main_parent = 3, /* npll */
809
	.alt_parent = 0, /* apll */
810

811
	.rates = rk3328_armclk_rates,
812
	.nrates = nitems(rk3328_armclk_rates),
813
};
814

815
static struct rk_clk rk3328_clks[] = {
816
	/* External clocks */
817
	LINK("xin24m"),
818
	LINK("gmac_clkin"),
819
	LINK("hdmi_phy"),
820
	LINK("usb480m_phy"),
821
	FRATE(0, "xin12m", 12000000),
822
	FRATE(0, "phy_50m_out", 50000000),
823
	FRATE(0, "clkin_i2s1", 0),
824
	FRATE(0, "clkin_i2s2", 0),
825

826
	/* PLLs */
827
	{
828
		.type = RK3328_CLK_PLL,
829
		.clk.pll = &apll
830
	},
831
	{
832
		.type = RK3328_CLK_PLL,
833
		.clk.pll = &dpll
834
	},
835
	{
836
		.type = RK3328_CLK_PLL,
837
		.clk.pll = &cpll
838
	},
839
	{
840
		.type = RK3328_CLK_PLL,
841
		.clk.pll = &gpll
842
	},
843
	{
844
		.type = RK3328_CLK_PLL,
845
		.clk.pll = &npll
846
	},
847

848
	{
849
		.type = RK_CLK_ARMCLK,
850
		.clk.armclk = &armclk,
851
	},
852

853
	/* CRU_CRU_MISC */
854
	MUXRAW(HDMIPHY, "hdmiphy", mux_hdmiphy_p, 0, 0x84, 13, 1),
855
	MUXRAW(USB480M, "usb480m", mux_usb480m_p, 0, 0x84, 15, 1),
856

857
	/* CRU_CLKSEL_CON0 */
858
	/* COMP clk_core_div_con core_clk_pll_sel */
859
	COMP(0, "aclk_bus_pre_c", pll_src_cpll_gpll_hdmiphy_p, 0, 0, 8, 5, 13, 2),
860

861
	/* CRU_CLKSEL_CON1 */
862
	/* CDIV clk_core_dbg_div_con */
863
	/* CDIV aclk_core_div_con */
864
	CDIV(0, "hclk_bus_pre_c", "aclk_bus_pre", 0, 1, 8, 2),
865
	CDIV(0, "pclk_bus_pre_c", "aclk_bus_pre", 0, 1, 12, 2),
866

867
	/* CRU_CLKSEL_CON2 */
868
	/* CDIV test_div_con */
869
	/* CDIV func_24m_div_con */
870

871
	/* CRU_CLKSEL_CON3 */
872
	/* COMP ddr_div_cnt ddr_clk_pll_sel */
873

874
	/* CRU_CLKSEL_CON4 */
875
	COMP(0, "clk_otp_c", pll_src_cpll_gpll_xin24m_p, 0, 4, 0, 6, 6, 2),
876
	/* COMP pd_ddr_div_con ddrpdclk_clk_pll_sel */
877

878
	/* CRU_CLKSEL_CON5 */
879
	COMP(0, "clk_efuse_c", pll_src_cpll_gpll_xin24m_p, 0, 5, 8, 5, 14, 2),
880

881
	/* CRU_CLKSEL_CON6 */
882
	MUX(0, "clk_i2s0_mux", mux_i2s0_p, RK_CLK_MUX_REPARENT, 6, 8, 2),
883
	COMP(0, "clk_i2s0_div_c", pll_src_cpll_gpll_p, 0, 6, 0, 7, 15, 1),
884

885
	/* CRU_CLKSEL_CON7 */
886
	FRACT(0, "clk_i2s0_frac_f", "clk_i2s0_div", 0, 7),
887

888
	/* CRU_CLKSEL_CON8 */
889
	MUX(0, "clk_i2s1_mux", mux_i2s1_p, RK_CLK_MUX_REPARENT, 8, 8, 2),
890
	COMP(0, "clk_i2s1_div_c", pll_src_cpll_gpll_p, 0, 8, 0, 7, 15, 1),
891
	/* MUX i2s1_out_sel */
892

893
	/* CRU_CLKSEL_CON9 */
894
	FRACT(0, "clk_i2s1_frac_f", "clk_i2s1_div", 0, 9),
895

896
	/* CRU_CLKSEL_CON10 */
897
	MUX(0, "clk_i2s2_mux", mux_i2s2_p, RK_CLK_MUX_REPARENT, 10, 8, 2),
898
	COMP(0, "clk_i2s2_div_c", pll_src_cpll_gpll_p, 0, 10, 0, 7, 15, 1),
899
	/* MUX i2s2_out_sel */
900

901
	/* CRU_CLKSEL_CON11 */
902
	FRACT(0, "clk_i2s2_frac_f", "clk_i2s2_div", 0, 11),
903

904
	/* CRU_CLKSEL_CON12 */
905
	MUX(0, "clk_spdif_pll", pll_src_cpll_gpll_p, 0, 12, 15, 1),
906
	MUX(SCLK_SPDIF, "clk_spdif", mux_spdif_p, 0, 12, 8, 2),
907
	CDIV(0, "clk_spdif_div_c", "clk_spdif_pll", 0, 12, 0, 7),
908

909
	/* CRU_CLKSEL_CON13 */
910
	FRACT(0, "clk_spdif_frac_f", "clk_spdif", 0, 13),
911

912
	/* CRU_CLKSEL_CON14 */
913
	MUX(0, "clk_uart0_pll", pll_src_cpll_gpll_usb480m_p, 0, 14, 12, 2),
914
	MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, 0, 14, 8, 2),
915
	CDIV(0, "clk_uart0_div_c", "clk_uart0_pll", 0, 14, 0, 7),
916

917
	/* CRU_CLKSEL_CON15 */
918
	FRACT(0, "clk_uart0_frac_f", "clk_uart0_pll", 0, 15),
919

920
	/* CRU_CLKSEL_CON16 */
921
	MUX(0, "clk_uart1_pll", pll_src_cpll_gpll_usb480m_p, 0, 16, 12, 2),
922
	MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, 0, 16, 8, 2),
923
	CDIV(0, "clk_uart1_div_c", "clk_uart1_pll", 0, 16, 0, 7),
924

925
	/* CRU_CLKSEL_CON17 */
926
	FRACT(0, "clk_uart1_frac_f", "clk_uart1_pll", 0, 17),
927

928
	/* CRU_CLKSEL_CON18 */
929
	MUX(0, "clk_uart2_pll", pll_src_cpll_gpll_usb480m_p, 0, 18, 12, 2),
930
	MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, 0, 18, 8, 2),
931
	CDIV(0, "clk_uart2_div_c", "clk_uart2_pll", 0, 18, 0, 7),
932

933
	/* CRU_CLKSEL_CON19 */
934
	FRACT(0, "clk_uart2_frac_f", "clk_uart2_pll", 0, 19),
935

936
	/* CRU_CLKSEL_CON20 */
937
	COMP(0, "clk_pdm_c", pll_src_cpll_gpll_apll_p, 0, 20, 8, 5, 14, 2),
938
	COMP(0, "clk_crypto_c", pll_src_cpll_gpll_p, 0, 20, 0, 5, 7, 1),
939

940
	/* CRU_CLKSEL_CON21 */
941
	COMP(0, "clk_tsp_c", pll_src_cpll_gpll_p, 0, 21, 8, 5, 15, 1),
942

943
	/* CRU_CLKSEL_CON22 */
944
	CDIV(0, "clk_tsadc_c", "xin24m", 0, 22, 0, 10),
945

946
	/* CRU_CLKSEL_CON23 */
947
	CDIV(0, "clk_saradc_c", "xin24m", 0, 23, 0, 10),
948

949
	/* CRU_CLKSEL_CON24 */
950
	COMP(0, "clk_pwm_c", pll_src_cpll_gpll_p, 0, 24, 8, 7, 15, 1),
951
	COMP(0, "clk_spi_c", pll_src_cpll_gpll_p, 0, 24, 0, 7, 7, 1),
952

953
	/* CRU_CLKSEL_CON25 */
954
	COMP(0, "aclk_gmac_c", pll_src_cpll_gpll_p, 0, 35, 0, 5, 6, 2),
955
	CDIV(0, "pclk_gmac_c", "pclk_gmac", 0, 25, 8, 3),
956

957
	/* CRU_CLKSEL_CON26 */
958
	CDIV(0, "clk_mac2phy_out_c", "clk_mac2phy", 0, 26, 8, 2),
959
	COMP(0, "clk_mac2phy_src_c", pll_src_cpll_gpll_p, 0, 26, 0, 5, 7, 1),
960

961
	/* CRU_CLKSEL_CON27 */
962
	COMP(0, "clk_mac2io_src_c", pll_src_cpll_gpll_p, 0, 27, 0, 5, 7, 1),
963
	COMP(0, "clk_mac2io_out_c", pll_src_cpll_gpll_p, 0, 27, 8, 5, 15, 1),
964

965
	/* CRU_CLKSEL_CON28 */
966
	COMP(ACLK_PERI_PRE, "aclk_peri_pre", pll_src_cpll_gpll_hdmiphy_p, 0, 28, 0, 5, 6, 2),
967

968
	/* CRU_CLKSEL_CON29 */
969
	CDIV(0, "pclk_peri_c", "aclk_peri_pre", 0, 29, 0, 2),
970
	CDIV(0, "hclk_peri_c", "aclk_peri_pre", 0, 29, 4, 3),
971

972
	/* CRU_CLKSEL_CON30 */
973
	COMP(0, "clk_sdmmc_c", pll_src_cpll_gpll_xin24m_usb480m_p, 0, 30, 0, 8, 8, 2),
974

975
	/* CRU_CLKSEL_CON31 */
976
	COMP(0, "clk_sdio_c", pll_src_cpll_gpll_xin24m_usb480m_p, 0, 31, 0, 8, 8, 2),
977

978
	/* CRU_CLKSEL_CON32 */
979
	COMP(0, "clk_emmc_c", pll_src_cpll_gpll_xin24m_usb480m_p, 0, 32, 0, 8, 8, 2),
980

981
	/* CRU_CLKSEL_CON33 */
982
	COMP(0, "clk_usb3otg_suspend_c", xin24m_rtc32k_p, 0, 33, 0, 10, 15, 1),
983

984
	/* CRU_CLKSEL_CON34 */
985
	COMP(0, "clk_i2c0_c", pll_src_cpll_gpll_p, 0, 34, 0, 7, 7, 1),
986
	COMP(0, "clk_i2c1_c", pll_src_cpll_gpll_p, 0, 34, 8, 7, 15, 1),
987

988
	/* CRU_CLKSEL_CON35 */
989
	COMP(0, "clk_i2c2_c", pll_src_cpll_gpll_p, 0, 35, 0, 7, 7, 1),
990
	COMP(0, "clk_i2c3_c", pll_src_cpll_gpll_p, 0, 35, 8, 7, 15, 1),
991

992
	/* CRU_CLKSEL_CON36 */
993
	COMP(0, "aclk_rga_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 36, 8, 5, 14, 2),
994
	COMP(0, "sclk_rga_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 36, 0, 5, 6, 2),
995

996
	/* CRU_CLKSEL_CON37 */
997
	COMP(0, "aclk_vio_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 37, 0, 5, 6, 2),
998
	CDIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_vio_pre", 0, 37, 8, 5),
999

1000
	/* CRU_CLKSEL_CON38 */
1001
	COMP(0, "clk_rtc32k_c", pll_src_cpll_gpll_xin24m_p, 0, 38, 0, 14, 14, 2),
1002

1003
	/* CRU_CLKSEL_CON39 */
1004
	COMP(0, "aclk_vop_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 39, 0, 5, 6, 2),
1005

1006
	/* CRU_CLKSEL_CON40 */
1007
	COMP(0, "vop_dclk_src_c", pll_src_cpll_gpll_p, 0, 40, 8, 8, 0, 1),
1008
	CDIV(DCLK_HDMIPHY, "hdmiphy_div", "vop_dclk_src", 0, 40, 3, 3),
1009
	/* MUX vop_dclk_frac_sel */
1010
	MUX(DCLK_LCDC, "vop_dclk", mux_dclk_lcdc_p, 0, 40, 1, 1),
1011

1012
	/* CRU_CLKSEL_CON41 */
1013
	/* FRACT dclk_vop_frac_div_con */
1014

1015
	/* CRU_CLKSEL_CON42 */
1016
	MUX(0, "clk_cif_pll", pll_src_cpll_gpll_p, 0, 42, 7, 1),
1017
	COMP(0, "clk_cif_src_c", mux_cif_p, 0, 42, 0, 5, 5, 1),
1018

1019
	/* CRU_CLKSEL_CON43 */
1020
	COMP(0, "clk_sdmmc_ext_c", pll_src_cpll_gpll_xin24m_usb480m_p, 0, 43, 0, 8, 8, 2),
1021

1022
	/* CRU_CLKSEL_CON44 */
1023
	COMP(0, "aclk_gpu_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 44, 0, 5, 6, 2),
1024

1025
	/* CRU_CLKSEL_CON45 */
1026
	MUX(SCLK_REF_USB3OTG, "clk_ref_usb3otg", mux_ref_usb3otg_p, 0, 45, 8, 1),
1027
	COMP(0, "clk_ref_usb3otg_src_c", pll_src_cpll_gpll_p, 0, 45, 0, 7, 7, 1),
1028

1029
	/* CRU_CLKSEL_CON46 */
1030
	/* Unused */
1031

1032
	/* CRU_CLKSEL_CON47 */
1033
	/* Unused */
1034

1035
	/* CRU_CLKSEL_CON48 */
1036
	COMP(0, "sclk_cabac_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 48, 8, 5, 14, 2),
1037
	COMP(0, "aclk_rkvdec_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 48, 0, 5, 6, 2),
1038

1039
	/* CRU_CLKSEL_CON49 */
1040
	COMP(0, "sclk_vdec_core_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 49, 0, 5, 6, 2),
1041

1042
	/* CRU_CLKSEL_CON50 */
1043
	COMP(0, "aclk_vpu_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 50, 0, 5, 6, 2),
1044

1045
	/* CRU_CLKSEL_CON51 */
1046
	COMP(0, "sclk_venc_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 51, 8, 5, 14, 2),
1047
	COMP(0, "aclk_rkvenc_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 51, 0, 5, 6, 2),
1048

1049
	/* CRU_CLKSEL_CON52 */
1050
	COMP(0, "sclk_venc_dsp_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 51, 8, 5, 14, 2),
1051
	COMP(0, "sclk_wifi_c", pll_src_cpll_gpll_usb480m_p, 0, 51, 0, 6, 6, 2),
1052

1053
	/* GRF_SOC_CON4 */
1054
	MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, 0, RK3328_GRF_SOC_CON4, 14, 1),
1055

1056
	/* GRF_MAC_CON1 */
1057
	MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_p, 0, RK3328_GRF_MAC_CON1, 10, 1),
1058

1059
	/* GRF_MAC_CON2 */
1060
	MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_p, 0, RK3328_GRF_MAC_CON2, 10, 1),
1061

1062
	/*
1063
	 * This clock is controlled in the secure world
1064
	 */
1065
	FFACT(PCLK_WDT, "pclk_wdt", "pclk_bus", 1, 1),
1066
};
1067

1068
static int
1069
rk3328_cru_probe(device_t dev)
1070
{
1071

1072
	if (!ofw_bus_status_okay(dev))
1073
		return (ENXIO);
1074

1075
	if (ofw_bus_is_compatible(dev, "rockchip,rk3328-cru")) {
1076
		device_set_desc(dev, "Rockchip RK3328 Clock and Reset Unit");
1077
		return (BUS_PROBE_DEFAULT);
1078
	}
1079

1080
	return (ENXIO);
1081
}
1082

1083
static int
1084
rk3328_cru_attach(device_t dev)
1085
{
1086
	struct rk_cru_softc *sc;
1087

1088
	sc = device_get_softc(dev);
1089
	sc->dev = dev;
1090

1091
	sc->gates = rk3328_gates;
1092
	sc->ngates = nitems(rk3328_gates);
1093

1094
	sc->clks = rk3328_clks;
1095
	sc->nclks = nitems(rk3328_clks);
1096

1097
	sc->reset_offset = 0x300;
1098
	sc->reset_num = 184;
1099

1100
	return (rk_cru_attach(dev));
1101
}
1102

1103
static device_method_t rk3328_cru_methods[] = {
1104
	/* Device interface */
1105
	DEVMETHOD(device_probe,		rk3328_cru_probe),
1106
	DEVMETHOD(device_attach,	rk3328_cru_attach),
1107

1108
	DEVMETHOD_END
1109
};
1110

1111
DEFINE_CLASS_1(rk3328_cru, rk3328_cru_driver, rk3328_cru_methods,
1112
  sizeof(struct rk_cru_softc), rk_cru_driver);
1113

1114
EARLY_DRIVER_MODULE(rk3328_cru, simplebus, rk3328_cru_driver, 0, 0,
1115
    BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
1116

1117
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