Path: blob/main/sys/dev/clk/rockchip/rk3399_cru.c
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/*-1* SPDX-License-Identifier: BSD-2-Clause2*3* Copyright (c) 2018 Emmanuel Vadot <[email protected]>4* Copyright (c) 2018 Val Packett <[email protected]>5*6* Redistribution and use in source and binary forms, with or without7* modification, are permitted provided that the following conditions8* are met:9* 1. Redistributions of source code must retain the above copyright10* notice, this list of conditions and the following disclaimer.11* 2. Redistributions in binary form must reproduce the above copyright12* notice, this list of conditions and the following disclaimer in the13* documentation and/or other materials provided with the distribution.14*15* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR16* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES17* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.18* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,19* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,20* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;21* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED22* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,23* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY24* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF25* SUCH DAMAGE.26*/2728#include <sys/param.h>29#include <sys/systm.h>30#include <sys/bus.h>31#include <sys/rman.h>32#include <sys/kernel.h>33#include <sys/module.h>34#include <machine/bus.h>3536#include <dev/fdt/simplebus.h>3738#include <dev/ofw/ofw_bus.h>39#include <dev/ofw/ofw_bus_subr.h>4041#include <dev/clk/clk_div.h>42#include <dev/clk/clk_fixed.h>43#include <dev/clk/clk_mux.h>4445#include <dev/clk/rockchip/rk_cru.h>4647#include <dev/clk/rockchip/rk3399_cru_dt.h>4849#define CRU_CLKSEL_CON(x) (0x100 + (x) * 0x4)50#define CRU_CLKGATE_CON(x) (0x300 + (x) * 0x4)5152/* GATES */5354static struct rk_cru_gate rk3399_gates[] = {55/* CRU_CLKGATE_CON0 */56/* 15-8 unused */57GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0, 7),58GATE(0, "pclk_dbg_core_l", "pclk_dbg_core_l_c", 0, 6),59GATE(0, "atclk_core_l", "atclk_core_l_c", 0, 5),60GATE(0, "aclkm_core_l", "aclkm_core_l_c", 0, 4),61GATE(0, "clk_core_l_gpll_src", "gpll", 0, 3),62GATE(0, "clk_core_l_dpll_src", "dpll", 0, 2),63GATE(0, "clk_core_l_bpll_src", "bpll", 0, 1),64GATE(0, "clk_core_l_lpll_src", "lpll", 0, 0),6566/* CRU_CLKGATE_CON1 */67/* 15 - 8 unused */68GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 1, 7),69GATE(0, "pclk_dbg_core_b","pclk_dbg_core_b_c", 1, 6),70GATE(0, "atclk_core_b", "atclk_core_b_c", 1, 5),71GATE(0, "aclkm_core_b", "aclkm_core_b_c", 1, 4),72GATE(0, "clk_core_b_gpll_src", "gpll", 1, 3),73GATE(0, "clk_core_b_dpll_src", "dpll", 1, 2),74GATE(0, "clk_core_b_bpll_src", "bpll", 1, 1),75GATE(0, "clk_core_b_lpll_src", "lpll", 1, 0),7677/* CRU_CLKGATE_CON2 */78/* 15 - 11 unused */79GATE(0, "npll_cs", "npll", 2, 10),80GATE(0, "gpll_cs", "gpll", 2, 9),81GATE(0, "cpll_cs", "cpll", 2, 8),82GATE(SCLK_CCI_TRACE, "clk_cci_trace", "clk_cci_trace_c", 2, 7),83GATE(0, "gpll_cci_trace", "gpll", 2, 6),84GATE(0, "cpll_cci_trace", "cpll", 2, 5),85GATE(0, "aclk_cci_pre", "aclk_cci_pre_c", 2, 4),86GATE(0, "vpll_aclk_cci_src", "vpll", 2, 3),87GATE(0, "npll_aclk_cci_src", "npll", 2, 2),88GATE(0, "gpll_aclk_cci_src", "gpll", 2, 1),89GATE(0, "cpll_aclk_cci_src", "cpll", 2, 0),9091/* CRU_CLKGATE_CON3 */92/* 15 - 8 unused */93GATE(0, "aclk_center", "aclk_center_c", 3, 7),94/* 6 unused */95/* 5 unused */96GATE(PCLK_DDR, "pclk_ddr", "pclk_ddr_c", 3, 4),97GATE(0, "clk_ddrc_gpll_src", "gpll", 3, 3),98GATE(0, "clk_ddrc_dpll_src", "dpll", 3, 2),99GATE(0, "clk_ddrc_bpll_src", "bpll", 3, 1),100GATE(0, "clk_ddrc_lpll_src", "lpll", 3, 0),101102/* CRU_CLKGATE_CON4 */103/* 15 - 12 unused */104GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 4, 11),105GATE(0, "clk_rga_core", "clk_rga_core_c", 4, 10),106GATE(0, "hclk_rga_pre", "hclk_rga_pre_c", 4, 9),107GATE(0, "aclk_rga_pre", "aclk_rga_pre_c", 4, 8),108GATE(0, "hclk_iep_pre", "hclk_iep_pre_c", 4, 7),109GATE(0, "aclk_iep_pre", "aclk_iep_pre_c", 4, 6),110GATE(SCLK_VDU_CA, "clk_vdu_ca", "clk_vdu_ca_c", 4, 5),111GATE(SCLK_VDU_CORE, "clk_vdu_core", "clk_vdu_core_c", 4, 4),112GATE(0, "hclk_vdu_pre", "hclk_vdu_pre_c", 4, 3),113GATE(0, "aclk_vdu_pre", "aclk_vdu_pre_c", 4, 2),114GATE(0, "hclk_vcodec_pre", "hclk_vcodec_pre_c", 4, 1),115GATE(0, "aclk_vcodec_pre", "aclk_vcodec_pre_c", 4, 0),116117/* CRU_CLKGATE_CON5 */118/* 15 - 10 unused */119GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 5, 9),120GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 5, 8),121GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 5, 7),122GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 5, 6),123GATE(SCLK_MAC, "clk_gmac", "clk_gmac_c", 5, 5),124GATE(PCLK_PERIHP, "pclk_perihp", "pclk_perihp_c", 5, 4),125GATE(HCLK_PERIHP, "hclk_perihp", "hclk_perihp_c", 5, 3),126GATE(ACLK_PERIHP, "aclk_perihp", "aclk_perihp_c", 5, 2),127GATE(0, "cpll_aclk_perihp_src", "cpll", 5, 1),128GATE(0, "gpll_aclk_perihp_src", "gpll", 5, 0),129130/* CRU_CLKGATE_CON6 */131/* 15 unused */132GATE(SCLK_EMMC, "clk_emmc", "clk_emmc_c", 6, 14),133GATE(0, "cpll_aclk_emmc_src", "cpll", 6, 13),134GATE(0, "gpll_aclk_emmc_src", "gpll", 6, 12),135GATE(0, "pclk_gmac_pre", "pclk_gmac_pre_c", 6, 11),136GATE(0, "aclk_gmac_pre", "aclk_gmac_pre_c", 6, 10),137GATE(0, "cpll_aclk_gmac_src", "cpll", 6, 9),138GATE(0, "gpll_aclk_gmac_src", "gpll", 6, 8),139/* 7 unused */140GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", 6, 6),141GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", 6, 5),142GATE(SCLK_HSICPHY, "clk_hsicphy", "clk_hsicphy_c", 6, 4),143GATE(0, "clk_pcie_core_cru", "clk_pcie_core_cru_c", 6, 3),144GATE(SCLK_PCIE_PM, "clk_pcie_pm", "clk_pcie_pm_c", 6, 2),145GATE(SCLK_SDMMC, "clk_sdmmc", "clk_sdmmc_c", 6, 1),146GATE(SCLK_SDIO, "clk_sdio", "clk_sdio_c", 6, 0),147148/* CRU_CLKGATE_CON7 */149/* 15 - 10 unused */150GATE(FCLK_CM0S, "fclk_cm0s", "fclk_cm0s_c", 7, 9),151GATE(SCLK_CRYPTO1, "clk_crypto1", "clk_crypto1_c", 7, 8),152GATE(SCLK_CRYPTO0, "clk_crypto0", "clk_crypto0_c", 7, 7),153GATE(0, "cpll_fclk_cm0s_src", "cpll", 7, 6),154GATE(0, "gpll_fclk_cm0s_src", "gpll", 7, 5),155GATE(PCLK_PERILP0, "pclk_perilp0", "pclk_perilp0_c", 7, 4),156GATE(HCLK_PERILP0, "hclk_perilp0", "hclk_perilp0_c", 7, 3),157GATE(ACLK_PERILP0, "aclk_perilp0", "aclk_perilp0_c", 7, 2),158GATE(0, "cpll_aclk_perilp0_src", "cpll", 7, 1),159GATE(0, "gpll_aclk_perilp0_src", "gpll", 7, 0),160161/* CRU_CLKGATE_CON8 */162GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", 8, 15),163GATE(0, "clk_spdif_frac", "clk_spdif_frac_c", 8, 14),164GATE(0, "clk_spdif_div", "clk_spdif_div_c", 8, 13),165GATE(SCLK_I2S_8CH_OUT, "clk_i2sout", "clk_i2sout_c", 8, 12),166GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", 8, 11),167GATE(0, "clk_i2s2_frac", "clk_i2s2_frac_c", 8, 10),168GATE(0, "clk_i2s2_div", "clk_i2s2_div_c", 8, 9),169GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", 8, 8),170GATE(0, "clk_i2s1_frac", "clk_i2s1_frac_c", 8, 7),171GATE(0, "clk_i2s1_div", "clk_i2s1_div_c", 8, 6),172GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", 8, 5),173GATE(0, "clk_i2s0_frac","clk_i2s0_frac_c", 8, 4),174GATE(0, "clk_i2s0_div","clk_i2s0_div_c", 8, 3),175GATE(PCLK_PERILP1, "pclk_perilp1", "pclk_perilp1_c", 8, 2),176GATE(HCLK_PERILP1, "cpll_hclk_perilp1_src", "cpll", 8, 1),177GATE(0, "gpll_hclk_perilp1_src", "gpll", 8, 0),178179/* CRU_CLKGATE_CON9 */180GATE(SCLK_SPI4, "clk_spi4", "clk_spi4_c", 9, 15),181GATE(SCLK_SPI2, "clk_spi2", "clk_spi2_c", 9, 14),182GATE(SCLK_SPI1, "clk_spi1", "clk_spi1_c", 9, 13),183GATE(SCLK_SPI0, "clk_spi0", "clk_spi0_c", 9, 12),184GATE(SCLK_SARADC, "clk_saradc", "clk_saradc_c", 9, 11),185GATE(SCLK_TSADC, "clk_tsadc", "clk_tsadc_c", 9, 10),186/* 9 - 8 unused */187GATE(0, "clk_uart3_frac", "clk_uart3_frac_c", 9, 7),188GATE(0, "clk_uart3_div", "clk_uart3_div_c", 9, 6),189GATE(0, "clk_uart2_frac", "clk_uart2_frac_c", 9, 5),190GATE(0, "clk_uart2_div", "clk_uart2_div_c", 9, 4),191GATE(0, "clk_uart1_frac", "clk_uart1_frac_c", 9, 3),192GATE(0, "clk_uart1_div", "clk_uart1_div_c", 9, 2),193GATE(0, "clk_uart0_frac", "clk_uart0_frac_c", 9, 1),194GATE(0, "clk_uart0_div", "clk_uart0_div_c", 9, 0),195196/* CRU_CLKGATE_CON10 */197GATE(SCLK_VOP1_PWM, "clk_vop1_pwm", "clk_vop1_pwm_c", 10, 15),198GATE(SCLK_VOP0_PWM, "clk_vop0_pwm", "clk_vop0_pwm_c", 10, 14),199GATE(DCLK_VOP0_DIV, "dclk_vop0_div", "dclk_vop0_div_c", 10, 12),200GATE(DCLK_VOP1_DIV, "dclk_vop1_div", "dclk_vop1_div_c", 10, 13),201GATE(0, "hclk_vop1_pre", "hclk_vop1_pre_c", 10, 11),202GATE(ACLK_VOP1_PRE, "aclk_vop1_pre", "aclk_vop1_pre_c", 10, 10),203GATE(0, "hclk_vop0_pre", "hclk_vop0_pre_c", 10, 9),204GATE(ACLK_VOP0_PRE, "aclk_vop0_pre", "aclk_vop0_pre_c", 10, 8),205GATE(0, "clk_cifout_src", "clk_cifout_src_c", 10, 7),206GATE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", "clk_spdif_rec_dptx_c", 10, 6),207GATE(SCLK_I2C7, "clk_i2c7", "clk_i2c7_c", 10, 5),208GATE(SCLK_I2C3, "clk_i2c3", "clk_i2c3_c", 10, 4),209GATE(SCLK_I2C6, "clk_i2c6", "clk_i2c6_c", 10, 3),210GATE(SCLK_I2C2, "clk_i2c2", "clk_i2c2_c", 10, 2),211GATE(SCLK_I2C5, "clk_i2c5", "clk_i2c5_c", 10, 1),212GATE(SCLK_I2C1, "clk_i2c1", "clk_i2c1_c", 10, 0),213214/* CRU_CLKGATE_CON11 */215GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 11, 15),216GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 11, 14),217/* 13-12 unused */218GATE(PCLK_EDP, "pclk_edp", "pclk_edp_c", 11, 11),219GATE(PCLK_HDCP, "pclk_hdcp", "pclk_hdcp_c", 11, 10),220/* 9 unuwsed */221GATE(SCLK_DP_CORE, "clk_dp_core", "clk_dp_core_c", 11, 8),222GATE(SCLK_HDMI_CEC, "clk_hdmi_cec", "clk_hdmi_cec_c", 11, 7),223GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 11, 6),224GATE(SCLK_ISP1, "clk_isp1", "clk_isp1_c", 11, 5),225GATE(SCLK_ISP0, "clk_isp0", "clk_isp0_c", 11, 4),226GATE(HCLK_HDCP, "hclk_hdcp", "hclk_hdcp_c", 11, 3),227GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_c", 11, 2),228GATE(PCLK_VIO, "pclk_vio", "pclk_vio_c", 11, 1),229GATE(ACLK_VIO, "aclk_vio", "aclk_vio_c", 11, 0),230231/* CRU_CLKGATE_CON12 */232/* 15 - 14 unused */233GATE(HCLK_SD, "hclk_sd", "hclk_sd_c", 12, 13),234GATE(ACLK_GIC_PRE, "aclk_gic_pre", "aclk_gic_pre_c", 12, 12),235GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_c", 12, 11),236GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_c", 12, 10),237GATE(HCLK_ISP0, "hclk_isp0", "hclk_isp0_c", 12, 9),238GATE(ACLK_ISP0, "aclk_isp0", "aclk_isp0_c", 12, 8),239/* 7 unused */240GATE(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "clk_pciephy_ref100m_c", 12, 6),241/* 5 unused */242GATE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", "clk_usb3otg1_suspend_c", 12, 4),243GATE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", "clk_usb3otg0_suspend_c", 12, 3),244GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 12, 2),245GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 12, 1),246GATE(ACLK_USB3, "aclk_usb3", "aclk_usb3_c", 12, 0),247248/* CRU_CLKGATE_CON13 */249GATE(SCLK_TESTCLKOUT2, "clk_testout2", "clk_testout2_c", 13, 15),250GATE(SCLK_TESTCLKOUT1, "clk_testout1", "clk_testout1_c", 13, 14),251GATE(SCLK_SPI5, "clk_spi5", "clk_spi5_c", 13, 13),252GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 13, 12),253GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 13, 12),254GATE(0, "clk_test", "clk_test_c", 13, 11),255/* 10 unused */256GATE(0, "clk_test_frac", "clk_test_frac_c", 13, 9),257/* 8 unused */258GATE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", "clk_uphy1_tcpdcore_c", 13, 7),259GATE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", "clk_uphy1_tcpdphy_ref_c", 13, 6),260GATE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", "clk_uphy0_tcpdcore_c", 13, 5),261GATE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", "clk_uphy0_tcpdphy_ref_c", 13, 4),262/* 3 - 2 unused */263GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 13, 1),264GATE(0, "aclk_gpu_pre", "aclk_gpu_pre_c", 13, 0),265266/* CRU_CLKGATE_CON14 */267/* 15 - 14 unused */268GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", 14, 13),269GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", 14, 12),270GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", 14, 11),271GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", 14, 10),272GATE(0, "clk_dbg_pd_core_l", "armclkl", 14, 9),273/* 8 - 7 unused */274GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", 14, 6),275GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", 14, 5),276GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", 14, 4),277GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", 14, 3),278GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", 14, 2),279GATE(0, "clk_dbg_pd_core_b", "armclkb", 14, 1),280/* 0 unused */281282/* CRU_CLKGATE_CON15 */283/* 15 - 8 unused */284GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", 15, 7),285GATE(0, "clk_dbg_noc", "clk_cs", 15, 6),286GATE(0, "clk_dbg_cxcs", "clk_cs", 15, 5),287GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", 15, 4),288GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", 15, 3),289GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", 15, 2),290GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", 15, 1),291GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", 15, 0),292293/* CRU_CLKGATE_CON16 */294/* 15 - 12 unused */295GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", 16, 11),296GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 16, 10),297GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", 16, 9),298GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 16, 8),299/* 7 - 4 unused */300GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", 16, 3),301GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 16, 2),302GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", 16, 1),303GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 16, 0),304305/* CRU_CLKGATE_CON17 */306/* 15 - 12 unused */307GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", 17, 11),308GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 17, 10),309GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", 17, 9),310GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 17, 8),311GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", 17, 3),312GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 17, 2),313GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", 17, 1),314GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 17, 0),315316/* CRU_CLKGATE_CON18 */317GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", 18, 15),318GATE(0, "clk_ddr_mon_timer", "xin24m", 18, 14),319GATE(0, "clk_ddr_mon", "clk_ddrc_div2", 18, 13),320GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 18, 12),321GATE(0, "clk_ddr_cic", "clk_ddrc_div2", 18, 11),322GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", 18, 10),323GATE(0, "clk_ddrcfg_msch1", "clk_ddrc_div2", 18, 9),324GATE(0, "clk_ddrphy1", "clk_ddrc_div2", 18, 8),325GATE(0, "clk_ddrphy_ctrl1", "clk_ddrc_div2", 18, 7),326GATE(0, "clk_ddrc1", "clk_ddrc_div2", 18, 6),327GATE(0, "clk_ddr1_msch", "clk_ddrc_div2", 18, 5),328GATE(0, "clk_ddrcfg_msch0", "clk_ddrc_div2", 18, 4),329GATE(0, "clk_ddrphy0", "clk_ddrc_div2", 18, 3),330GATE(0, "clk_ddrphy_ctrl0", "clk_ddrc_div2", 18, 2),331GATE(0, "clk_ddrc0", "clk_ddrc_div2", 18, 1),332333/* CRU_CLKGATE_CON19 */334/* 15 - 3 unused */335GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", 19, 2),336GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", 19, 1),337GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", 19, 0),338339/* CRU_CLKGATE_CON20 */340GATE(0, "hclk_ahb1tom", "hclk_perihp", 20, 15),341GATE(0, "pclk_perihp_noc", "pclk_perihp", 20, 14),342GATE(0, "hclk_perihp_noc", "hclk_perihp", 20, 13),343GATE(0, "aclk_perihp_noc", "aclk_perihp", 20, 12),344GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 20, 11),345GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 20, 10),346GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 20, 9),347GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 20, 8),348GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 20, 7),349GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 20, 6),350GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 20, 5),351GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", 20, 4),352GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 20, 2),353/* 1 - 0 unused */354355/* CRU_CLKGATE_CON21 */356/* 15 - 10 unused */357GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", 21, 9),358GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", 21, 8),359/* 7 unused */360GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", 21, 6),361GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", 21, 5),362GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", 21, 4),363GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", 21, 3),364GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", 21, 2),365GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", 21, 1),366GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", 21, 0),367368/* CRU_CLKGATE_CON22 */369GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 22, 15),370GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 22, 14),371GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 22, 13),372GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 22, 12),373GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 22, 11),374GATE(PCLK_I2C3, "pclk_i2c3", "pclk_perilp1", 22, 10),375GATE(PCLK_I2C2, "pclk_i2c2", "pclk_perilp1", 22, 9),376GATE(PCLK_I2C6, "pclk_i2c6", "pclk_perilp1", 22, 8),377GATE(PCLK_I2C5, "pclk_i2c5", "pclk_perilp1", 22, 7),378GATE(PCLK_I2C1, "pclk_i2c1", "pclk_perilp1", 22, 6),379GATE(PCLK_I2C7, "pclk_i2c7", "pclk_perilp1", 22, 5),380GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 22, 3),381GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 22, 2),382GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 22, 1),383GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 22, 0),384385/* CRU_CLKGATE_CON23 */386/* 15 - 14 unused */387GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 23, 13),388GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 23, 12),389GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 23, 11),390GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 23, 10),391GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 23, 9),392GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 23, 8),393GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", 23, 7),394GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", 23, 6),395GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", 23, 5),396GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", 23, 4),397GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", 23, 3),398GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", 23, 2),399GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", 23, 1),400GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", 23, 0),401402/* CRU_CLKGATE_CON24 */403GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 24, 15),404GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 24, 14),405GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 24, 13),406GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 24, 11),407GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 24, 10),408GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 24, 9),409GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 24, 8),410/* 7 - unused */411GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 24, 6),412GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 24, 5),413GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", 24, 4),414/* 3 - 0 unused */415416/* CRU_CLKGATE_CON25 */417/* 15 - 13 unused */418GATE(0, "hclk_sdio_noc", "hclk_perilp1", 25, 12),419GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", 25, 11),420GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 25, 10),421GATE(0, "hclk_perilp1_noc", "hclk_perilp1", 25, 9),422GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", 25, 8),423GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", 25, 7),424GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 25, 6),425GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 25, 5),426/* 4 - 0 unused */427428/* CRU_CLKGATE_CON26 */429/* 15 - 12 unused */430GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 26, 11),431GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 26, 10),432GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 26, 9),433GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 26, 8),434GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 26, 7),435GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 26, 6),436GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 26, 5),437GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 26, 4),438GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 26, 3),439GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 26, 2),440GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 26, 1),441GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 26, 0),442443/* CRU_CLKGATE_CON27 */444/* 15 - 9 unused */445GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 27, 8),446GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 27, 7),447GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 27, 6),448GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 27, 5),449GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 27, 4),450GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", 27, 3),451GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", 27, 2),452GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", 27, 1),453GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", 27, 0),454455/* CRU_CLKGATE_CON28 */456/* 15 - 8 unused */457GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 28, 7),458GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 28, 6),459GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", 28, 5),460GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", 28, 4),461GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 28, 3),462GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 28, 2),463GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", 28, 1),464GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", 28, 0),465466/* CRU_CLKGATE_CON29 */467/* 15 - 13 unused */468GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", 29, 12),469GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 29, 11),470GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 29, 10),471GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 29, 9),472GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 29, 8),473GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 29, 7),474GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 29, 6),475GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", 29, 5),476GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", 29, 4),477GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", 29, 3),478GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 29, 2),479GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 29, 1),480GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", 29, 0),481482/* CRU_CLKGATE_CON30 */483/* 15 - 12 unused */484GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 30, 11),485GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 30, 10),486/* 9 unused */487GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 30, 8),488/* 7 - 5 unused */489GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 30, 4),490GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 30, 3),491GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 30, 2),492GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 30, 1),493GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", 30, 0),494495/* CRU_CLKGATE_CON31 */496/* 15 - 11 unused */497GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", 31, 10),498GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", 31, 9),499GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 31, 8),500GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 31, 7),501GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 31, 6),502GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 31, 5),503GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 31, 4),504GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 31, 3),505GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", 31, 2),506GATE(PCLK_GRF, "pclk_grf", "pclk_alive", 31, 1),507/* 0 unused */508509/* CRU_CLKGATE_CON32 */510/* 15 - 14 unused */511GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 32, 13),512GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", 32, 12),513/* 11 unused */514GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", 32, 10),515GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", 32, 9),516GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", 32, 8),517/* 7 - 5 unused */518GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 32, 4),519GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", 32, 3),520GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 32, 2),521GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", 32, 1),522GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 32, 0),523524/* CRU_CLKGATE_CON33 */525/* 15 - 10 unused */526GATE(0, "hclk_sdmmc_noc", "hclk_sd", 33, 9),527GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 33, 8),528GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", 33, 5),529GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", 33, 4),530GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", 33, 3),531GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", 33, 2),532GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", 33, 1),533GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", 33, 0),534535/* CRU_CLKGATE_CON34 */536/* 15 - 7 unused */537GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", 34, 6),538GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 34, 5),539GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 34, 4),540GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 34, 3),541GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 34, 2),542GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 34, 1),543GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 34, 0),544};545546#define PLL_RATE(_hz, _ref, _fb, _post1, _post2, _dspd) \547{ \548.freq = _hz, \549.refdiv = _ref, \550.fbdiv = _fb, \551.postdiv1 = _post1, \552.postdiv2 = _post2, \553.dsmpd = _dspd, \554}555556static struct rk_clk_pll_rate rk3399_pll_rates[] = {557/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */558PLL_RATE(2208000000, 1, 92, 1, 1, 1),559PLL_RATE(2184000000, 1, 91, 1, 1, 1),560PLL_RATE(2160000000, 1, 90, 1, 1, 1),561PLL_RATE(2136000000, 1, 89, 1, 1, 1),562PLL_RATE(2112000000, 1, 88, 1, 1, 1),563PLL_RATE(2088000000, 1, 87, 1, 1, 1),564PLL_RATE(2064000000, 1, 86, 1, 1, 1),565PLL_RATE(2040000000, 1, 85, 1, 1, 1),566PLL_RATE(2016000000, 1, 84, 1, 1, 1),567PLL_RATE(1992000000, 1, 83, 1, 1, 1),568PLL_RATE(1968000000, 1, 82, 1, 1, 1),569PLL_RATE(1944000000, 1, 81, 1, 1, 1),570PLL_RATE(1920000000, 1, 80, 1, 1, 1),571PLL_RATE(1896000000, 1, 79, 1, 1, 1),572PLL_RATE(1872000000, 1, 78, 1, 1, 1),573PLL_RATE(1848000000, 1, 77, 1, 1, 1),574PLL_RATE(1824000000, 1, 76, 1, 1, 1),575PLL_RATE(1800000000, 1, 75, 1, 1, 1),576PLL_RATE(1776000000, 1, 74, 1, 1, 1),577PLL_RATE(1752000000, 1, 73, 1, 1, 1),578PLL_RATE(1728000000, 1, 72, 1, 1, 1),579PLL_RATE(1704000000, 1, 71, 1, 1, 1),580PLL_RATE(1680000000, 1, 70, 1, 1, 1),581PLL_RATE(1656000000, 1, 69, 1, 1, 1),582PLL_RATE(1632000000, 1, 68, 1, 1, 1),583PLL_RATE(1608000000, 1, 67, 1, 1, 1),584PLL_RATE(1600000000, 3, 200, 1, 1, 1),585PLL_RATE(1584000000, 1, 66, 1, 1, 1),586PLL_RATE(1560000000, 1, 65, 1, 1, 1),587PLL_RATE(1536000000, 1, 64, 1, 1, 1),588PLL_RATE(1512000000, 1, 63, 1, 1, 1),589PLL_RATE(1488000000, 1, 62, 1, 1, 1),590PLL_RATE(1464000000, 1, 61, 1, 1, 1),591PLL_RATE(1440000000, 1, 60, 1, 1, 1),592PLL_RATE(1416000000, 1, 59, 1, 1, 1),593PLL_RATE(1392000000, 1, 58, 1, 1, 1),594PLL_RATE(1368000000, 1, 57, 1, 1, 1),595PLL_RATE(1344000000, 1, 56, 1, 1, 1),596PLL_RATE(1320000000, 1, 55, 1, 1, 1),597PLL_RATE(1296000000, 1, 54, 1, 1, 1),598PLL_RATE(1272000000, 1, 53, 1, 1, 1),599PLL_RATE(1248000000, 1, 52, 1, 1, 1),600PLL_RATE(1200000000, 1, 50, 1, 1, 1),601PLL_RATE(1188000000, 2, 99, 1, 1, 1),602PLL_RATE(1104000000, 1, 46, 1, 1, 1),603PLL_RATE(1100000000, 12, 550, 1, 1, 1),604PLL_RATE(1008000000, 1, 84, 2, 1, 1),605PLL_RATE(1000000000, 1, 125, 3, 1, 1),606PLL_RATE( 984000000, 1, 82, 2, 1, 1),607PLL_RATE( 960000000, 1, 80, 2, 1, 1),608PLL_RATE( 936000000, 1, 78, 2, 1, 1),609PLL_RATE( 912000000, 1, 76, 2, 1, 1),610PLL_RATE( 900000000, 4, 300, 2, 1, 1),611PLL_RATE( 888000000, 1, 74, 2, 1, 1),612PLL_RATE( 864000000, 1, 72, 2, 1, 1),613PLL_RATE( 840000000, 1, 70, 2, 1, 1),614PLL_RATE( 816000000, 1, 68, 2, 1, 1),615PLL_RATE( 800000000, 1, 100, 3, 1, 1),616PLL_RATE( 700000000, 6, 350, 2, 1, 1),617PLL_RATE( 696000000, 1, 58, 2, 1, 1),618PLL_RATE( 676000000, 3, 169, 2, 1, 1),619PLL_RATE( 600000000, 1, 75, 3, 1, 1),620PLL_RATE( 594000000, 1, 99, 4, 1, 1),621PLL_RATE( 533250000, 8, 711, 4, 1, 1),622PLL_RATE( 504000000, 1, 63, 3, 1, 1),623PLL_RATE( 500000000, 6, 250, 2, 1, 1),624PLL_RATE( 408000000, 1, 68, 2, 2, 1),625PLL_RATE( 312000000, 1, 52, 2, 2, 1),626PLL_RATE( 297000000, 1, 99, 4, 2, 1),627PLL_RATE( 216000000, 1, 72, 4, 2, 1),628PLL_RATE( 148500000, 1, 99, 4, 4, 1),629PLL_RATE( 106500000, 1, 71, 4, 4, 1),630PLL_RATE( 96000000, 1, 64, 4, 4, 1),631PLL_RATE( 74250000, 2, 99, 4, 4, 1),632PLL_RATE( 65000000, 1, 65, 6, 4, 1),633PLL_RATE( 54000000, 1, 54, 6, 4, 1),634PLL_RATE( 27000000, 1, 27, 6, 4, 1),635{},636};637638static struct rk_clk_armclk_rates rk3399_cpu_l_rates[] = {639{1800000000, 1},640{1704000000, 1},641{1608000000, 1},642{1512000000, 1},643{1488000000, 1},644{1416000000, 1},645{1200000000, 1},646{1008000000, 1},647{ 816000000, 1},648{ 696000000, 1},649{ 600000000, 1},650{ 408000000, 1},651{ 312000000, 1},652{ 216000000, 1},653{ 96000000, 1},654};655656static struct rk_clk_armclk_rates rk3399_cpu_b_rates[] = {657{2208000000, 1},658{2184000000, 1},659{2088000000, 1},660{2040000000, 1},661{2016000000, 1},662{1992000000, 1},663{1896000000, 1},664{1800000000, 1},665{1704000000, 1},666{1608000000, 1},667{1512000000, 1},668{1488000000, 1},669{1416000000, 1},670{1200000000, 1},671{1008000000, 1},672{ 816000000, 1},673{ 696000000, 1},674{ 600000000, 1},675{ 408000000, 1},676{ 312000000, 1},677{ 216000000, 1},678{ 96000000, 1},679};680681/* Standard PLL. */682#define PLL(_id, _name, _base) \683{ \684.type = RK3399_CLK_PLL, \685.clk.pll = &(struct rk_clk_pll_def) { \686.clkdef.id = _id, \687.clkdef.name = _name, \688.clkdef.parent_names = pll_src_p, \689.clkdef.parent_cnt = nitems(pll_src_p), \690.clkdef.flags = CLK_NODE_STATIC_STRINGS, \691.base_offset = _base, \692.rates = rk3399_pll_rates, \693}, \694}695696PLIST(pll_src_p) = {"xin24m", "xin32k"};697698PLIST(armclkl_p) = {"clk_core_l_lpll_src", "clk_core_l_bpll_src",699"clk_core_l_dpll_src", "clk_core_l_gpll_src"};700PLIST(armclkb_p) = {"clk_core_b_lpll_src", "clk_core_b_bpll_src",701"clk_core_b_dpll_src", "clk_core_b_gpll_src"};702PLIST(ddrclk_p) = {"clk_ddrc_lpll_src", "clk_ddrc_bpll_src",703"clk_ddrc_dpll_src", "clk_ddrc_gpll_src"};704PLIST(pll_src_cpll_gpll_p) = {"cpll", "gpll"};705PLIST(pll_src_cpll_gpll_ppll_p) = {"cpll", "gpll", "ppll"};706PLIST(pll_src_cpll_gpll_upll_p) = {"cpll", "gpll", "upll"};707PLIST(pll_src_npll_cpll_gpll_p) = {"npll", "cpll", "gpll"};708PLIST(pll_src_cpll_gpll_npll_npll_p) = {"cpll", "gpll", "npll", "npll"};709PLIST(pll_src_cpll_gpll_npll_ppll_p) = {"cpll", "gpll", "npll", "ppll" };710PLIST(pll_src_cpll_gpll_npll_24m_p) = {"cpll", "gpll", "npll", "xin24m" };711PLIST(pll_src_cpll_gpll_npll_usbphy480m_p)= {"cpll", "gpll", "npll", "clk_usbphy_480m" };712PLIST(pll_src_ppll_cpll_gpll_npll_upll_p) = { "ppll", "cpll", "gpll", "npll", "upll" };713PLIST(pll_src_cpll_gpll_npll_upll_24m_p)= { "cpll", "gpll", "npll", "upll", "xin24m" };714PLIST(pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" };715PLIST(pll_src_vpll_cpll_gpll_gpll_p) = {"vpll", "cpll", "gpll", "gpll"};716PLIST(pll_src_vpll_cpll_gpll_npll_p) = {"vpll", "cpll", "gpll", "npll"};717718PLIST(aclk_cci_p) = {"cpll_aclk_cci_src", "gpll_aclk_cci_src",719"npll_aclk_cci_src", "vpll_aclk_cci_src"};720PLIST(cci_trace_p) = {"cpll_cci_trace","gpll_cci_trace"};721PLIST(cs_p)= {"cpll_cs", "gpll_cs", "npll_cs","npll_cs"};722PLIST(aclk_perihp_p)= {"cpll_aclk_perihp_src", "gpll_aclk_perihp_src" };723PLIST(dclk_vop0_p) = {"dclk_vop0_div", "dclk_vop0_frac"};724PLIST(dclk_vop1_p)= {"dclk_vop1_div", "dclk_vop1_frac"};725726PLIST(clk_cif_p) = {"clk_cifout_src", "xin24m"};727728PLIST(pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m"};729PLIST(pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m"};730PLIST(pll_src_24m_32k_cpll_gpll_p)= {"xin24m", "xin32k", "cpll", "gpll"};731PLIST(pciecore_cru_phy_p) = {"clk_pcie_core_cru", "clk_pcie_core_phy"};732733PLIST(aclk_emmc_p) = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src"};734735PLIST(aclk_perilp0_p) = { "cpll_aclk_perilp0_src",736"gpll_aclk_perilp0_src" };737738PLIST(fclk_cm0s_p) = { "cpll_fclk_cm0s_src",739"gpll_fclk_cm0s_src" };740741PLIST(hclk_perilp1_p) = { "cpll_hclk_perilp1_src",742"gpll_hclk_perilp1_src" };743744PLIST(clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };745PLIST(clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };746747PLIST(usbphy_480m_p) = { "clk_usbphy0_480m_src",748"clk_usbphy1_480m_src" };749PLIST(aclk_gmac_p) = { "cpll_aclk_gmac_src",750"gpll_aclk_gmac_src" };751PLIST(rmii_p) = { "clk_gmac", "clkin_gmac" };752PLIST(spdif_p) = { "clk_spdif_div", "clk_spdif_frac",753"clkin_i2s", "xin12m" };754PLIST(i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",755"clkin_i2s", "xin12m" };756PLIST(i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",757"clkin_i2s", "xin12m" };758PLIST(i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",759"clkin_i2s", "xin12m" };760PLIST(i2sch_p) = {"clk_i2s0", "clk_i2s1", "clk_i2s2"};761PLIST(i2sout_p) = {"clk_i2sout_src", "xin12m"};762763PLIST(uart0_p)= {"clk_uart0_div", "clk_uart0_frac", "xin24m"};764PLIST(uart1_p)= {"clk_uart1_div", "clk_uart1_frac", "xin24m"};765PLIST(uart2_p)= {"clk_uart2_div", "clk_uart2_frac", "xin24m"};766PLIST(uart3_p)= {"clk_uart3_div", "clk_uart3_frac", "xin24m"};767768static struct rk_clk rk3399_clks[] = {769/* External clocks */770LINK("xin24m"),771LINK("xin32k"),772FFACT(0, "xin12m", "xin24m", 1, 2),773FRATE(0, "clkin_i2s", 0),774FRATE(0, "pclkin_cif", 0),775LINK("clk_usbphy0_480m"),776LINK("clk_usbphy1_480m"),777LINK("clkin_gmac"),778FRATE(0, "clk_pcie_core_phy", 0),779FFACT(0, "clk_ddrc_div2", "clk_ddrc", 1, 2),780781/* PLLs */782PLL(PLL_APLLL, "lpll", 0x00),783PLL(PLL_APLLB, "bpll", 0x20),784PLL(PLL_DPLL, "dpll", 0x40),785PLL(PLL_CPLL, "cpll", 0x60),786PLL(PLL_GPLL, "gpll", 0x80),787PLL(PLL_NPLL, "npll", 0xA0),788PLL(PLL_VPLL, "vpll", 0xC0),789790/* CRU_CLKSEL_CON0 */791CDIV(0, "aclkm_core_l_c", "armclkl", 0,7920, 8, 5),793ARMDIV(ARMCLKL, "armclkl", armclkl_p, rk3399_cpu_l_rates,7940, 0, 5, 6, 2, 0, 3),795/* CRU_CLKSEL_CON1 */796CDIV(0, "pclk_dbg_core_l_c", "armclkl", 0,7971, 8, 5),798CDIV(0, "atclk_core_l_c", "armclkl", 0,7991, 0, 5),800801/* CRU_CLKSEL_CON2 */802CDIV(0, "aclkm_core_b_c", "armclkb", 0,8032, 8, 5),804ARMDIV(ARMCLKB, "armclkb", armclkb_p, rk3399_cpu_b_rates,8052, 0, 5, 6, 2, 1, 3),806807/* CRU_CLKSEL_CON3 */808CDIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", 0,8093, 13, 2),810CDIV(0, "pclk_dbg_core_b_c", "armclkb", 0,8113, 8, 5),812CDIV(0, "atclk_core_b_c", "armclkb", 0,8133, 0, 5),814815/* CRU_CLKSEL_CON4 */816COMP(0, "clk_cs", cs_p, 0,8174, 0, 5, 6, 2),818819/* CRU_CLKSEL_CON5 */820COMP(0, "clk_cci_trace_c", cci_trace_p, 0,8215, 8, 5, 15, 1),822COMP(0, "aclk_cci_pre_c", aclk_cci_p, 0,8235, 0, 5, 6, 2),824825/* CRU_CLKSEL_CON6 */826COMP(0, "pclk_ddr_c", pll_src_cpll_gpll_p, 0,8276, 8, 5, 15, 1),828COMP(SCLK_DDRC, "clk_ddrc", ddrclk_p, 0,8296, 0, 3, 4, 2),830831/* CRU_CLKSEL_CON7 */832CDIV(0, "hclk_vcodec_pre_c", "aclk_vcodec_pre", 0,8337, 8, 5),834COMP(0, "aclk_vcodec_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,8357, 0, 5, 6, 2),836837/* CRU_CLKSEL_CON8 */838CDIV(0, "hclk_vdu_pre_c", "aclk_vdu_pre", 0,8398, 8, 5),840COMP(0, "aclk_vdu_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,8418, 0, 5, 6, 2),842843/* CRU_CLKSEL_CON9 */844COMP(0, "clk_vdu_ca_c", pll_src_cpll_gpll_npll_npll_p, 0,8459, 8, 5, 14, 2),846COMP(0, "clk_vdu_core_c", pll_src_cpll_gpll_npll_npll_p, 0,8479, 0, 5, 6, 2),848849/* CRU_CLKSEL_CON10 */850CDIV(0, "hclk_iep_pre_c", "aclk_iep_pre", 0,85110, 8, 5),852COMP(0, "aclk_iep_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,85310, 0, 5, 6, 2),854855/* CRU_CLKSEL_CON11 */856CDIV(0, "hclk_rga_pre_c", "aclk_rga_pre", 0,85711, 8, 5),858COMP(0, "aclk_rga_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,85911, 0, 5, 6, 2),860861/* CRU_CLKSEL_CON12 */862COMP(0, "aclk_center_c", pll_src_cpll_gpll_npll_npll_p, 0,86312, 8, 5, 14, 2),864COMP(SCLK_RGA_CORE, "clk_rga_core_c", pll_src_cpll_gpll_npll_ppll_p, 0,86512, 0, 5, 6, 2),866867/* CRU_CLKSEL_CON13 */868COMP(0, "hclk_sd_c", pll_src_cpll_gpll_p, 0,86913, 8, 5, 15, 1),870COMP(0, "aclk_gpu_pre_c", pll_src_ppll_cpll_gpll_npll_upll_p, 0,87113, 0, 5, 5, 3),872873/* CRU_CLKSEL_CON14 */874MUX(0, "upll", pll_src_24m_usbphy480m_p, 0,87514, 15, 1),876CDIV(0, "pclk_perihp_c", "aclk_perihp", 0,87714, 12, 2),878CDIV(0, "hclk_perihp_c", "aclk_perihp", 0,87914, 8, 2),880MUX(0, "clk_usbphy_480m", usbphy_480m_p, 0,88114, 6, 1),882COMP(0, "aclk_perihp_c", aclk_perihp_p, 0,88314, 0, 5, 7, 1),884885/* CRU_CLKSEL_CON15 */886COMP(0, "clk_sdio_c", pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,88715, 0, 7, 8, 3),888889/* CRU_CLKSEL_CON16 */890COMP(0, "clk_sdmmc_c", pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,89116, 0, 7, 8, 3),892893/* CRU_CLKSEL_CON17 */894COMP(0, "clk_pcie_pm_c", pll_src_cpll_gpll_npll_24m_p, 0,89517, 0, 7, 8, 3),896897/* CRU_CLKSEL_CON18 */898CDIV(0, "clk_pciephy_ref100m_c", "npll", 0,89918, 11, 5),900MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", pll_src_24m_pciephy_p, 0,90118, 10, 1),902MUX(SCLK_PCIE_CORE, "clk_pcie_core", pciecore_cru_phy_p, 0,90318, 7, 1),904COMP(0, "clk_pcie_core_cru_c", pll_src_cpll_gpll_npll_npll_p, 0,90518, 0, 7, 8, 2),906907/* CRU_CLKSEL_CON19 */908CDIV(0, "pclk_gmac_pre_c", "aclk_gmac_pre", 0,90919, 8, 3),910MUX(SCLK_RMII_SRC, "clk_rmii_src",rmii_p, 0,91119, 4, 1),912MUX(SCLK_HSICPHY, "clk_hsicphy_c", pll_src_cpll_gpll_npll_usbphy480m_p, 0,91319, 0, 2),914915/* CRU_CLKSEL_CON20 */916COMP(0, "clk_gmac_c", pll_src_cpll_gpll_npll_npll_p, 0,91720, 8, 5, 14, 2),918COMP(0, "aclk_gmac_pre_c", aclk_gmac_p, 0,91920, 0, 5, 7, 1),920921/* CRU_CLKSEL_CON21 */922COMP(ACLK_EMMC, "aclk_emmc", aclk_emmc_p, 0,92321, 0, 5, 7, 1),924925/* CRU_CLKSEL_CON22 */926COMP(0, "clk_emmc_c", pll_src_cpll_gpll_npll_upll_24m_p, 0,92722, 0, 7, 8, 3),928929/* CRU_CLKSEL_CON23 */930CDIV(0, "pclk_perilp0_c", "aclk_perilp0", 0,93123, 12, 3),932CDIV(0, "hclk_perilp0_c", "aclk_perilp0", 0,93323, 8, 2),934COMP(0, "aclk_perilp0_c", aclk_perilp0_p, 0,93523, 0, 5, 7, 1),936937/* CRU_CLKSEL_CON24 */938COMP(0, "fclk_cm0s_c", fclk_cm0s_p, 0,93924, 8, 5, 15, 1),940COMP(0, "clk_crypto0_c", pll_src_cpll_gpll_ppll_p, 0,94124, 0, 5, 6, 2),942943/* CRU_CLKSEL_CON25 */944CDIV(0, "pclk_perilp1_c", "hclk_perilp1", 0,94525, 8, 3),946COMP(HCLK_PERILP1, "hclk_perilp1", hclk_perilp1_p, 0,94725, 0, 5, 7, 1),948949/* CRU_CLKSEL_CON26 */950CDIV(0, "clk_saradc_c", "xin24m", 0,95126, 8, 8),952COMP(0, "clk_crypto1_c", pll_src_cpll_gpll_ppll_p, 0,95326, 0, 5, 6, 2),954955/* CRU_CLKSEL_CON27 */956COMP(0, "clk_tsadc_c", pll_src_p, 0,95727, 0, 10, 15, 1),958959/* CRU_CLKSEL_CON28 */960MUX(0, "clk_i2s0_mux", i2s0_p, RK_CLK_MUX_REPARENT,96128, 8, 2),962COMP(0, "clk_i2s0_div_c", pll_src_cpll_gpll_p, 0,96328, 0, 7, 7, 1),964965/* CRU_CLKSEL_CON29 */966MUX(0, "clk_i2s1_mux", i2s1_p, RK_CLK_MUX_REPARENT,96729, 8, 2),968COMP(0, "clk_i2s1_div_c", pll_src_cpll_gpll_p, 0,96929, 0, 7, 7, 1),970971/* CRU_CLKSEL_CON30 */972MUX(0, "clk_i2s2_mux", i2s2_p, RK_CLK_MUX_REPARENT,97330, 8, 2),974COMP(0, "clk_i2s2_div_c", pll_src_cpll_gpll_p, 0,97530, 0, 7, 7, 1),976977/* CRU_CLKSEL_CON31 */978MUX(0, "clk_i2sout_c", i2sout_p, 0,97931, 2, 1),980MUX(0, "clk_i2sout_src", i2sch_p, 0,98131, 0, 2),982983/* CRU_CLKSEL_CON32 */984COMP(0, "clk_spdif_rec_dptx_c", pll_src_cpll_gpll_p, 0,98532, 8, 5, 15, 1),986MUX(0, "clk_spdif_mux", spdif_p, 0,98732, 13, 2),988COMP(0, "clk_spdif_div_c", pll_src_cpll_gpll_p, 0,98932, 0, 7, 7, 1),990991/* CRU_CLKSEL_CON33 */992MUX(0, "clk_uart_src", pll_src_cpll_gpll_p, 0,99333, 15, 1),994MUX(0, "clk_uart0_src", pll_src_cpll_gpll_upll_p, 0,99533, 12, 2),996MUX(SCLK_UART0, "clk_uart0", uart0_p, 0,99733, 8, 2),998CDIV(0, "clk_uart0_div_c", "clk_uart0_src", 0,99933, 0, 7),10001001/* CRU_CLKSEL_CON34 */1002MUX(SCLK_UART1, "clk_uart1", uart1_p, 0,100334, 8, 2),1004CDIV(0, "clk_uart1_div_c", "clk_uart_src", 0,100534, 0, 7),10061007/* CRU_CLKSEL_CON35 */1008MUX(SCLK_UART2, "clk_uart2", uart2_p, 0,100935, 8, 2),1010CDIV(0, "clk_uart2_div_c", "clk_uart_src", 0,101135, 0, 7),10121013/* CRU_CLKSEL_CON36 */1014MUX(SCLK_UART3, "clk_uart3", uart3_p, 0,101536, 8, 2),1016CDIV(0, "clk_uart3_div_c", "clk_uart_src", 0,101736, 0, 7),10181019/* CRU_CLKSEL_CON37 */1020/* unused */10211022/* CRU_CLKSEL_CON38 */1023MUX(0, "clk_testout2_pll_src", pll_src_cpll_gpll_npll_npll_p, 0,102438, 14, 2),1025COMP(0, "clk_testout2_c", clk_testout2_p, 0,102638, 8, 5, 13, 1),1027MUX(0, "clk_testout1_pll_src", pll_src_cpll_gpll_npll_npll_p, 0,102838, 6, 2),1029COMP(0, "clk_testout1_c", clk_testout1_p, 0,103038, 0, 5, 5, 1),10311032/* CRU_CLKSEL_CON39 */1033COMP(0, "aclk_usb3_c", pll_src_cpll_gpll_npll_npll_p, 0,103439, 0, 5, 6, 2),10351036/* CRU_CLKSEL_CON40 */1037COMP(0, "clk_usb3otg0_suspend_c", pll_src_p, 0,103840, 0, 10, 15, 1),10391040/* CRU_CLKSEL_CON41 */1041COMP(0, "clk_usb3otg1_suspend_c", pll_src_p, 0,104241, 0, 10, 15, 1),10431044/* CRU_CLKSEL_CON42 */1045COMP(0, "aclk_hdcp_c", pll_src_cpll_gpll_ppll_p, 0,104642, 8, 5, 14, 2),1047COMP(0, "aclk_vio_c", pll_src_cpll_gpll_ppll_p, 0,104842, 0, 5, 6, 2),10491050/* CRU_CLKSEL_CON43 */1051CDIV(0, "pclk_hdcp_c", "aclk_hdcp", 0,105243, 10, 5),1053CDIV(0, "hclk_hdcp_c", "aclk_hdcp", 0,105443, 5, 5),1055CDIV(0, "pclk_vio_c", "aclk_vio", 0,105643, 0, 5),10571058/* CRU_CLKSEL_CON44 */1059COMP(0, "pclk_edp_c", pll_src_cpll_gpll_p, 0,106044, 8, 6, 15, 1),10611062/* CRU_CLKSEL_CON45 - XXX clocks in mux are reversed in TRM !!!*/1063COMP(0, "clk_hdmi_cec_c", pll_src_p, 0,106445, 0, 10, 15, 1),10651066/* CRU_CLKSEL_CON46 */1067COMP(0, "clk_dp_core_c", pll_src_npll_cpll_gpll_p, 0,106846, 0, 5, 6, 2),10691070/* CRU_CLKSEL_CON47 */1071CDIV(0, "hclk_vop0_pre_c", "aclk_vop0_pre_c", 0,107247, 8, 5),1073COMP(0, "aclk_vop0_pre_c", pll_src_vpll_cpll_gpll_npll_p, 0,107447, 0, 5, 6, 2),10751076/* CRU_CLKSEL_CON48 */1077CDIV(0, "hclk_vop1_pre_c", "aclk_vop1_pre", 0,107848, 8, 5),1079COMP(0, "aclk_vop1_pre_c", pll_src_vpll_cpll_gpll_npll_p, 0,108048, 0, 5, 6, 2),10811082/* CRU_CLKSEL_CON49 */1083MUX(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, 0,108449, 11, 1),1085COMP(0, "dclk_vop0_div_c", pll_src_vpll_cpll_gpll_gpll_p, 0,108649, 0, 8, 8, 2),10871088/* CRU_CLKSEL_CON50 */1089MUX(DCLK_VOP1, "dclk_vop1", dclk_vop1_p, 0,109050, 11, 1),1091COMP(0, "dclk_vop1_div_c", pll_src_vpll_cpll_gpll_gpll_p, 0,109250, 0, 8, 8, 2),10931094/* CRU_CLKSEL_CON51 */1095COMP(0, "clk_vop0_pwm_c", pll_src_vpll_cpll_gpll_gpll_p, 0,109651, 0, 5, 6, 2),10971098/* CRU_CLKSEL_CON52 */1099COMP(0, "clk_vop1_pwm_c", pll_src_vpll_cpll_gpll_gpll_p, 0,110052, 0, 5, 6, 2),11011102/* CRU_CLKSEL_CON53 */1103CDIV(0, "hclk_isp0_c", "aclk_isp0", 0,110453, 8, 5),1105COMP(0, "aclk_isp0_c", pll_src_cpll_gpll_ppll_p, 0,110653, 0, 5, 6, 2),11071108/* CRU_CLKSEL_CON54 */1109CDIV(0, "hclk_isp1_c", "aclk_isp1", 0,111054, 8, 5),1111COMP(0, "aclk_isp1_c", pll_src_cpll_gpll_ppll_p, 0,111254, 0, 5, 6, 2),11131114/* CRU_CLKSEL_CON55 */1115COMP(0, "clk_isp1_c", pll_src_cpll_gpll_npll_npll_p, 0,111655, 8, 5, 14, 2),1117COMP(0, "clk_isp0_c", pll_src_cpll_gpll_npll_npll_p, 0,111855, 0, 5, 6, 2),11191120/* CRU_CLKSEL_CON56 */1121COMP(0, "aclk_gic_pre_c", pll_src_cpll_gpll_p, 0,112256, 8, 5, 15, 1),1123MUX(0, "clk_cifout_src_c", pll_src_cpll_gpll_npll_npll_p, 0,112456, 6, 2),1125COMP(SCLK_CIF_OUT, "clk_cifout", clk_cif_p, 0,112656, 0, 5, 5, 1),11271128/* CRU_CLKSEL_CON57 */1129CDIV(0, "clk_test_24m", "xin24m", 0,113057, 6, 10),1131CDIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,113257, 0, 5),11331134/* CRU_CLKSEL_CON58 */1135COMP(0, "clk_spi5_c", pll_src_cpll_gpll_p, 0,113658, 8, 7, 15, 1),1137MUX(0, "clk_test_pre", pll_src_cpll_gpll_p, 0,113858, 7, 1),1139CDIV(0, "clk_test_c", "clk_test_pre", 0,114058, 0, 5),11411142/* CRU_CLKSEL_CON59 */1143COMP(0, "clk_spi1_c", pll_src_cpll_gpll_p, 0,114459, 8, 7, 15, 1),1145COMP(0, "clk_spi0_c", pll_src_cpll_gpll_p, 0,114659, 0, 7, 7, 1),11471148/* CRU_CLKSEL_CON60 */1149COMP(0, "clk_spi4_c", pll_src_cpll_gpll_p, 0,115060, 8, 7, 15, 1),1151COMP(0, "clk_spi2_c", pll_src_cpll_gpll_p, 0,115260, 0, 7, 7, 1),11531154/* CRU_CLKSEL_CON61 */1155COMP(0, "clk_i2c5_c", pll_src_cpll_gpll_p, 0,115661, 8, 7, 15, 1),1157COMP(0, "clk_i2c1_c", pll_src_cpll_gpll_p, 0,115861, 0, 7, 7, 1),11591160/* CRU_CLKSEL_CON62 */1161COMP(0, "clk_i2c6_c", pll_src_cpll_gpll_p, 0,116262, 8, 7, 15, 1),1163COMP(0, "clk_i2c2_c", pll_src_cpll_gpll_p, 0,116462, 0, 7, 7, 1),11651166/* CRU_CLKSEL_CON63 */1167COMP(0, "clk_i2c7_c", pll_src_cpll_gpll_p, 0,116863, 8, 7, 15, 1),1169COMP(0, "clk_i2c3_c", pll_src_cpll_gpll_p, 0,117063, 0, 7, 7, 1),11711172/* CRU_CLKSEL_CON64 */1173COMP(0, "clk_uphy0_tcpdphy_ref_c", pll_src_p, 0,117464, 8, 5, 15, 1),1175COMP(0, "clk_uphy0_tcpdcore_c", pll_src_24m_32k_cpll_gpll_p, 0,117664, 0, 5, 6, 2),11771178/* CRU_CLKSEL_CON65 */1179COMP(0, "clk_uphy1_tcpdphy_ref_c", pll_src_p, 0,118065, 8, 5, 15, 1),1181COMP(0, "clk_uphy1_tcpdcore_c", pll_src_24m_32k_cpll_gpll_p, 0,118265, 0, 5, 6, 2),11831184/* CRU_CLKSEL_CON99 - 107 */1185FRACT(0, "clk_spdif_frac_c", "clk_spdif_div", 0,118699),1187FRACT(0, "clk_i2s0_frac_c", "clk_i2s0_div", 0,118896),1189FRACT(0, "clk_i2s1_frac_c", "clk_i2s1_div", 0,119097),1191FRACT(0, "clk_i2s2_frac_c", "clk_i2s2_div", 0,119298),1193FRACT(0, "clk_uart0_frac_c", "clk_uart0_div", 0,1194100),1195FRACT(0, "clk_uart1_frac_c", "clk_uart1_div", 0,1196101),1197FRACT(0, "clk_uart2_frac_c", "clk_uart2_div", 0,1198102),1199FRACT(0, "clk_uart3_frac_c", "clk_uart3_div", 0,1200103),1201FRACT(0, "clk_test_frac_c", "clk_test_pre", 0,1202105),1203FRACT(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0,1204106),1205FRACT(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0,1206107),12071208/*1209* This clock is controlled in the secure world1210*/1211FFACT(PCLK_WDT, "pclk_wdt", "pclk_alive", 1, 1),12121213/* Not yet implemented yet1214* MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),1215* MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),1216* MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),1217* MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),1218*/12191220};12211222static int1223rk3399_cru_probe(device_t dev)1224{12251226if (!ofw_bus_status_okay(dev))1227return (ENXIO);12281229if (ofw_bus_is_compatible(dev, "rockchip,rk3399-cru")) {1230device_set_desc(dev, "Rockchip RK3399 Clock and Reset Unit");1231return (BUS_PROBE_DEFAULT);1232}12331234return (ENXIO);1235}12361237static int1238rk3399_cru_attach(device_t dev)1239{1240struct rk_cru_softc *sc;12411242sc = device_get_softc(dev);1243sc->dev = dev;12441245sc->gates = rk3399_gates;1246sc->ngates = nitems(rk3399_gates);12471248sc->clks = rk3399_clks;1249sc->nclks = nitems(rk3399_clks);12501251sc->reset_offset = 0x400;1252sc->reset_num = 335;12531254return (rk_cru_attach(dev));1255}12561257static device_method_t rk3399_cru_methods[] = {1258/* Device interface */1259DEVMETHOD(device_probe, rk3399_cru_probe),1260DEVMETHOD(device_attach, rk3399_cru_attach),12611262DEVMETHOD_END1263};12641265DEFINE_CLASS_1(rk3399_cru, rk3399_cru_driver, rk3399_cru_methods,1266sizeof(struct rk_cru_softc), rk_cru_driver);12671268EARLY_DRIVER_MODULE(rk3399_cru, simplebus, rk3399_cru_driver, 0, 0,1269BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);127012711272