CoCalc -- rk3399

GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/dev/clk/rockchip/rk3399_cru.c
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/*-
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 * SPDX-License-Identifier: BSD-2-Clause
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 *
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 * Copyright (c) 2018 Emmanuel Vadot <[email protected]>
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 * Copyright (c) 2018 Val Packett <[email protected]>
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * 1. Redistributions of source code must retain the above copyright
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 *    notice, this list of conditions and the following disclaimer.
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 * 2. Redistributions in binary form must reproduce the above copyright
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 *    notice, this list of conditions and the following disclaimer in the
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 *    documentation and/or other materials provided with the distribution.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/clk/clk_div.h>
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#include <dev/clk/clk_fixed.h>
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#include <dev/clk/clk_mux.h>
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#include <dev/clk/rockchip/rk_cru.h>
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#include <dev/clk/rockchip/rk3399_cru_dt.h>
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#define	CRU_CLKSEL_CON(x)	(0x100 + (x) * 0x4)
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#define	CRU_CLKGATE_CON(x)	(0x300 + (x) * 0x4)
52

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/* GATES */
54

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static struct rk_cru_gate rk3399_gates[] = {
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	/* CRU_CLKGATE_CON0 */
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	/* 15-8 unused */
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	GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m",		0, 7),
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	GATE(0, "pclk_dbg_core_l", "pclk_dbg_core_l_c",			0, 6),
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	GATE(0, "atclk_core_l", "atclk_core_l_c",			0, 5),
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	GATE(0, "aclkm_core_l", "aclkm_core_l_c",			0, 4),
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	GATE(0, "clk_core_l_gpll_src", "gpll",				0, 3),
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	GATE(0, "clk_core_l_dpll_src", "dpll",				0, 2),
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	GATE(0, "clk_core_l_bpll_src", "bpll",				0, 1),
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	GATE(0, "clk_core_l_lpll_src", "lpll",				0, 0),
66

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	/* CRU_CLKGATE_CON1 */
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	/* 15 - 8 unused */
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	GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m",		1, 7),
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	GATE(0, "pclk_dbg_core_b","pclk_dbg_core_b_c",			1, 6),
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	GATE(0, "atclk_core_b", "atclk_core_b_c", 			1, 5),
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	GATE(0, "aclkm_core_b", "aclkm_core_b_c",			1, 4),
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	GATE(0, "clk_core_b_gpll_src", "gpll",				1, 3),
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	GATE(0, "clk_core_b_dpll_src", "dpll",				1, 2),
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	GATE(0, "clk_core_b_bpll_src", "bpll",				1, 1),
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	GATE(0, "clk_core_b_lpll_src", "lpll",				1, 0),
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	/* CRU_CLKGATE_CON2 */
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	/* 15 - 11 unused */
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	GATE(0, "npll_cs", "npll",					2, 10),
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	GATE(0, "gpll_cs", "gpll",					2, 9),
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	GATE(0, "cpll_cs", "cpll",					2, 8),
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	GATE(SCLK_CCI_TRACE, "clk_cci_trace", "clk_cci_trace_c",	2, 7),
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	GATE(0, "gpll_cci_trace", "gpll",				2, 6),
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	GATE(0, "cpll_cci_trace", "cpll",				2, 5),
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	GATE(0, "aclk_cci_pre", "aclk_cci_pre_c",			2, 4),
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	GATE(0, "vpll_aclk_cci_src", "vpll",				2, 3),
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	GATE(0, "npll_aclk_cci_src", "npll",				2, 2),
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	GATE(0, "gpll_aclk_cci_src", "gpll",				2, 1),
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	GATE(0, "cpll_aclk_cci_src", "cpll",				2, 0),
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	/* CRU_CLKGATE_CON3 */
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	/* 15 - 8 unused */
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	GATE(0, "aclk_center", "aclk_center_c",				3, 7),
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	/* 6 unused */
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	/* 5 unused */
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	GATE(PCLK_DDR, "pclk_ddr", "pclk_ddr_c",			3, 4),
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	GATE(0, "clk_ddrc_gpll_src", "gpll",				3, 3),
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	GATE(0, "clk_ddrc_dpll_src", "dpll",				3, 2),
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	GATE(0, "clk_ddrc_bpll_src", "bpll",				3, 1),
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	GATE(0, "clk_ddrc_lpll_src", "lpll",				3, 0),
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	/* CRU_CLKGATE_CON4 */
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	/* 15 - 12 unused */
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	GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m",			4, 11),
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	GATE(0, "clk_rga_core", "clk_rga_core_c",			4, 10),
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	GATE(0, "hclk_rga_pre", "hclk_rga_pre_c",			4, 9),
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	GATE(0, "aclk_rga_pre", "aclk_rga_pre_c",			4, 8),
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	GATE(0, "hclk_iep_pre", "hclk_iep_pre_c",			4, 7),
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	GATE(0, "aclk_iep_pre", "aclk_iep_pre_c",			4, 6),
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	GATE(SCLK_VDU_CA, "clk_vdu_ca", "clk_vdu_ca_c",			4, 5),
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	GATE(SCLK_VDU_CORE, "clk_vdu_core", "clk_vdu_core_c",		4, 4),
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	GATE(0, "hclk_vdu_pre", "hclk_vdu_pre_c",			4, 3),
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	GATE(0, "aclk_vdu_pre", "aclk_vdu_pre_c",			4, 2),
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	GATE(0, "hclk_vcodec_pre", "hclk_vcodec_pre_c",			4, 1),
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	GATE(0, "aclk_vcodec_pre", "aclk_vcodec_pre_c",			4, 0),
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	/* CRU_CLKGATE_CON5 */
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	/* 15 - 10 unused */
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	GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src",		5, 9),
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	GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src",		5, 8),
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	GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src",		5, 7),
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	GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src",		5, 6),
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	GATE(SCLK_MAC, "clk_gmac", "clk_gmac_c",			5, 5),
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	GATE(PCLK_PERIHP, "pclk_perihp", "pclk_perihp_c",		5, 4),
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	GATE(HCLK_PERIHP, "hclk_perihp", "hclk_perihp_c",		5, 3),
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	GATE(ACLK_PERIHP, "aclk_perihp", "aclk_perihp_c",		5, 2),
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	GATE(0, "cpll_aclk_perihp_src", "cpll",				5, 1),
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	GATE(0, "gpll_aclk_perihp_src", "gpll",				5, 0),
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	/* CRU_CLKGATE_CON6 */
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	/* 15 unused */
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	GATE(SCLK_EMMC, "clk_emmc", "clk_emmc_c",			6, 14),
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	GATE(0, "cpll_aclk_emmc_src", "cpll",				6, 13),
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	GATE(0, "gpll_aclk_emmc_src", "gpll",				6, 12),
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	GATE(0, "pclk_gmac_pre", "pclk_gmac_pre_c",			6, 11),
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	GATE(0, "aclk_gmac_pre", "aclk_gmac_pre_c",			6, 10),
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	GATE(0, "cpll_aclk_gmac_src", "cpll",				6, 9),
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	GATE(0, "gpll_aclk_gmac_src", "gpll",				6, 8),
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	/* 7 unused */
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	GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m",		6, 6),
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	GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", 		6, 5),
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	GATE(SCLK_HSICPHY, "clk_hsicphy", "clk_hsicphy_c",		6, 4),
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	GATE(0, "clk_pcie_core_cru", "clk_pcie_core_cru_c",		6, 3),
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	GATE(SCLK_PCIE_PM, "clk_pcie_pm", "clk_pcie_pm_c",		6, 2),
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	GATE(SCLK_SDMMC, "clk_sdmmc", "clk_sdmmc_c",			6, 1),
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	GATE(SCLK_SDIO, "clk_sdio", "clk_sdio_c",			6, 0),
148

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	/* CRU_CLKGATE_CON7 */
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	/* 15 - 10 unused */
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	GATE(FCLK_CM0S, "fclk_cm0s", "fclk_cm0s_c",			7, 9),
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	GATE(SCLK_CRYPTO1, "clk_crypto1", "clk_crypto1_c",		7, 8),
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	GATE(SCLK_CRYPTO0, "clk_crypto0", "clk_crypto0_c",		7, 7),
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	GATE(0, "cpll_fclk_cm0s_src", "cpll",				7, 6),
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	GATE(0, "gpll_fclk_cm0s_src", "gpll",				7, 5),
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	GATE(PCLK_PERILP0, "pclk_perilp0", "pclk_perilp0_c",		7, 4),
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	GATE(HCLK_PERILP0, "hclk_perilp0", "hclk_perilp0_c",		7, 3),
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	GATE(ACLK_PERILP0, "aclk_perilp0", "aclk_perilp0_c",		7, 2),
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	GATE(0, "cpll_aclk_perilp0_src", "cpll",			7, 1),
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	GATE(0, "gpll_aclk_perilp0_src", "gpll",			7, 0),
161

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	/* CRU_CLKGATE_CON8 */
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	GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux",		8, 15),
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	GATE(0, "clk_spdif_frac", "clk_spdif_frac_c",			8, 14),
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	GATE(0, "clk_spdif_div", "clk_spdif_div_c",			8, 13),
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	GATE(SCLK_I2S_8CH_OUT, "clk_i2sout", "clk_i2sout_c",		8, 12),
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	GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux",			8, 11),
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	GATE(0, "clk_i2s2_frac", "clk_i2s2_frac_c",			8, 10),
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	GATE(0, "clk_i2s2_div", "clk_i2s2_div_c",			8, 9),
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	GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux",			8, 8),
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	GATE(0, "clk_i2s1_frac", "clk_i2s1_frac_c",			8, 7),
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	GATE(0, "clk_i2s1_div", "clk_i2s1_div_c",			8, 6),
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	GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux",			8, 5),
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	GATE(0, "clk_i2s0_frac","clk_i2s0_frac_c",			8, 4),
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	GATE(0, "clk_i2s0_div","clk_i2s0_div_c",			8, 3),
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	GATE(PCLK_PERILP1, "pclk_perilp1", "pclk_perilp1_c",		8, 2),
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	GATE(HCLK_PERILP1, "cpll_hclk_perilp1_src", "cpll",		8, 1),
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	GATE(0, "gpll_hclk_perilp1_src", "gpll",			8, 0),
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	/* CRU_CLKGATE_CON9 */
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	GATE(SCLK_SPI4, "clk_spi4", "clk_spi4_c", 			9, 15),
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	GATE(SCLK_SPI2, "clk_spi2", "clk_spi2_c",			9, 14),
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	GATE(SCLK_SPI1, "clk_spi1", "clk_spi1_c",			9, 13),
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	GATE(SCLK_SPI0, "clk_spi0", "clk_spi0_c",			9, 12),
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	GATE(SCLK_SARADC, "clk_saradc", "clk_saradc_c",			9, 11),
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	GATE(SCLK_TSADC, "clk_tsadc", "clk_tsadc_c",			9, 10),
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	/* 9 - 8 unused */
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	GATE(0, "clk_uart3_frac", "clk_uart3_frac_c",			9, 7),
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	GATE(0, "clk_uart3_div", "clk_uart3_div_c",			9, 6),
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	GATE(0, "clk_uart2_frac", "clk_uart2_frac_c",			9, 5),
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	GATE(0, "clk_uart2_div", "clk_uart2_div_c",			9, 4),
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	GATE(0, "clk_uart1_frac", "clk_uart1_frac_c",			9, 3),
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	GATE(0, "clk_uart1_div", "clk_uart1_div_c",			9, 2),
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	GATE(0, "clk_uart0_frac", "clk_uart0_frac_c", 			9, 1),
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	GATE(0, "clk_uart0_div", "clk_uart0_div_c",			9, 0),
196

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	/* CRU_CLKGATE_CON10 */
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	GATE(SCLK_VOP1_PWM, "clk_vop1_pwm", "clk_vop1_pwm_c",		10, 15),
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	GATE(SCLK_VOP0_PWM, "clk_vop0_pwm", "clk_vop0_pwm_c",		10, 14),
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	GATE(DCLK_VOP0_DIV, "dclk_vop0_div", "dclk_vop0_div_c",		10, 12),
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	GATE(DCLK_VOP1_DIV, "dclk_vop1_div", "dclk_vop1_div_c",		10, 13),
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	GATE(0, "hclk_vop1_pre", "hclk_vop1_pre_c",			10, 11),
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	GATE(ACLK_VOP1_PRE, "aclk_vop1_pre", "aclk_vop1_pre_c",		10, 10),
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	GATE(0, "hclk_vop0_pre", "hclk_vop0_pre_c",			10, 9),
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	GATE(ACLK_VOP0_PRE, "aclk_vop0_pre", "aclk_vop0_pre_c",		10, 8),
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	GATE(0, "clk_cifout_src", "clk_cifout_src_c",			10, 7),
207
	GATE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", "clk_spdif_rec_dptx_c", 10, 6),
208
	GATE(SCLK_I2C7, "clk_i2c7", "clk_i2c7_c",			10, 5),
209
	GATE(SCLK_I2C3, "clk_i2c3", "clk_i2c3_c",			10, 4),
210
	GATE(SCLK_I2C6, "clk_i2c6", "clk_i2c6_c",			10, 3),
211
	GATE(SCLK_I2C2, "clk_i2c2", "clk_i2c2_c",			10, 2),
212
	GATE(SCLK_I2C5, "clk_i2c5", "clk_i2c5_c",			10, 1),
213
	GATE(SCLK_I2C1, "clk_i2c1", "clk_i2c1_c",			10, 0),
214

215
	/* CRU_CLKGATE_CON11 */
216
	GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m",		11, 15),
217
	GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m",		11, 14),
218
	/* 13-12 unused */
219
	GATE(PCLK_EDP, "pclk_edp", "pclk_edp_c",			11, 11),
220
	GATE(PCLK_HDCP, "pclk_hdcp", "pclk_hdcp_c",			11, 10),
221
	/* 9 unuwsed */
222
	GATE(SCLK_DP_CORE, "clk_dp_core", "clk_dp_core_c",		11, 8),
223
	GATE(SCLK_HDMI_CEC, "clk_hdmi_cec", "clk_hdmi_cec_c",		11, 7),
224
	GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m",			11, 6),
225
	GATE(SCLK_ISP1, "clk_isp1", "clk_isp1_c",			11, 5),
226
	GATE(SCLK_ISP0, "clk_isp0",  "clk_isp0_c",			11, 4),
227
	GATE(HCLK_HDCP, "hclk_hdcp",  "hclk_hdcp_c",			11, 3),
228
	GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_c",			11, 2),
229
	GATE(PCLK_VIO, "pclk_vio", "pclk_vio_c",			11, 1),
230
	GATE(ACLK_VIO, "aclk_vio", "aclk_vio_c",			11, 0),
231

232
	/* CRU_CLKGATE_CON12 */
233
	/* 15 - 14 unused */
234
	GATE(HCLK_SD, "hclk_sd", "hclk_sd_c",				12, 13),
235
	GATE(ACLK_GIC_PRE, "aclk_gic_pre",  "aclk_gic_pre_c",		12, 12),
236
	GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_c",			12, 11),
237
	GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_c",			12, 10),
238
	GATE(HCLK_ISP0, "hclk_isp0", "hclk_isp0_c",			12, 9),
239
	GATE(ACLK_ISP0, "aclk_isp0",  "aclk_isp0_c",			12, 8),
240
	/* 7 unused */
241
	GATE(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "clk_pciephy_ref100m_c", 12, 6),
242
	/* 5 unused */
243
	GATE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", "clk_usb3otg1_suspend_c", 12, 4),
244
	GATE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", "clk_usb3otg0_suspend_c", 12, 3),
245
	GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m",		12, 2),
246
	GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m",		12, 1),
247
	GATE(ACLK_USB3, "aclk_usb3",  "aclk_usb3_c", 			12, 0),
248

249
	/* CRU_CLKGATE_CON13 */
250
	GATE(SCLK_TESTCLKOUT2, "clk_testout2", "clk_testout2_c",	13, 15),
251
	GATE(SCLK_TESTCLKOUT1, "clk_testout1",  "clk_testout1_c",	13, 14),
252
	GATE(SCLK_SPI5, "clk_spi5",  "clk_spi5_c",			13, 13),
253
	GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m",		13, 12),
254
	GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m",		13, 12),
255
	GATE(0, "clk_test", "clk_test_c",				13, 11),
256
	/* 10 unused */
257
	GATE(0, "clk_test_frac", "clk_test_frac_c",			13, 9),
258
	/* 8 unused */
259
	GATE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", "clk_uphy1_tcpdcore_c", 13, 7),
260
	GATE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", "clk_uphy1_tcpdphy_ref_c", 13, 6),
261
	GATE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", "clk_uphy0_tcpdcore_c", 13, 5),
262
	GATE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", "clk_uphy0_tcpdphy_ref_c", 13, 4),
263
	/* 3 - 2 unused */
264
	GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 			13, 1),
265
	GATE(0, "aclk_gpu_pre", "aclk_gpu_pre_c",			13, 0),
266

267
	/* CRU_CLKGATE_CON14 */
268
	/* 15 - 14 unused */
269
	GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l",	14, 13),
270
	GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", 14, 12),
271
	GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", 14, 11),
272
	GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", 14, 10),
273
	GATE(0, "clk_dbg_pd_core_l", "armclkl",				14, 9),
274
	/* 8 - 7 unused */
275
	GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", 	14, 6),
276
	GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", 14, 5),
277
	GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", 14, 4),
278
	GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", 14, 3),
279
	GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b",		14, 2),
280
	GATE(0, "clk_dbg_pd_core_b", "armclkb", 			14, 1),
281
	/* 0 unused */
282

283
	/* CRU_CLKGATE_CON15 */
284
	/* 15 - 8 unused */
285
	GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre",		15, 7),
286
	GATE(0, "clk_dbg_noc", "clk_cs",				15, 6),
287
	GATE(0, "clk_dbg_cxcs", "clk_cs",				15, 5),
288
	GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre",		15, 4),
289
	GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre",		15, 3),
290
	GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre",			15, 2),
291
	GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", 15, 1),
292
	GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", 15, 0),
293

294
	/* CRU_CLKGATE_CON16 */
295
	/* 15 - 12 unused */
296
	GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre",		16, 11),
297
	GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 			16, 10),
298
	GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre",		16, 9),
299
	GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 			16, 8),
300
	/* 7 - 4 unused */
301
	GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre",		16, 3),
302
	GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 			16, 2),
303
	GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre",		16, 1),
304
	GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 			16, 0),
305

306
	/* CRU_CLKGATE_CON17 */
307
	/* 15 - 12 unused */
308
	GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre",		17, 11),
309
	GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre",			17, 10),
310
	GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre",		17, 9),
311
	GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 			17, 8),
312
	GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre",			17, 3),
313
	GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre",		17, 2),
314
	GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre",			17, 1),
315
	GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre",		17, 0),
316

317
	/* CRU_CLKGATE_CON18 */
318
	GATE(PCLK_CIC, "pclk_cic", "pclk_ddr",				18, 15),
319
	GATE(0, "clk_ddr_mon_timer", "xin24m",				18, 14),
320
	GATE(0, "clk_ddr_mon", "clk_ddrc_div2",				18, 13),
321
	GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 			18, 12),
322
	GATE(0, "clk_ddr_cic", "clk_ddrc_div2",				18, 11),
323
	GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr",	18, 10),
324
	GATE(0, "clk_ddrcfg_msch1", "clk_ddrc_div2",			18,  9),
325
	GATE(0, "clk_ddrphy1", "clk_ddrc_div2",				18,  8),
326
	GATE(0, "clk_ddrphy_ctrl1", "clk_ddrc_div2",			18,  7),
327
	GATE(0, "clk_ddrc1", "clk_ddrc_div2",				18,  6),
328
	GATE(0, "clk_ddr1_msch", "clk_ddrc_div2",			18,  5),
329
	GATE(0, "clk_ddrcfg_msch0", "clk_ddrc_div2",			18,  4),
330
	GATE(0, "clk_ddrphy0", "clk_ddrc_div2",				18,  3),
331
	GATE(0, "clk_ddrphy_ctrl0", "clk_ddrc_div2",			18,  2),
332
	GATE(0, "clk_ddrc0", "clk_ddrc_div2",				18,  1),
333

334
	/* CRU_CLKGATE_CON19 */
335
	/* 15 - 3 unused */
336
	GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr",		19, 2),
337
	GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", 19, 1),
338
	GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", 19, 0),
339

340
	/* CRU_CLKGATE_CON20 */
341
	GATE(0, "hclk_ahb1tom", "hclk_perihp",				20, 15),
342
	GATE(0, "pclk_perihp_noc", "pclk_perihp",			20, 14),
343
	GATE(0, "hclk_perihp_noc", "hclk_perihp",			20, 13),
344
	GATE(0, "aclk_perihp_noc", "aclk_perihp",			20, 12),
345
	GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp",			20, 11),
346
	GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp",			20, 10),
347
	GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp",			20, 9),
348
	GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp",		20, 8),
349
	GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp",			20, 7),
350
	GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp",		20, 6),
351
	GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp",			20, 5),
352
	GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp",		20, 4),
353
	GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp",		20, 2),
354
	/* 1 - 0 unused */
355

356
	/* CRU_CLKGATE_CON21 */
357
	/* 15 - 10 unused */
358
	GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive",	21, 9),
359
	GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive",	21, 8),
360
	/* 7 unused */
361
	GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive",	21, 6),
362
	GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive",	21, 5),
363
	GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive",	21, 4),
364
	GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg",	21, 3),
365
	GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", 21, 2),
366
	GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg",	21, 1),
367
	GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref",		21, 0),
368

369
	/* CRU_CLKGATE_CON22 */
370
	GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1",	22, 15),
371
	GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1",	22, 14),
372
	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1",			22, 13),
373
	GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1",		22, 12),
374
	GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1",		22, 11),
375
	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_perilp1",			22, 10),
376
	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_perilp1",			22, 9),
377
	GATE(PCLK_I2C6, "pclk_i2c6", "pclk_perilp1",			22, 8),
378
	GATE(PCLK_I2C5, "pclk_i2c5", "pclk_perilp1",			22, 7),
379
	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_perilp1",			22, 6),
380
	GATE(PCLK_I2C7, "pclk_i2c7", "pclk_perilp1",			22, 5),
381
	GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1",			22, 3),
382
	GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1",			22, 2),
383
	GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1",			22, 1),
384
	GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1",			22, 0),
385

386
	/* CRU_CLKGATE_CON23 */
387
	/* 15 - 14 unused */
388
	GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1",			23, 13),
389
	GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1",			23, 12),
390
	GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1",			23, 11),
391
	GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1",			23, 10),
392
	GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0",			23, 9),
393
	GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0",			23, 8),
394
	GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0",		23, 7),
395
	GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0",		23, 6),
396
	GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0",		23, 5),
397
	GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0",		23, 4),
398
	GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0",		23, 3),
399
	GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0",		23, 2),
400
	GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0",			23, 1),
401
	GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0",		23, 0),
402

403
	/* CRU_CLKGATE_CON24 */
404
	GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0",		24, 15),
405
	GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0",		24, 14),
406
	GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1",	24, 13),
407
	GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s",	24, 11),
408
	GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 		24, 10),
409
	GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 		24, 9),
410
	GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s",		24, 8),
411
	/* 7 - unused */
412
	GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0",		24, 6),
413
	GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0",		24, 5),
414
	GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0",			24, 4),
415
	/* 3 - 0 unused */
416

417
	/* CRU_CLKGATE_CON25 */
418
	/* 15 - 13 unused */
419
	GATE(0, "hclk_sdio_noc", "hclk_perilp1",			25, 12),
420
	GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s",	25, 11),
421
	GATE(0, "pclk_perilp1_noc", "pclk_perilp1",			25, 10),
422
	GATE(0, "hclk_perilp1_noc", "hclk_perilp1",			25, 9),
423
	GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0",	25, 8),
424
	GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0",	25, 7),
425
	GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0",	25, 6),
426
	GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0",	25, 5),
427
	/* 4 - 0 unused */
428

429
	/* CRU_CLKGATE_CON26 */
430
	/* 15 - 12 unused */
431
	GATE(SCLK_TIMER11, "clk_timer11", "xin24m",			26, 11),
432
	GATE(SCLK_TIMER10, "clk_timer10", "xin24m",			26, 10),
433
	GATE(SCLK_TIMER09, "clk_timer09", "xin24m",			26, 9),
434
	GATE(SCLK_TIMER08, "clk_timer08", "xin24m",			26, 8),
435
	GATE(SCLK_TIMER07, "clk_timer07", "xin24m",			26, 7),
436
	GATE(SCLK_TIMER06, "clk_timer06", "xin24m",			26, 6),
437
	GATE(SCLK_TIMER05, "clk_timer05", "xin24m",			26, 5),
438
	GATE(SCLK_TIMER04, "clk_timer04", "xin24m",			26, 4),
439
	GATE(SCLK_TIMER03, "clk_timer03", "xin24m",			26, 3),
440
	GATE(SCLK_TIMER02, "clk_timer02", "xin24m",			26, 2),
441
	GATE(SCLK_TIMER01, "clk_timer01", "xin24m",			26, 1),
442
	GATE(SCLK_TIMER00, "clk_timer00", "xin24m",			26, 0),
443

444
	/* CRU_CLKGATE_CON27 */
445
	/* 15 - 9 unused */
446
	GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 	27, 8),
447
	GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 	27, 7),
448
	GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif",	27, 6),
449
	GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 	27, 5),
450
	GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 	27, 4),
451
	GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1",		27, 3),
452
	GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1",		27, 2),
453
	GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0",		27, 1),
454
	GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0",		27, 0),
455

456
	/* CRU_CLKGATE_CON28 */
457
	/* 15 - 8 unused */
458
	GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre",			28, 7),
459
	GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre",			28, 6),
460
	GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre",		28, 5),
461
	GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre",		28, 4),
462
	GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre",			28, 3),
463
	GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre",			28, 2),
464
	GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre",		28, 1),
465
	GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre",		28, 0),
466

467
	/* CRU_CLKGATE_CON29 */
468
	/* 15 - 13 unused */
469
	GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio",			29, 12),
470
	GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp",			29, 11),
471
	GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp",			29, 10),
472
	GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp",			29, 9),
473
	GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp",			29, 8),
474
	GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp",			29, 7),
475
	GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp",		29, 6),
476
	GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp",		29, 5),
477
	GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp",		29, 4),
478
	GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp",		29, 3),
479
	GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 		29, 2),
480
	GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 		29, 1),
481
	GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio",			29, 0),
482

483
	/* CRU_CLKGATE_CON30 */
484
	/* 15 - 12 unused */
485
	GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 		30, 11),
486
	GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre",		30, 10),
487
	/* 9 unused */
488
	GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre",			30, 8),
489
	/* 7 - 5 unused */
490
	GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3",		30, 4),
491
	GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 30, 3),
492
	GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3",		30, 2),
493
	GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3",		30, 1),
494
	GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3",		30, 0),
495

496
	/* CRU_CLKGATE_CON31 */
497
	/* 15 - 11 unused */
498
	GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive",			31, 10),
499
	GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive",	31, 9),
500
	GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp",		31, 8),
501
	GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive",			31, 7),
502
	GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive",			31, 6),
503
	GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive",			31, 5),
504
	GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive",			31, 4),
505
	GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive",			31, 3),
506
	GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive",		31, 2),
507
	GATE(PCLK_GRF, "pclk_grf", "pclk_alive",			31, 1),
508
	/* 0 unused */
509

510
	/* CRU_CLKGATE_CON32 */
511
	/* 15 - 14 unused */
512
	GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp",		32, 13),
513
	GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp",			32, 12),
514
	/* 11 unused */
515
	GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc",		32, 10),
516
	GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc",		32, 9),
517
	GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc",		32, 8),
518
	/* 7 - 5 unused */
519
	GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre",		32, 4),
520
	GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", 		32, 3),
521
	GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre",			32, 2),
522
	GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre",		32, 1),
523
	GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre",			32, 0),
524

525
	/* CRU_CLKGATE_CON33 */
526
	/* 15 - 10 unused */
527
	GATE(0, "hclk_sdmmc_noc", "hclk_sd",				33, 9),
528
	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 			33, 8),
529
	GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", 33, 5),
530
	GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", 33, 4),
531
	GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", 33, 3),
532
	GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", 33, 2),
533
	GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre",		33, 1),
534
	GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre",			33, 0),
535

536
	/* CRU_CLKGATE_CON34 */
537
	/* 15 - 7 unused */
538
	GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1",			34, 6),
539
	GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1",			34, 5),
540
	GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1",			34, 4),
541
	GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1",			34, 3),
542
	GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1",		34, 2),
543
	GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1",		34, 1),
544
	GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1",		34, 0),
545
};
546

547
#define PLL_RATE(_hz, _ref, _fb, _post1, _post2, _dspd)			\
548
{									\
549
	.freq = _hz,							\
550
	.refdiv = _ref,							\
551
	.fbdiv = _fb,							\
552
	.postdiv1 = _post1,						\
553
	.postdiv2 = _post2,						\
554
	.dsmpd = _dspd,							\
555
}
556

557
static struct rk_clk_pll_rate rk3399_pll_rates[] = {
558
	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
559
	PLL_RATE(2208000000,  1,  92, 1, 1, 1),
560
	PLL_RATE(2184000000,  1,  91, 1, 1, 1),
561
	PLL_RATE(2160000000,  1,  90, 1, 1, 1),
562
	PLL_RATE(2136000000,  1,  89, 1, 1, 1),
563
	PLL_RATE(2112000000,  1,  88, 1, 1, 1),
564
	PLL_RATE(2088000000,  1,  87, 1, 1, 1),
565
	PLL_RATE(2064000000,  1,  86, 1, 1, 1),
566
	PLL_RATE(2040000000,  1,  85, 1, 1, 1),
567
	PLL_RATE(2016000000,  1,  84, 1, 1, 1),
568
	PLL_RATE(1992000000,  1,  83, 1, 1, 1),
569
	PLL_RATE(1968000000,  1,  82, 1, 1, 1),
570
	PLL_RATE(1944000000,  1,  81, 1, 1, 1),
571
	PLL_RATE(1920000000,  1,  80, 1, 1, 1),
572
	PLL_RATE(1896000000,  1,  79, 1, 1, 1),
573
	PLL_RATE(1872000000,  1,  78, 1, 1, 1),
574
	PLL_RATE(1848000000,  1,  77, 1, 1, 1),
575
	PLL_RATE(1824000000,  1,  76, 1, 1, 1),
576
	PLL_RATE(1800000000,  1,  75, 1, 1, 1),
577
	PLL_RATE(1776000000,  1,  74, 1, 1, 1),
578
	PLL_RATE(1752000000,  1,  73, 1, 1, 1),
579
	PLL_RATE(1728000000,  1,  72, 1, 1, 1),
580
	PLL_RATE(1704000000,  1,  71, 1, 1, 1),
581
	PLL_RATE(1680000000,  1,  70, 1, 1, 1),
582
	PLL_RATE(1656000000,  1,  69, 1, 1, 1),
583
	PLL_RATE(1632000000,  1,  68, 1, 1, 1),
584
	PLL_RATE(1608000000,  1,  67, 1, 1, 1),
585
	PLL_RATE(1600000000,  3, 200, 1, 1, 1),
586
	PLL_RATE(1584000000,  1,  66, 1, 1, 1),
587
	PLL_RATE(1560000000,  1,  65, 1, 1, 1),
588
	PLL_RATE(1536000000,  1,  64, 1, 1, 1),
589
	PLL_RATE(1512000000,  1,  63, 1, 1, 1),
590
	PLL_RATE(1488000000,  1,  62, 1, 1, 1),
591
	PLL_RATE(1464000000,  1,  61, 1, 1, 1),
592
	PLL_RATE(1440000000,  1,  60, 1, 1, 1),
593
	PLL_RATE(1416000000,  1,  59, 1, 1, 1),
594
	PLL_RATE(1392000000,  1,  58, 1, 1, 1),
595
	PLL_RATE(1368000000,  1,  57, 1, 1, 1),
596
	PLL_RATE(1344000000,  1,  56, 1, 1, 1),
597
	PLL_RATE(1320000000,  1,  55, 1, 1, 1),
598
	PLL_RATE(1296000000,  1,  54, 1, 1, 1),
599
	PLL_RATE(1272000000,  1,  53, 1, 1, 1),
600
	PLL_RATE(1248000000,  1,  52, 1, 1, 1),
601
	PLL_RATE(1200000000,  1,  50, 1, 1, 1),
602
	PLL_RATE(1188000000,  2,  99, 1, 1, 1),
603
	PLL_RATE(1104000000,  1,  46, 1, 1, 1),
604
	PLL_RATE(1100000000, 12, 550, 1, 1, 1),
605
	PLL_RATE(1008000000,  1,  84, 2, 1, 1),
606
	PLL_RATE(1000000000,  1, 125, 3, 1, 1),
607
	PLL_RATE( 984000000,  1,  82, 2, 1, 1),
608
	PLL_RATE( 960000000,  1,  80, 2, 1, 1),
609
	PLL_RATE( 936000000,  1,  78, 2, 1, 1),
610
	PLL_RATE( 912000000,  1,  76, 2, 1, 1),
611
	PLL_RATE( 900000000,  4, 300, 2, 1, 1),
612
	PLL_RATE( 888000000,  1,  74, 2, 1, 1),
613
	PLL_RATE( 864000000,  1,  72, 2, 1, 1),
614
	PLL_RATE( 840000000,  1,  70, 2, 1, 1),
615
	PLL_RATE( 816000000,  1,  68, 2, 1, 1),
616
	PLL_RATE( 800000000,  1, 100, 3, 1, 1),
617
	PLL_RATE( 700000000,  6, 350, 2, 1, 1),
618
	PLL_RATE( 696000000,  1,  58, 2, 1, 1),
619
	PLL_RATE( 676000000,  3, 169, 2, 1, 1),
620
	PLL_RATE( 600000000,  1,  75, 3, 1, 1),
621
	PLL_RATE( 594000000,  1,  99, 4, 1, 1),
622
	PLL_RATE( 533250000,  8, 711, 4, 1, 1),
623
	PLL_RATE( 504000000,  1,  63, 3, 1, 1),
624
	PLL_RATE( 500000000,  6, 250, 2, 1, 1),
625
	PLL_RATE( 408000000,  1,  68, 2, 2, 1),
626
	PLL_RATE( 312000000,  1,  52, 2, 2, 1),
627
	PLL_RATE( 297000000,  1,  99, 4, 2, 1),
628
	PLL_RATE( 216000000,  1,  72, 4, 2, 1),
629
	PLL_RATE( 148500000,  1,  99, 4, 4, 1),
630
	PLL_RATE( 106500000,  1,  71, 4, 4, 1),
631
	PLL_RATE(  96000000,  1,  64, 4, 4, 1),
632
	PLL_RATE(  74250000,  2,  99, 4, 4, 1),
633
	PLL_RATE(  65000000,  1,  65, 6, 4, 1),
634
	PLL_RATE(  54000000,  1,  54, 6, 4, 1),
635
	PLL_RATE(  27000000,  1,  27, 6, 4, 1),
636
	{},
637
};
638

639
static struct rk_clk_armclk_rates rk3399_cpu_l_rates[]  = {
640
	{1800000000, 1},
641
	{1704000000, 1},
642
	{1608000000, 1},
643
	{1512000000, 1},
644
	{1488000000, 1},
645
	{1416000000, 1},
646
	{1200000000, 1},
647
	{1008000000, 1},
648
	{ 816000000, 1},
649
	{ 696000000, 1},
650
	{ 600000000, 1},
651
	{ 408000000, 1},
652
	{ 312000000, 1},
653
	{ 216000000, 1},
654
	{  96000000, 1},
655
};
656

657
static struct rk_clk_armclk_rates rk3399_cpu_b_rates[] = {
658
	{2208000000, 1},
659
	{2184000000, 1},
660
	{2088000000, 1},
661
	{2040000000, 1},
662
	{2016000000, 1},
663
	{1992000000, 1},
664
	{1896000000, 1},
665
	{1800000000, 1},
666
	{1704000000, 1},
667
	{1608000000, 1},
668
	{1512000000, 1},
669
	{1488000000, 1},
670
	{1416000000, 1},
671
	{1200000000, 1},
672
	{1008000000, 1},
673
	{ 816000000, 1},
674
	{ 696000000, 1},
675
	{ 600000000, 1},
676
	{ 408000000, 1},
677
	{ 312000000, 1},
678
	{ 216000000, 1},
679
	{  96000000, 1},
680
};
681

682
/* Standard PLL. */
683
#define PLL(_id, _name, _base)						\
684
{									\
685
	.type = RK3399_CLK_PLL,						\
686
	.clk.pll = &(struct rk_clk_pll_def) {				\
687
		.clkdef.id = _id,					\
688
		.clkdef.name = _name,					\
689
		.clkdef.parent_names = pll_src_p,			\
690
		.clkdef.parent_cnt = nitems(pll_src_p),			\
691
		.clkdef.flags = CLK_NODE_STATIC_STRINGS,		\
692
		.base_offset = _base,					\
693
		.rates = rk3399_pll_rates,				\
694
	},								\
695
}
696

697
PLIST(pll_src_p) = {"xin24m", "xin32k"};
698

699
PLIST(armclkl_p) = {"clk_core_l_lpll_src", "clk_core_l_bpll_src",
700
		    "clk_core_l_dpll_src", "clk_core_l_gpll_src"};
701
PLIST(armclkb_p) = {"clk_core_b_lpll_src", "clk_core_b_bpll_src",
702
		    "clk_core_b_dpll_src", "clk_core_b_gpll_src"};
703
PLIST(ddrclk_p) = {"clk_ddrc_lpll_src", "clk_ddrc_bpll_src",
704
		   "clk_ddrc_dpll_src", "clk_ddrc_gpll_src"};
705
PLIST(pll_src_cpll_gpll_p) =		{"cpll", "gpll"};
706
PLIST(pll_src_cpll_gpll_ppll_p) =	{"cpll", "gpll", "ppll"};
707
PLIST(pll_src_cpll_gpll_upll_p) =	{"cpll", "gpll", "upll"};
708
PLIST(pll_src_npll_cpll_gpll_p) =	{"npll", "cpll", "gpll"};
709
PLIST(pll_src_cpll_gpll_npll_npll_p) =	{"cpll", "gpll", "npll", "npll"};
710
PLIST(pll_src_cpll_gpll_npll_ppll_p) =	{"cpll", "gpll", "npll", "ppll" };
711
PLIST(pll_src_cpll_gpll_npll_24m_p) =	{"cpll", "gpll", "npll",  "xin24m" };
712
PLIST(pll_src_cpll_gpll_npll_usbphy480m_p)= {"cpll", "gpll", "npll", "clk_usbphy_480m" };
713
PLIST(pll_src_ppll_cpll_gpll_npll_upll_p) = { "ppll", "cpll", "gpll", "npll", "upll" };
714
PLIST(pll_src_cpll_gpll_npll_upll_24m_p)= { "cpll", "gpll", "npll", "upll", "xin24m" };
715
PLIST(pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",  "ppll", "upll", "xin24m" };
716
PLIST(pll_src_vpll_cpll_gpll_gpll_p) = 	{"vpll", "cpll", "gpll", "gpll"};
717
PLIST(pll_src_vpll_cpll_gpll_npll_p) = 	{"vpll", "cpll", "gpll", "npll"};
718

719
PLIST(aclk_cci_p) = {"cpll_aclk_cci_src", "gpll_aclk_cci_src",
720
		     "npll_aclk_cci_src", "vpll_aclk_cci_src"};
721
PLIST(cci_trace_p) = {"cpll_cci_trace","gpll_cci_trace"};
722
PLIST(cs_p)= {"cpll_cs", "gpll_cs", "npll_cs","npll_cs"};
723
PLIST(aclk_perihp_p)= {"cpll_aclk_perihp_src", "gpll_aclk_perihp_src" };
724
PLIST(dclk_vop0_p) =	{"dclk_vop0_div", "dclk_vop0_frac"};
725
PLIST(dclk_vop1_p)= 	{"dclk_vop1_div", "dclk_vop1_frac"};
726

727
PLIST(clk_cif_p) = 	{"clk_cifout_src", "xin24m"};
728

729
PLIST(pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m"};
730
PLIST(pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m"};
731
PLIST(pll_src_24m_32k_cpll_gpll_p)= {"xin24m", "xin32k", "cpll", "gpll"};
732
PLIST(pciecore_cru_phy_p) = {"clk_pcie_core_cru", "clk_pcie_core_phy"};
733

734
PLIST(aclk_emmc_p)		= { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src"};
735

736
PLIST(aclk_perilp0_p)		= { "cpll_aclk_perilp0_src",
737
					    "gpll_aclk_perilp0_src" };
738

739
PLIST(fclk_cm0s_p)			= { "cpll_fclk_cm0s_src",
740
					    "gpll_fclk_cm0s_src" };
741

742
PLIST(hclk_perilp1_p)		= { "cpll_hclk_perilp1_src",
743
					    "gpll_hclk_perilp1_src" };
744

745
PLIST(clk_testout1_p)		= { "clk_testout1_pll_src", "xin24m" };
746
PLIST(clk_testout2_p)		= { "clk_testout2_pll_src", "xin24m" };
747

748
PLIST(usbphy_480m_p)		= { "clk_usbphy0_480m_src",
749
					    "clk_usbphy1_480m_src" };
750
PLIST(aclk_gmac_p)		= { "cpll_aclk_gmac_src",
751
				    "gpll_aclk_gmac_src" };
752
PLIST(rmii_p)			= { "clk_gmac", "clkin_gmac" };
753
PLIST(spdif_p)			= { "clk_spdif_div", "clk_spdif_frac",
754
				    "clkin_i2s", "xin12m" };
755
PLIST(i2s0_p)			= { "clk_i2s0_div", "clk_i2s0_frac",
756
				    "clkin_i2s", "xin12m" };
757
PLIST(i2s1_p)			= { "clk_i2s1_div", "clk_i2s1_frac",
758
				    "clkin_i2s", "xin12m" };
759
PLIST(i2s2_p)			= { "clk_i2s2_div", "clk_i2s2_frac",
760
				    "clkin_i2s", "xin12m" };
761
PLIST(i2sch_p)			= {"clk_i2s0", "clk_i2s1", "clk_i2s2"};
762
PLIST(i2sout_p)			= {"clk_i2sout_src", "xin12m"};
763

764
PLIST(uart0_p)= {"clk_uart0_div", "clk_uart0_frac", "xin24m"};
765
PLIST(uart1_p)= {"clk_uart1_div", "clk_uart1_frac", "xin24m"};
766
PLIST(uart2_p)= {"clk_uart2_div", "clk_uart2_frac", "xin24m"};
767
PLIST(uart3_p)= {"clk_uart3_div", "clk_uart3_frac", "xin24m"};
768

769
static struct rk_clk rk3399_clks[] = {
770
	/* External clocks */
771
	LINK("xin24m"),
772
	LINK("xin32k"),
773
	FFACT(0, "xin12m", "xin24m", 1, 2),
774
	FRATE(0, "clkin_i2s", 0),
775
	FRATE(0, "pclkin_cif", 0),
776
	LINK("clk_usbphy0_480m"),
777
	LINK("clk_usbphy1_480m"),
778
	LINK("clkin_gmac"),
779
	FRATE(0, "clk_pcie_core_phy", 0),
780
	FFACT(0, "clk_ddrc_div2", "clk_ddrc", 1, 2),
781

782
	/* PLLs */
783
	PLL(PLL_APLLL, "lpll", 0x00),
784
	PLL(PLL_APLLB, "bpll", 0x20),
785
	PLL(PLL_DPLL,  "dpll", 0x40),
786
	PLL(PLL_CPLL,  "cpll", 0x60),
787
	PLL(PLL_GPLL,  "gpll", 0x80),
788
	PLL(PLL_NPLL,  "npll", 0xA0),
789
	PLL(PLL_VPLL,  "vpll", 0xC0),
790

791
	/*  CRU_CLKSEL_CON0 */
792
	CDIV(0, "aclkm_core_l_c", "armclkl", 0,
793
	    0, 8, 5),
794
	ARMDIV(ARMCLKL, "armclkl", armclkl_p, rk3399_cpu_l_rates,
795
	    0, 0, 5,	6, 2, 0, 3),
796
	/* CRU_CLKSEL_CON1 */
797
	CDIV(0, "pclk_dbg_core_l_c", "armclkl", 0,
798
	    1, 8, 5),
799
	CDIV(0, "atclk_core_l_c", "armclkl", 0,
800
	    1, 0, 5),
801

802
	/* CRU_CLKSEL_CON2 */
803
	CDIV(0, "aclkm_core_b_c", "armclkb", 0,
804
	    2, 8, 5),
805
	ARMDIV(ARMCLKB, "armclkb", armclkb_p, rk3399_cpu_b_rates,
806
	    2, 0, 5,	6, 2, 1, 3),
807

808
	/* CRU_CLKSEL_CON3 */
809
	CDIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", 0,
810
	    3, 13, 2),
811
	CDIV(0, "pclk_dbg_core_b_c", "armclkb", 0,
812
	    3, 8, 5),
813
	CDIV(0, "atclk_core_b_c", "armclkb", 0,
814
	    3, 0, 5),
815

816
	/* CRU_CLKSEL_CON4 */
817
	COMP(0, "clk_cs", cs_p, 0,
818
	    4, 0, 5,	6, 2),
819

820
	/* CRU_CLKSEL_CON5 */
821
	COMP(0, "clk_cci_trace_c", cci_trace_p, 0,
822
	    5, 8, 5,	15, 1),
823
	COMP(0, "aclk_cci_pre_c", aclk_cci_p, 0,
824
	    5, 0, 5, 	6, 2),
825

826
	/*  CRU_CLKSEL_CON6 */
827
	COMP(0, "pclk_ddr_c", pll_src_cpll_gpll_p, 0,
828
	    6, 8, 5,	15, 1),
829
	COMP(SCLK_DDRC, "clk_ddrc", ddrclk_p, 0,
830
	    6, 0, 3, 	4, 2),
831

832
	/* CRU_CLKSEL_CON7 */
833
	CDIV(0, "hclk_vcodec_pre_c", "aclk_vcodec_pre", 0,
834
	    7, 8, 5),
835
	COMP(0, "aclk_vcodec_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
836
	    7, 0, 5,	6, 2),
837

838
	/* CRU_CLKSEL_CON8 */
839
	CDIV(0, "hclk_vdu_pre_c", "aclk_vdu_pre", 0,
840
	    8, 8, 5),
841
	COMP(0, "aclk_vdu_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
842
	    8, 0, 5,	6, 2),
843

844
	/* CRU_CLKSEL_CON9 */
845
	COMP(0, "clk_vdu_ca_c", pll_src_cpll_gpll_npll_npll_p, 0,
846
	    9, 8, 5,	14, 2),
847
	COMP(0, "clk_vdu_core_c", pll_src_cpll_gpll_npll_npll_p, 0,
848
	    9, 0, 5,	6, 2),
849

850
	/* CRU_CLKSEL_CON10 */
851
	CDIV(0, "hclk_iep_pre_c", "aclk_iep_pre", 0,
852
	    10, 8, 5),
853
	COMP(0, "aclk_iep_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
854
	    10, 0, 5, 	6, 2),
855

856
	/* CRU_CLKSEL_CON11 */
857
	CDIV(0, "hclk_rga_pre_c", "aclk_rga_pre", 0,
858
	    11, 8, 5),
859
	COMP(0, "aclk_rga_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
860
	    11, 0, 5,	 6, 2),
861

862
	/* CRU_CLKSEL_CON12 */
863
	COMP(0, "aclk_center_c", pll_src_cpll_gpll_npll_npll_p, 0,
864
	    12, 8, 5, 	14, 2),
865
	COMP(SCLK_RGA_CORE, "clk_rga_core_c", pll_src_cpll_gpll_npll_ppll_p, 0,
866
	    12, 0, 5, 	6, 2),
867

868
	/* CRU_CLKSEL_CON13 */
869
	COMP(0, "hclk_sd_c", pll_src_cpll_gpll_p, 0,
870
	    13, 8, 5,	15, 1),
871
	COMP(0, "aclk_gpu_pre_c", pll_src_ppll_cpll_gpll_npll_upll_p, 0,
872
	    13, 0, 5,	5, 3),
873

874
	/* CRU_CLKSEL_CON14 */
875
	MUX(0, "upll", pll_src_24m_usbphy480m_p, 0,
876
	    14, 	15, 1),
877
	CDIV(0, "pclk_perihp_c", "aclk_perihp", 0,
878
	    14, 12, 2),
879
	CDIV(0, "hclk_perihp_c", "aclk_perihp", 0,
880
	    14, 8, 2),
881
	MUX(0, "clk_usbphy_480m", usbphy_480m_p, 0,
882
	    14,		 6, 1),
883
	COMP(0, "aclk_perihp_c", aclk_perihp_p, 0,
884
	    14, 0, 5,	7, 1),
885

886
	/* CRU_CLKSEL_CON15 */
887
	COMP(0, "clk_sdio_c", pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
888
	    15, 0, 7,	8, 3),
889

890
	/* CRU_CLKSEL_CON16 */
891
	COMP(0, "clk_sdmmc_c", pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
892
	    16, 0, 7,	8, 3),
893

894
	/* CRU_CLKSEL_CON17 */
895
	COMP(0, "clk_pcie_pm_c", pll_src_cpll_gpll_npll_24m_p, 0,
896
	    17, 0, 7,	8, 3),
897

898
	/* CRU_CLKSEL_CON18 */
899
	CDIV(0, "clk_pciephy_ref100m_c", "npll", 0,
900
	    18, 11, 5),
901
	MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", pll_src_24m_pciephy_p, 0,
902
	    18,		10, 1),
903
	MUX(SCLK_PCIE_CORE, "clk_pcie_core", pciecore_cru_phy_p, 0,
904
	    18,		7, 1),
905
	COMP(0, "clk_pcie_core_cru_c", pll_src_cpll_gpll_npll_npll_p, 0,
906
	    18, 0, 7,	8, 2),
907

908
	/* CRU_CLKSEL_CON19 */
909
	CDIV(0, "pclk_gmac_pre_c", "aclk_gmac_pre", 0,
910
	    19, 8, 3),
911
	MUX(SCLK_RMII_SRC, "clk_rmii_src",rmii_p, 0,
912
	    19,		4, 1),
913
	MUX(SCLK_HSICPHY, "clk_hsicphy_c", pll_src_cpll_gpll_npll_usbphy480m_p, 0,
914
	    19,		0, 2),
915

916
	/* CRU_CLKSEL_CON20 */
917
	COMP(0, "clk_gmac_c", pll_src_cpll_gpll_npll_npll_p, 0,
918
	    20, 8, 5,	14, 2),
919
	COMP(0, "aclk_gmac_pre_c", aclk_gmac_p, 0,
920
	    20, 0, 5,	7, 1),
921

922
	/* CRU_CLKSEL_CON21 */
923
	COMP(ACLK_EMMC, "aclk_emmc", aclk_emmc_p, 0,
924
	    21, 0, 5,	7, 1),
925

926
	/* CRU_CLKSEL_CON22 */
927
	COMP(0, "clk_emmc_c", pll_src_cpll_gpll_npll_upll_24m_p, 0,
928
	    22, 0, 7,	8, 3),
929

930
	/* CRU_CLKSEL_CON23 */
931
	CDIV(0, "pclk_perilp0_c", "aclk_perilp0", 0,
932
	    23, 12, 3),
933
	CDIV(0, "hclk_perilp0_c", "aclk_perilp0", 0,
934
	    23, 8, 2),
935
	COMP(0, "aclk_perilp0_c", aclk_perilp0_p, 0,
936
	    23, 0, 5,	7, 1),
937

938
	/* CRU_CLKSEL_CON24 */
939
	COMP(0, "fclk_cm0s_c", fclk_cm0s_p, 0,
940
	    24, 8, 5,	15, 1),
941
	COMP(0, "clk_crypto0_c", pll_src_cpll_gpll_ppll_p, 0,
942
	    24, 0, 5,	6, 2),
943

944
	/* CRU_CLKSEL_CON25 */
945
	CDIV(0, "pclk_perilp1_c", "hclk_perilp1", 0,
946
	    25, 8, 3),
947
	COMP(HCLK_PERILP1, "hclk_perilp1", hclk_perilp1_p, 0,
948
	    25, 0, 5,	7, 1),
949

950
	/* CRU_CLKSEL_CON26 */
951
	CDIV(0, "clk_saradc_c", "xin24m", 0,
952
	    26, 8, 8),
953
	COMP(0, "clk_crypto1_c", pll_src_cpll_gpll_ppll_p, 0,
954
	    26, 0, 5,	6, 2),
955

956
	/* CRU_CLKSEL_CON27 */
957
	COMP(0, "clk_tsadc_c", pll_src_p, 0,
958
	    27, 0, 10,	15, 1),
959

960
	/* CRU_CLKSEL_CON28 */
961
	MUX(0, "clk_i2s0_mux", i2s0_p, RK_CLK_MUX_REPARENT,
962
	    28, 8, 2),
963
	COMP(0, "clk_i2s0_div_c", pll_src_cpll_gpll_p, 0,
964
	    28, 0, 7,	7, 1),
965

966
	/* CRU_CLKSEL_CON29 */
967
	MUX(0, "clk_i2s1_mux", i2s1_p, RK_CLK_MUX_REPARENT,
968
	    29,		8, 2),
969
	COMP(0, "clk_i2s1_div_c", pll_src_cpll_gpll_p, 0,
970
	    29, 0, 7,	7, 1),
971

972
	/* CRU_CLKSEL_CON30 */
973
	MUX(0, "clk_i2s2_mux", i2s2_p, RK_CLK_MUX_REPARENT,
974
	    30,		8, 2),
975
	COMP(0, "clk_i2s2_div_c", pll_src_cpll_gpll_p, 0,
976
	    30, 0, 7,	7, 1),
977

978
	/* CRU_CLKSEL_CON31 */
979
	MUX(0, "clk_i2sout_c", i2sout_p, 0,
980
	    31,		2, 1),
981
	MUX(0, "clk_i2sout_src", i2sch_p, 0,
982
	    31,		0, 2),
983

984
	/* CRU_CLKSEL_CON32 */
985
	COMP(0, "clk_spdif_rec_dptx_c", pll_src_cpll_gpll_p, 0,
986
	    32, 8, 5,	15, 1),
987
	MUX(0, "clk_spdif_mux", spdif_p, 0,
988
	    32,		13, 2),
989
	COMP(0, "clk_spdif_div_c", pll_src_cpll_gpll_p, 0,
990
	    32, 0, 7,	7, 1),
991

992
	/* CRU_CLKSEL_CON33 */
993
	MUX(0, "clk_uart_src", pll_src_cpll_gpll_p, 0,
994
	    33,		15, 1),
995
	MUX(0, "clk_uart0_src", pll_src_cpll_gpll_upll_p, 0,
996
	    33,		12, 2),
997
	MUX(SCLK_UART0, "clk_uart0", uart0_p, 0,
998
	    33,		8, 2),
999
	CDIV(0, "clk_uart0_div_c", "clk_uart0_src", 0,
1000
	    33, 0, 7),
1001

1002
	/* CRU_CLKSEL_CON34 */
1003
	MUX(SCLK_UART1, "clk_uart1", uart1_p, 0,
1004
	    34,		8, 2),
1005
	CDIV(0, "clk_uart1_div_c", "clk_uart_src", 0,
1006
	    34, 0, 7),
1007

1008
	/* CRU_CLKSEL_CON35 */
1009
	MUX(SCLK_UART2, "clk_uart2", uart2_p, 0,
1010
	    35,		8, 2),
1011
	CDIV(0, "clk_uart2_div_c", "clk_uart_src", 0,
1012
	    35, 0, 7),
1013

1014
	/* CRU_CLKSEL_CON36 */
1015
	MUX(SCLK_UART3, "clk_uart3", uart3_p, 0,
1016
	    36,		8, 2),
1017
	CDIV(0, "clk_uart3_div_c", "clk_uart_src", 0,
1018
	    36, 0, 7),
1019

1020
	/* CRU_CLKSEL_CON37 */
1021
	/* unused */
1022

1023
	/* CRU_CLKSEL_CON38 */
1024
	MUX(0, "clk_testout2_pll_src", pll_src_cpll_gpll_npll_npll_p, 0,
1025
	    38,		14, 2),
1026
	COMP(0, "clk_testout2_c", clk_testout2_p, 0,
1027
	    38, 8, 5,	13, 1),
1028
	MUX(0, "clk_testout1_pll_src", pll_src_cpll_gpll_npll_npll_p, 0,
1029
	    38,		6, 2),
1030
	COMP(0, "clk_testout1_c", clk_testout1_p, 0,
1031
	    38, 0, 5,	5, 1),
1032

1033
	/* CRU_CLKSEL_CON39 */
1034
	COMP(0, "aclk_usb3_c", pll_src_cpll_gpll_npll_npll_p, 0,
1035
	    39, 0, 5,	6, 2),
1036

1037
	/* CRU_CLKSEL_CON40 */
1038
	COMP(0, "clk_usb3otg0_suspend_c", pll_src_p, 0,
1039
	    40, 0, 10,	15, 1),
1040

1041
	/* CRU_CLKSEL_CON41 */
1042
	COMP(0, "clk_usb3otg1_suspend_c", pll_src_p, 0,
1043
	    41, 0, 10,	15, 1),
1044

1045
	/* CRU_CLKSEL_CON42 */
1046
	COMP(0, "aclk_hdcp_c", pll_src_cpll_gpll_ppll_p, 0,
1047
	    42, 8, 5,	14, 2),
1048
	COMP(0, "aclk_vio_c", pll_src_cpll_gpll_ppll_p, 0,
1049
	    42, 0, 5,	6, 2),
1050

1051
	/* CRU_CLKSEL_CON43 */
1052
	CDIV(0, "pclk_hdcp_c", "aclk_hdcp", 0,
1053
	    43, 10, 5),
1054
	CDIV(0, "hclk_hdcp_c", "aclk_hdcp", 0,
1055
	    43, 5, 5),
1056
	CDIV(0, "pclk_vio_c", "aclk_vio", 0,
1057
	    43, 0, 5),
1058

1059
	/* CRU_CLKSEL_CON44 */
1060
	COMP(0, "pclk_edp_c", pll_src_cpll_gpll_p, 0,
1061
	    44, 8, 6,	15, 1),
1062

1063
	/* CRU_CLKSEL_CON45  - XXX clocks in mux are reversed in TRM !!!*/
1064
	COMP(0, "clk_hdmi_cec_c", pll_src_p, 0,
1065
	    45, 0, 10,	15, 1),
1066

1067
	/* CRU_CLKSEL_CON46 */
1068
	COMP(0, "clk_dp_core_c", pll_src_npll_cpll_gpll_p, 0,
1069
	    46, 0, 5,	6, 2),
1070

1071
	/* CRU_CLKSEL_CON47 */
1072
	CDIV(0, "hclk_vop0_pre_c", "aclk_vop0_pre_c", 0,
1073
	    47, 8, 5),
1074
	COMP(0, "aclk_vop0_pre_c", pll_src_vpll_cpll_gpll_npll_p, 0,
1075
	    47, 0, 5,	6, 2),
1076

1077
	/* CRU_CLKSEL_CON48 */
1078
	CDIV(0, "hclk_vop1_pre_c", "aclk_vop1_pre", 0,
1079
	    48, 8, 5),
1080
	COMP(0, "aclk_vop1_pre_c", pll_src_vpll_cpll_gpll_npll_p, 0,
1081
	    48, 0, 5,	6, 2),
1082

1083
	/* CRU_CLKSEL_CON49 */
1084
	MUX(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, 0,
1085
	    49,		11, 1),
1086
	COMP(0, "dclk_vop0_div_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1087
	    49, 0, 8,	8, 2),
1088

1089
	/* CRU_CLKSEL_CON50 */
1090
	MUX(DCLK_VOP1, "dclk_vop1", dclk_vop1_p, 0,
1091
	    50,		11, 1),
1092
	COMP(0, "dclk_vop1_div_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1093
	    50, 0, 8,	8, 2),
1094

1095
	/* CRU_CLKSEL_CON51 */
1096
	COMP(0, "clk_vop0_pwm_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1097
	    51, 0, 5,	6, 2),
1098

1099
	/* CRU_CLKSEL_CON52 */
1100
	COMP(0, "clk_vop1_pwm_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1101
	    52, 0, 5,	6, 2),
1102

1103
	/* CRU_CLKSEL_CON53 */
1104
	CDIV(0, "hclk_isp0_c", "aclk_isp0", 0,
1105
	    53, 8, 5),
1106
	COMP(0, "aclk_isp0_c", pll_src_cpll_gpll_ppll_p, 0,
1107
	    53, 0, 5,	6, 2),
1108

1109
	/* CRU_CLKSEL_CON54 */
1110
	CDIV(0, "hclk_isp1_c", "aclk_isp1", 0,
1111
	    54, 8, 5),
1112
	COMP(0, "aclk_isp1_c", pll_src_cpll_gpll_ppll_p, 0,
1113
	    54, 0, 5,	6, 2),
1114

1115
	/* CRU_CLKSEL_CON55 */
1116
	COMP(0, "clk_isp1_c", pll_src_cpll_gpll_npll_npll_p, 0,
1117
	    55, 8, 5,	14, 2),
1118
	COMP(0, "clk_isp0_c", pll_src_cpll_gpll_npll_npll_p, 0,
1119
	    55, 0, 5,	6, 2),
1120

1121
	/* CRU_CLKSEL_CON56 */
1122
	COMP(0, "aclk_gic_pre_c", pll_src_cpll_gpll_p, 0,
1123
	    56, 8, 5,	15, 1),
1124
	MUX(0, "clk_cifout_src_c", pll_src_cpll_gpll_npll_npll_p, 0,
1125
	    56,		6, 2),
1126
	COMP(SCLK_CIF_OUT, "clk_cifout", clk_cif_p, 0,
1127
	    56, 0, 5,	5, 1),
1128

1129
	/* CRU_CLKSEL_CON57 */
1130
	CDIV(0, "clk_test_24m", "xin24m", 0,
1131
	    57, 6, 10),
1132
	CDIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
1133
	    57, 0, 5),
1134

1135
	/* CRU_CLKSEL_CON58 */
1136
	COMP(0, "clk_spi5_c", pll_src_cpll_gpll_p, 0,
1137
	    58, 8, 7,	15, 1),
1138
	MUX(0, "clk_test_pre", pll_src_cpll_gpll_p, 0,
1139
	    58,		7, 1),
1140
	CDIV(0, "clk_test_c", "clk_test_pre", 0,
1141
	    58, 0, 5),
1142

1143
	/* CRU_CLKSEL_CON59 */
1144
	COMP(0, "clk_spi1_c", pll_src_cpll_gpll_p, 0,
1145
	    59, 8, 7,	15, 1),
1146
	COMP(0, "clk_spi0_c", pll_src_cpll_gpll_p, 0,
1147
	    59, 0, 7,	7, 1),
1148

1149
	/* CRU_CLKSEL_CON60 */
1150
	COMP(0, "clk_spi4_c", pll_src_cpll_gpll_p, 0,
1151
	    60, 8, 7,	15, 1),
1152
	COMP(0, "clk_spi2_c", pll_src_cpll_gpll_p, 0,
1153
	    60, 0, 7,	7, 1),
1154

1155
	/* CRU_CLKSEL_CON61 */
1156
	COMP(0, "clk_i2c5_c", pll_src_cpll_gpll_p, 0,
1157
	    61, 8, 7,	15, 1),
1158
	COMP(0, "clk_i2c1_c", pll_src_cpll_gpll_p, 0,
1159
	    61, 0, 7,	7, 1),
1160

1161
	/* CRU_CLKSEL_CON62 */
1162
	COMP(0, "clk_i2c6_c", pll_src_cpll_gpll_p, 0,
1163
	    62, 8, 7,	15, 1),
1164
	COMP(0, "clk_i2c2_c", pll_src_cpll_gpll_p, 0,
1165
	    62, 0, 7,	7, 1),
1166

1167
	/* CRU_CLKSEL_CON63 */
1168
	COMP(0, "clk_i2c7_c", pll_src_cpll_gpll_p, 0,
1169
	    63, 8, 7,	15, 1),
1170
	COMP(0, "clk_i2c3_c", pll_src_cpll_gpll_p, 0,
1171
	    63, 0, 7,	7, 1),
1172

1173
	/* CRU_CLKSEL_CON64 */
1174
	COMP(0, "clk_uphy0_tcpdphy_ref_c", pll_src_p, 0,
1175
	    64, 8, 5,	15, 1),
1176
	COMP(0, "clk_uphy0_tcpdcore_c", pll_src_24m_32k_cpll_gpll_p, 0,
1177
	    64, 0, 5,	6, 2),
1178

1179
	/* CRU_CLKSEL_CON65 */
1180
	COMP(0, "clk_uphy1_tcpdphy_ref_c", pll_src_p, 0,
1181
	    65, 8, 5,	15, 1),
1182
	COMP(0, "clk_uphy1_tcpdcore_c", pll_src_24m_32k_cpll_gpll_p, 0,
1183
	    65, 0, 5,	6, 2),
1184

1185
	/* CRU_CLKSEL_CON99  - 107 */
1186
	FRACT(0, "clk_spdif_frac_c", "clk_spdif_div", 0,
1187
	    99),
1188
	FRACT(0, "clk_i2s0_frac_c", "clk_i2s0_div", 0,
1189
	    96),
1190
	FRACT(0, "clk_i2s1_frac_c", "clk_i2s1_div", 0,
1191
	    97),
1192
	FRACT(0, "clk_i2s2_frac_c", "clk_i2s2_div", 0,
1193
	    98),
1194
	FRACT(0, "clk_uart0_frac_c", "clk_uart0_div", 0,
1195
	    100),
1196
	FRACT(0, "clk_uart1_frac_c", "clk_uart1_div", 0,
1197
	    101),
1198
	FRACT(0, "clk_uart2_frac_c", "clk_uart2_div", 0,
1199
	    102),
1200
	FRACT(0, "clk_uart3_frac_c", "clk_uart3_div", 0,
1201
	    103),
1202
	FRACT(0, "clk_test_frac_c", "clk_test_pre", 0,
1203
	    105),
1204
	FRACT(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0,
1205
	    106),
1206
	FRACT(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0,
1207
	    107),
1208

1209
	/* 
1210
	 * This clock is controlled in the secure world
1211
	 */
1212
	FFACT(PCLK_WDT, "pclk_wdt", "pclk_alive", 1, 1),
1213

1214
/* Not yet implemented yet
1215
 *	MMC(SCLK_SDMMC_DRV,     "sdmmc_drv",    "clk_sdmmc", RK3399_SDMMC_CON0, 1),
1216
 *	MMC(SCLK_SDMMC_SAMPLE,  "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
1217
 *	MMC(SCLK_SDIO_DRV,      "sdio_drv",     "clk_sdio",  RK3399_SDIO_CON0,  1),
1218
 *	MMC(SCLK_SDIO_SAMPLE,   "sdio_sample",  "clk_sdio",  RK3399_SDIO_CON1,  1),
1219
 */
1220

1221
};
1222

1223
static int
1224
rk3399_cru_probe(device_t dev)
1225
{
1226

1227
	if (!ofw_bus_status_okay(dev))
1228
		return (ENXIO);
1229

1230
	if (ofw_bus_is_compatible(dev, "rockchip,rk3399-cru")) {
1231
		device_set_desc(dev, "Rockchip RK3399 Clock and Reset Unit");
1232
		return (BUS_PROBE_DEFAULT);
1233
	}
1234

1235
	return (ENXIO);
1236
}
1237

1238
static int
1239
rk3399_cru_attach(device_t dev)
1240
{
1241
	struct rk_cru_softc *sc;
1242

1243
	sc = device_get_softc(dev);
1244
	sc->dev = dev;
1245

1246
	sc->gates = rk3399_gates;
1247
	sc->ngates = nitems(rk3399_gates);
1248

1249
	sc->clks = rk3399_clks;
1250
	sc->nclks = nitems(rk3399_clks);
1251

1252
	sc->reset_offset = 0x400;
1253
	sc->reset_num = 335;
1254

1255
	return (rk_cru_attach(dev));
1256
}
1257

1258
static device_method_t rk3399_cru_methods[] = {
1259
	/* Device interface */
1260
	DEVMETHOD(device_probe,		rk3399_cru_probe),
1261
	DEVMETHOD(device_attach,	rk3399_cru_attach),
1262

1263
	DEVMETHOD_END
1264
};
1265

1266
DEFINE_CLASS_1(rk3399_cru, rk3399_cru_driver, rk3399_cru_methods,
1267
  sizeof(struct rk_cru_softc), rk_cru_driver);
1268

1269
EARLY_DRIVER_MODULE(rk3399_cru, simplebus, rk3399_cru_driver, 0, 0,
1270
    BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
1271

1272
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