Path: blob/main/sys/dev/clk/starfive/jh7110_clk_aon.c
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/*-1* SPDX-License-Identifier: BSD-2-Clause2*3* Copyright 2016 Michal Meloun <[email protected]>4* Copyright (c) 2020 Oskar Holmlund <[email protected]>5* Copyright (c) 2024 Jari Sihvola <[email protected]>6*/78/* Clocks for JH7110 AON group. PLL driver must be attached before this. */910#include <sys/param.h>11#include <sys/systm.h>12#include <sys/bus.h>13#include <sys/kernel.h>14#include <sys/module.h>15#include <sys/mutex.h>16#include <sys/resource.h>17#include <sys/rman.h>18#include <machine/bus.h>1920#include <dev/fdt/simplebus.h>21#include <dev/hwreset/hwreset.h>22#include <dev/ofw/ofw_bus.h>23#include <dev/ofw/ofw_bus_subr.h>2425#include <dev/clk/clk.h>26#include <dev/clk/starfive/jh7110_clk.h>2728#include <dt-bindings/clock/starfive,jh7110-crg.h>2930#include "clkdev_if.h"31#include "hwreset_if.h"3233static struct ofw_compat_data compat_data[] = {34{ "starfive,jh7110-aoncrg", 1 },35{ NULL, 0 }36};3738static struct resource_spec res_spec[] = {39{ SYS_RES_MEMORY, 0, RF_ACTIVE | RF_SHAREABLE },40RESOURCE_SPEC_END41};4243/* parents */44static const char *gmac0_axi_p[] = { "stg_axiahb" };45static const char *gmac0_ahb_p[] = { "stg_axiahb" };46static const char *gmac0_tx_inv_p[] = { "gmac0_tx" };47static const char *gmac0_tx_p[] = { "gmac0_gtxclk", "gmac0_rmii_rtx" };48static const char *gmac0_rmii_rtx_p[] = { "gmac0_rmii_refin" };4950/* AON clocks */51static const struct jh7110_clk_def aon_clks[] = {52JH7110_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", gmac0_axi_p),53JH7110_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", gmac0_ahb_p),54JH7110_GATEMUX(JH7110_AONCLK_GMAC0_TX, "gmac0_tx", gmac0_tx_p),55JH7110_INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", gmac0_tx_inv_p),56JH7110_DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx",57gmac0_rmii_rtx_p, 30),58};5960static int61jh7110_clk_aon_probe(device_t dev)62{63if (!ofw_bus_status_okay(dev))64return (ENXIO);6566if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)67return (ENXIO);6869device_set_desc(dev, "StarFive JH7110 AON clock generator");7071return (BUS_PROBE_DEFAULT);72}7374static int75jh7110_clk_aon_attach(device_t dev)76{77struct jh7110_clkgen_softc *sc;78int err;7980sc = device_get_softc(dev);8182sc->reset_status_offset = AONCRG_RESET_STATUS;83sc->reset_selector_offset = AONCRG_RESET_SELECTOR;8485mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);8687err = bus_alloc_resources(dev, res_spec, &sc->mem_res);88if (err != 0) {89device_printf(dev, "Couldn't allocate resources, error %d\n",90err);91return (ENXIO);92}9394sc->clkdom = clkdom_create(dev);95if (sc->clkdom == NULL) {96device_printf(dev, "Couldn't create clkdom, error %d\n", err);97return (ENXIO);98}99100for (int i = 0; i < nitems(aon_clks); i++) {101err = jh7110_clk_register(sc->clkdom, &aon_clks[i]);102if (err != 0) {103device_printf(dev,104"Couldn't register clk %s, error %d\n",105aon_clks[i].clkdef.name, err);106return (ENXIO);107}108}109110if (clkdom_finit(sc->clkdom) != 0)111panic("Cannot finalize clkdom initialization\n");112113if (bootverbose)114clkdom_dump(sc->clkdom);115116hwreset_register_ofw_provider(dev);117118return (0);119}120121static void122jh7110_clk_aon_device_lock(device_t dev)123{124struct jh7110_clkgen_softc *sc;125126sc = device_get_softc(dev);127mtx_lock(&sc->mtx);128}129130static void131jh7110_clk_aon_device_unlock(device_t dev)132{133struct jh7110_clkgen_softc *sc;134135sc = device_get_softc(dev);136mtx_unlock(&sc->mtx);137}138139static int140jh7110_clk_aon_detach(device_t dev)141{142/* Detach not supported */143return (EBUSY);144}145146static device_method_t jh7110_clk_aon_methods[] = {147/* Device interface */148DEVMETHOD(device_probe, jh7110_clk_aon_probe),149DEVMETHOD(device_attach, jh7110_clk_aon_attach),150DEVMETHOD(device_detach, jh7110_clk_aon_detach),151152/* clkdev interface */153DEVMETHOD(clkdev_device_lock, jh7110_clk_aon_device_lock),154DEVMETHOD(clkdev_device_unlock, jh7110_clk_aon_device_unlock),155156/* Reset interface */157DEVMETHOD(hwreset_assert, jh7110_reset_assert),158DEVMETHOD(hwreset_is_asserted, jh7110_reset_is_asserted),159160DEVMETHOD_END161};162163DEFINE_CLASS_0(jh7110_aon, jh7110_aon_driver, jh7110_clk_aon_methods,164sizeof(struct jh7110_clkgen_softc));165EARLY_DRIVER_MODULE(jh7110_aon, simplebus, jh7110_aon_driver, 0, 0,166BUS_PASS_BUS + BUS_PASS_ORDER_LATE);167MODULE_VERSION(jh7110_aon, 1);168169170