CoCalc -- jh7110_clk

GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/dev/clk/starfive/jh7110_clk_sys.c
³⁹⁵³⁷ views
1
/*-
2
 * SPDX-License-Identifier: BSD-2-Clause
3
 *
4
 * Copyright 2016 Michal Meloun <[email protected]>
5
 * Copyright (c) 2020 Oskar Holmlund <[email protected]>
6
 * Copyright (c) 2022 Mitchell Horne <[email protected]>
7
 * Copyright (c) 2024 Jari Sihvola <[email protected]>
8
 */
9

10
/* Clocks for JH7110 SYS group. PLL driver must be attached before this. */
11

12
#include <sys/param.h>
13
#include <sys/systm.h>
14
#include <sys/bus.h>
15
#include <sys/kernel.h>
16
#include <sys/module.h>
17
#include <sys/mutex.h>
18
#include <sys/resource.h>
19
#include <sys/rman.h>
20

21
#include <machine/bus.h>
22

23
#include <dev/fdt/simplebus.h>
24
#include <dev/ofw/ofw_bus.h>
25
#include <dev/ofw/ofw_bus_subr.h>
26

27
#include <dev/clk/clk.h>
28
#include <dev/clk/starfive/jh7110_clk.h>
29
#include <dev/hwreset/hwreset.h>
30

31
#include <dt-bindings/clock/starfive,jh7110-crg.h>
32

33
#include "clkdev_if.h"
34
#include "hwreset_if.h"
35

36
static struct ofw_compat_data compat_data[] = {
37
	{ "starfive,jh7110-syscrg",	1 },
38
	{ NULL,				0 }
39
};
40

41
static struct resource_spec res_spec[] = {
42
	{ SYS_RES_MEMORY, 0, RF_ACTIVE | RF_SHAREABLE },
43
	RESOURCE_SPEC_END
44
};
45

46
/* parents for non-pll SYS clocks */
47
static const char *cpu_root_p[] = { "osc", "pll0_out" };
48
static const char *cpu_core_p[] = { "cpu_root" };
49
static const char *cpu_bus_p[] = { "cpu_core" };
50
static const char *perh_root_p[] = { "pll0_out", "pll2_out" };
51
static const char *bus_root_p[] = { "osc", "pll2_out" };
52

53
static const char *apb_bus_p[] = { "stg_axiahb" };
54
static const char *apb0_p[] = { "apb_bus" };
55
static const char *u0_sys_iomux_apb_p[] = { "apb_bus" };
56
static const char *stg_axiahb_p[] = { "axi_cfg0" };
57
static const char *ahb0_p[] = { "stg_axiahb" };
58
static const char *axi_cfg0_p[] = { "bus_root" };
59
static const char *nocstg_bus_p[] = { "bus_root" };
60
static const char *noc_bus_stg_axi_p[] = { "nocstg_bus" };
61

62
static const char *u0_dw_uart_clk_apb_p[] = { "apb0" };
63
static const char *u0_dw_uart_clk_core_p[] = { "osc" };
64
static const char *u0_dw_sdio_clk_ahb_p[] = { "ahb0" };
65
static const char *u0_dw_sdio_clk_sdcard_p[] = { "axi_cfg0" };
66
static const char *u1_dw_uart_clk_apb_p[] = { "apb0" };
67
static const char *u1_dw_uart_clk_core_p[] = { "osc" };
68
static const char *u1_dw_sdio_clk_ahb_p[] = { "ahb0" };
69
static const char *u1_dw_sdio_clk_sdcard_p[] = { "axi_cfg0" };
70
static const char *usb_125m_p[] = { "pll0_out" };
71
static const char *u2_dw_uart_clk_apb_p[] = { "apb0" };
72
static const char *u2_dw_uart_clk_core_p[] = { "osc" };
73
static const char *u3_dw_uart_clk_apb_p[] = { "apb0" };
74
static const char *u3_dw_uart_clk_core_p[] = { "perh_root" };
75

76
static const char *gmac_src_p[] = { "pll0_out" };
77
static const char *gmac_phy_p[] = { "gmac_src" };
78
static const char *gmac0_gtxclk_p[] = { "pll0_out" };
79
static const char *gmac0_ptp_p[] = { "gmac_src" };
80
static const char *gmac0_gtxc_p[] = { "gmac0_gtxclk" };
81
static const char *gmac1_gtxclk_p[] = { "pll0_out" };
82
static const char *gmac1_gtxc_p[] = { "gmac1_gtxclk" };
83
static const char *gmac1_rmii_rtx_p[] = { "gmac1_rmii_refin" };
84
static const char *gmac1_axi_p[] = { "stg_axiahb" };
85
static const char *gmac1_ahb_p[] = { "ahb0" };
86
static const char *gmac1_ptp_p[] = { "gmac_src" };
87
static const char *gmac1_tx_inv_p[] = { "gmac1_tx" };
88
static const char *gmac1_tx_p[] = { "gmac1_gtxclk", "gmac1_rmii_rtx" };
89
static const char *gmac1_rx_p[] = { "gmac1_rgmii_rxin", "gmac1_rmii_rtx" };
90
static const char *gmac1_rx_inv_p[] = { "gmac1_rx" };
91

92
/* non-pll SYS clocks */
93
static const struct jh7110_clk_def sys_clks[] = {
94
	JH7110_MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", cpu_root_p),
95
	JH7110_DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", cpu_core_p, 7),
96
	JH7110_DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", cpu_bus_p, 2),
97
	JH7110_GATEDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", perh_root_p, 2),
98
	JH7110_MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", bus_root_p),
99

100
	JH7110_GATE(JH7110_SYSCLK_APB0, "apb0", apb0_p),
101
	JH7110_GATE(JH7110_SYSCLK_IOMUX_APB, "u0_sys_iomux_apb",
102
	    u0_sys_iomux_apb_p),
103
	JH7110_GATE(JH7110_SYSCLK_UART0_APB, "u0_dw_uart_clk_apb",
104
	    u0_dw_uart_clk_apb_p),
105
	JH7110_GATE(JH7110_SYSCLK_UART0_CORE, "u0_dw_uart_clk_core",
106
	    u0_dw_uart_clk_core_p),
107
	JH7110_GATE(JH7110_SYSCLK_UART1_APB, "u1_dw_uart_clk_apb",
108
	    u1_dw_uart_clk_apb_p),
109
	JH7110_GATE(JH7110_SYSCLK_UART1_CORE, "u1_dw_uart_clk_core",
110
	    u1_dw_uart_clk_core_p),
111
	JH7110_GATE(JH7110_SYSCLK_UART2_APB, "u2_dw_uart_clk_apb",
112
	    u2_dw_uart_clk_apb_p),
113
	JH7110_GATE(JH7110_SYSCLK_UART2_CORE, "u2_dw_uart_clk_core",
114
	    u2_dw_uart_clk_core_p),
115
	JH7110_GATE(JH7110_SYSCLK_UART3_APB, "u3_dw_uart_clk_apb",
116
	    u3_dw_uart_clk_apb_p),
117
	JH7110_GATE(JH7110_SYSCLK_UART3_CORE, "u3_dw_uart_clk_core",
118
	    u3_dw_uart_clk_core_p),
119

120
	JH7110_DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", axi_cfg0_p, 3),
121
	JH7110_DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", stg_axiahb_p, 2),
122
	JH7110_DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", nocstg_bus_p, 3),
123
	JH7110_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi",
124
	    noc_bus_stg_axi_p),
125
	JH7110_GATE(JH7110_SYSCLK_AHB0, "ahb0", ahb0_p),
126
	JH7110_DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", apb_bus_p, 8),
127

128
	JH7110_GATE(JH7110_SYSCLK_SDIO0_AHB, "u0_dw_sdio_clk_ahb",
129
	    u0_dw_sdio_clk_ahb_p),
130
	JH7110_GATE(JH7110_SYSCLK_SDIO1_AHB, "u1_dw_sdio_clk_ahb",
131
	    u1_dw_sdio_clk_ahb_p),
132
	JH7110_GATEDIV(JH7110_SYSCLK_SDIO0_SDCARD, "u0_dw_sdio_clk_sdcard",
133
	    u0_dw_sdio_clk_sdcard_p, 15),
134
	JH7110_GATEDIV(JH7110_SYSCLK_SDIO1_SDCARD, "u1_dw_sdio_clk_sdcard",
135
	    u1_dw_sdio_clk_sdcard_p, 15),
136
	JH7110_DIV(JH7110_SYSCLK_USB_125M, "usb_125m", usb_125m_p, 15),
137

138
	JH7110_DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", gmac_src_p, 7),
139
	JH7110_GATEDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk",
140
	    gmac0_gtxclk_p, 15),
141
	JH7110_GATEDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp", gmac0_ptp_p, 31),
142
	JH7110_GATEDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy", gmac_phy_p, 31),
143
	JH7110_GATE(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", gmac0_gtxc_p),
144

145
	JH7110_MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", gmac1_rx_p),
146
	JH7110_INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", gmac1_rx_inv_p),
147
	JH7110_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", gmac1_ahb_p),
148
	JH7110_DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk",
149
	    gmac1_gtxclk_p, 15),
150
	JH7110_GATEMUX(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx", gmac1_tx_p),
151
	JH7110_INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv", gmac1_tx_inv_p),
152
	JH7110_GATEDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", gmac1_ptp_p, 31),
153
	JH7110_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", gmac1_axi_p),
154
	JH7110_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", gmac1_gtxc_p),
155
	JH7110_DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx",
156
	    gmac1_rmii_rtx_p, 30),
157
};
158

159
static int
160
jh7110_clk_sys_probe(device_t dev)
161
{
162
	if (!ofw_bus_status_okay(dev))
163
		return (ENXIO);
164

165
	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
166
		return (ENXIO);
167

168
	device_set_desc(dev, "StarFive JH7110 SYS clock generator");
169

170
	return (BUS_PROBE_DEFAULT);
171
}
172

173
static int
174
jh7110_clk_sys_attach(device_t dev)
175
{
176
	struct jh7110_clkgen_softc *sc;
177
	int i, error;
178

179
	sc = device_get_softc(dev);
180

181
	sc->reset_status_offset = SYSCRG_RESET_STATUS;
182
	sc->reset_selector_offset = SYSCRG_RESET_SELECTOR;
183

184
	mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
185

186
	/* Allocate memory groups */
187
	error = bus_alloc_resources(dev, res_spec, &sc->mem_res);
188
	if (error != 0) {
189
		device_printf(dev, "Couldn't allocate resources, error %d\n",
190
		    error);
191
		return (ENXIO);
192
	}
193

194
	/* Create clock domain */
195
	sc->clkdom = clkdom_create(dev);
196
	if (sc->clkdom == NULL) {
197
		device_printf(dev, "Couldn't create clkdom\n");
198
		return (ENXIO);
199
	}
200

201
	/* Register clocks */
202
	for (i = 0; i < nitems(sys_clks); i++) {
203
		error = jh7110_clk_register(sc->clkdom, &sys_clks[i]);
204
		if (error != 0) {
205
			device_printf(dev, "Couldn't register clock %s: %d\n",
206
			    sys_clks[i].clkdef.name, error);
207
			return (ENXIO);
208
		}
209
	}
210

211
	if (clkdom_finit(sc->clkdom) != 0)
212
		panic("Cannot finalize clkdom initialization\n");
213

214
	if (bootverbose)
215
		clkdom_dump(sc->clkdom);
216

217
	hwreset_register_ofw_provider(dev);
218

219
	return (0);
220
}
221

222
static int
223
jh7110_clk_sys_detach(device_t dev)
224
{
225
	/* Detach not supported */
226
	return (EBUSY);
227
}
228

229
static void
230
jh7110_clk_sys_device_lock(device_t dev)
231
{
232
	struct jh7110_clkgen_softc *sc;
233

234
	sc = device_get_softc(dev);
235
	mtx_lock(&sc->mtx);
236
}
237

238
static void
239
jh7110_clk_sys_device_unlock(device_t dev)
240
{
241
	struct jh7110_clkgen_softc *sc;
242

243
	sc = device_get_softc(dev);
244
	mtx_unlock(&sc->mtx);
245
}
246

247
static device_method_t jh7110_clk_sys_methods[] = {
248
	/* Device interface */
249
	DEVMETHOD(device_probe,		jh7110_clk_sys_probe),
250
	DEVMETHOD(device_attach,	jh7110_clk_sys_attach),
251
	DEVMETHOD(device_detach,	jh7110_clk_sys_detach),
252

253
	/* clkdev interface */
254
	DEVMETHOD(clkdev_device_lock,	jh7110_clk_sys_device_lock),
255
	DEVMETHOD(clkdev_device_unlock,	jh7110_clk_sys_device_unlock),
256

257
	/* Reset interface */
258
	DEVMETHOD(hwreset_assert,	jh7110_reset_assert),
259
	DEVMETHOD(hwreset_is_asserted,	jh7110_reset_is_asserted),
260

261
	DEVMETHOD_END
262
};
263

264
DEFINE_CLASS_0(jh7110_clk_sys, jh7110_clk_sys_driver, jh7110_clk_sys_methods,
265
    sizeof(struct jh7110_clkgen_softc));
266
EARLY_DRIVER_MODULE(jh7110_clk_sys, simplebus, jh7110_clk_sys_driver, 0, 0,
267
    BUS_PASS_BUS + BUS_PASS_ORDER_LATE);
268
MODULE_VERSION(jh7110_clk_sys, 1);
269

270
Product

Resources

Company
