Path: blob/main/sys/dev/clk/xilinx/zynqmp_clk_gate.c
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/*-1* SPDX-License-Identifier: BSD-2-Clause2*3* Copyright (c) 2023 Beckhoff Automation GmbH & Co. KG4*5* Redistribution and use in source and binary forms, with or without6* modification, are permitted provided that the following conditions7* are met:8* 1. Redistributions of source code must retain the above copyright9* notice, this list of conditions and the following disclaimer.10* 2. Redistributions in binary form must reproduce the above copyright11* notice, this list of conditions and the following disclaimer in the12* documentation and/or other materials provided with the distribution.13*14* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND15* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE16* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE17* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE18* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL19* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS20* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)21* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT22* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY23* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF24* SUCH DAMAGE.25*/2627#include <sys/cdefs.h>2829#include <sys/param.h>30#include <sys/systm.h>31#include <sys/bus.h>3233#include <dev/clk/clk.h>3435#include <dev/clk/xilinx/zynqmp_clk_gate.h>3637#include "clkdev_if.h"38#include "zynqmp_firmware_if.h"3940struct zynqmp_clk_gate_softc {41device_t firmware;42uint32_t id;43};4445static int46zynqmp_clk_gate_init(struct clknode *clk, device_t dev)47{4849clknode_init_parent_idx(clk, 0);50return (0);51}5253static int54zynqmp_clk_set_gate(struct clknode *clk, bool enable)55{56struct zynqmp_clk_gate_softc *sc;57int rv;5859sc = clknode_get_softc(clk);60if (enable)61rv = ZYNQMP_FIRMWARE_CLOCK_ENABLE(sc->firmware, sc->id);62else63rv = ZYNQMP_FIRMWARE_CLOCK_DISABLE(sc->firmware, sc->id);64if (rv != 0) {65printf("%s: Error %sbling %s\n",66__func__,67enable == true ? "ena" : "disa",68clknode_get_name(clk));69return (EINVAL);70}71return (0);72}7374static clknode_method_t zynqmp_clk_gate_clknode_methods[] = {75/* Device interface */76CLKNODEMETHOD(clknode_init, zynqmp_clk_gate_init),77CLKNODEMETHOD(clknode_set_gate, zynqmp_clk_set_gate),78CLKNODEMETHOD_END79};8081DEFINE_CLASS_1(zynqmp_clk_gate_clknode, zynqmp_clk_gate_clknode_class,82zynqmp_clk_gate_clknode_methods, sizeof(struct zynqmp_clk_gate_softc), clknode_class);8384int85zynqmp_clk_gate_register(struct clkdom *clkdom, device_t fw, struct clknode_init_def *clkdef)86{87struct clknode *clk;88struct zynqmp_clk_gate_softc *sc;89uint32_t fw_clk_id;9091fw_clk_id = clkdef->id - 1;92clkdef->id = 0;93clk = clknode_create(clkdom, &zynqmp_clk_gate_clknode_class, clkdef);94if (clk == NULL)95return (1);96sc = clknode_get_softc(clk);97sc->id = fw_clk_id;98sc->firmware = fw;99clknode_register(clkdom, clk);100return (0);101}102103104