/*-1* Copyright (c) 1998 - 2008 Søren Schmidt <[email protected]>2* Copyright (c) 2009-2012 Alexander Motin <[email protected]>3* Copyright (c) 2015-2016 Justin Hibbits <[email protected]>4* All rights reserved.5*6* Redistribution and use in source and binary forms, with or without7* modification, are permitted provided that the following conditions8* are met:9* 1. Redistributions of source code must retain the above copyright10* notice, this list of conditions and the following disclaimer,11* without modification, immediately at the beginning of the file.12* 2. Redistributions in binary form must reproduce the above copyright13* notice, this list of conditions and the following disclaimer in the14* documentation and/or other materials provided with the distribution.15*16* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR17* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES18* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.19* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,20* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT21* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,22* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY23* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT24* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF25* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.26*/2728/* ATA register defines */2930#define ATA_FEATURE 1 /* (W) feature */31#define ATA_F_DMA 0x01 /* enable DMA */32#define ATA_F_OVL 0x02 /* enable overlap */3334#define ATA_COUNT 2 /* (W) sector count */3536#define ATA_SECTOR 3 /* (RW) sector # */37#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */38#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */39#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */40#define ATA_D_LBA 0x40 /* use LBA addressing */41#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */4243#define ATA_COMMAND 7 /* (W) command */4445#define ATA_ERROR 8 /* (R) error */46#define ATA_E_ILI 0x01 /* illegal length */47#define ATA_E_NM 0x02 /* no media */48#define ATA_E_ABORT 0x04 /* command aborted */49#define ATA_E_MCR 0x08 /* media change request */50#define ATA_E_IDNF 0x10 /* ID not found */51#define ATA_E_MC 0x20 /* media changed */52#define ATA_E_UNC 0x40 /* uncorrectable data */53#define ATA_E_ICRC 0x80 /* UDMA crc error */54#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */5556#define ATA_IREASON 9 /* (R) interrupt reason */57#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */58#define ATA_I_IN 0x02 /* read (1) | write (0) */59#define ATA_I_RELEASE 0x04 /* released bus (1) */60#define ATA_I_TAGMASK 0xf8 /* tag mask */6162#define ATA_STATUS 10 /* (R) status */63#define ATA_ALTSTAT 11 /* (R) alternate status */64#define ATA_S_ERROR 0x01 /* error */65#define ATA_S_INDEX 0x02 /* index */66#define ATA_S_CORR 0x04 /* data corrected */67#define ATA_S_DRQ 0x08 /* data request */68#define ATA_S_DSC 0x10 /* drive seek completed */69#define ATA_S_SERVICE 0x10 /* drive needs service */70#define ATA_S_DWF 0x20 /* drive write fault */71#define ATA_S_DMA 0x20 /* DMA ready */72#define ATA_S_READY 0x40 /* drive ready */73#define ATA_S_BUSY 0x80 /* busy */7475#define ATA_CONTROL 12 /* (W) control */76#define ATA_A_IDS 0x02 /* disable interrupts */77#define ATA_A_RESET 0x04 /* RESET controller */78#define ATA_A_4BIT 0x08 /* 4 head bits */79#define ATA_A_HOB 0x80 /* High Order Byte enable */8081/* SATA register defines */82#define ATA_SSTATUS 1383#define ATA_SS_DET_MASK 0x0000000f84#define ATA_SS_DET_NO_DEVICE 0x0000000085#define ATA_SS_DET_DEV_PRESENT 0x0000000186#define ATA_SS_DET_PHY_ONLINE 0x0000000387#define ATA_SS_DET_PHY_OFFLINE 0x000000048889#define ATA_SS_SPD_MASK 0x000000f090#define ATA_SS_SPD_NO_SPEED 0x0000000091#define ATA_SS_SPD_GEN1 0x0000001092#define ATA_SS_SPD_GEN2 0x0000002093#define ATA_SS_SPD_GEN3 0x000000309495#define ATA_SS_IPM_MASK 0x00000f0096#define ATA_SS_IPM_NO_DEVICE 0x0000000097#define ATA_SS_IPM_ACTIVE 0x0000010098#define ATA_SS_IPM_PARTIAL 0x0000020099#define ATA_SS_IPM_SLUMBER 0x00000600100#define ATA_SS_IPM_DEVSLEEP 0x00000800101102#define ATA_SERROR 14103#define ATA_SE_DATA_CORRECTED 0x00000001104#define ATA_SE_COMM_CORRECTED 0x00000002105#define ATA_SE_DATA_ERR 0x00000100106#define ATA_SE_COMM_ERR 0x00000200107#define ATA_SE_PROT_ERR 0x00000400108#define ATA_SE_HOST_ERR 0x00000800109#define ATA_SE_PHY_CHANGED 0x00010000110#define ATA_SE_PHY_IERROR 0x00020000111#define ATA_SE_COMM_WAKE 0x00040000112#define ATA_SE_DECODE_ERR 0x00080000113#define ATA_SE_PARITY_ERR 0x00100000114#define ATA_SE_CRC_ERR 0x00200000115#define ATA_SE_HANDSHAKE_ERR 0x00400000116#define ATA_SE_LINKSEQ_ERR 0x00800000117#define ATA_SE_TRANSPORT_ERR 0x01000000118#define ATA_SE_UNKNOWN_FIS 0x02000000119#define ATA_SE_EXCHANGED 0x04000000120121#define ATA_SCONTROL 15122#define ATA_SC_DET_MASK 0x0000000f123#define ATA_SC_DET_IDLE 0x00000000124#define ATA_SC_DET_RESET 0x00000001125#define ATA_SC_DET_DISABLE 0x00000004126127#define ATA_SC_SPD_MASK 0x000000f0128#define ATA_SC_SPD_NO_SPEED 0x00000000129#define ATA_SC_SPD_SPEED_GEN1 0x00000010130#define ATA_SC_SPD_SPEED_GEN2 0x00000020131#define ATA_SC_SPD_SPEED_GEN3 0x00000030132133#define ATA_SC_IPM_MASK 0x00000f00134#define ATA_SC_IPM_NONE 0x00000000135#define ATA_SC_IPM_DIS_PARTIAL 0x00000100136#define ATA_SC_IPM_DIS_SLUMBER 0x00000200137#define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400138139140