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freebsd
GitHub Repository: freebsd/freebsd-src
 Path: blob/main/sys/powerpc/ps3/if_glcreg.h
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/*-

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 * SPDX-License-Identifier: BSD-2-Clause

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 *

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 * Copyright (C) 2010 Nathan Whitehorn

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 * All rights reserved.

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 *

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 * Redistribution and use in source and binary forms, with or without

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 * modification, are permitted provided that the following conditions

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 * are met:

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 * 1. Redistributions of source code must retain the above copyright

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 *    notice, this list of conditions and the following disclaimer.

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 * 2. Redistributions in binary form must reproduce the above copyright

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 *    notice, this list of conditions and the following disclaimer in the

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 *    documentation and/or other materials provided with the distribution.

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 *

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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR

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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.

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 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

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 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,

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 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;

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 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,

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 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR

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 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

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 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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 */

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#ifndef _POWERPC_PS3_IF_GLCREG_H

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#define _POWERPC_PS3_IF_GLCREG_H

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#define GLC_MAX_TX_PACKETS	128

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#define GLC_MAX_RX_PACKETS	128

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struct glc_dmadesc;

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/*

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 * software state for transmit job mbufs (may be elements of mbuf chains)

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 */

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struct glc_txsoft {

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	struct mbuf *txs_mbuf;		/* head of our mbuf chain */

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	bus_dmamap_t txs_dmamap;	/* our DMA map */

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	int txs_firstdesc;		/* first descriptor in packet */

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	int txs_lastdesc;		/* last descriptor in packet */

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	int txs_ndescs;			/* number of descriptors */

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	STAILQ_ENTRY(glc_txsoft) txs_q;

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};

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STAILQ_HEAD(glc_txsq, glc_txsoft);

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/*

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 * software state for receive jobs

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 */

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struct glc_rxsoft {

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	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */

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	bus_dmamap_t rxs_dmamap;	/* our DMA map */

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	int rxs_desc_slot;		/* DMA descriptor for this packet */

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	bus_addr_t rxs_desc;

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	bus_dma_segment_t segment;

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};

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struct glc_softc {

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	if_t		sc_ifp;

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	device_t	sc_self;

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	struct mtx	sc_mtx;

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	u_char		sc_enaddr[ETHER_ADDR_LEN];

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	int		sc_tx_vlan, sc_rx_vlan;

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	int		sc_ifpflags;

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	uint64_t	sc_dma_base[5];

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	bus_dma_tag_t	sc_dmadesc_tag;

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	int		sc_irqid;

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	struct resource	*sc_irq;

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	void		*sc_irqctx;

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	uint64_t	*sc_hwirq_status;

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	volatile uint64_t sc_interrupt_status;

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	struct ifmedia	sc_media;

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	/* Transmission */

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	bus_dma_tag_t	sc_txdma_tag;

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	struct glc_txsoft sc_txsoft[GLC_MAX_TX_PACKETS];

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	struct glc_dmadesc *sc_txdmadesc;

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	int		next_txdma_slot, first_used_txdma_slot, bsy_txdma_slots;

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	bus_dmamap_t	sc_txdmadesc_map;

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	bus_addr_t	sc_txdmadesc_phys;

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	struct glc_txsq	sc_txfreeq;

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	struct glc_txsq	sc_txdirtyq;

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	/* Reception */

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	bus_dma_tag_t	sc_rxdma_tag;

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	struct glc_rxsoft sc_rxsoft[GLC_MAX_RX_PACKETS];

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	struct glc_dmadesc *sc_rxdmadesc;

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	int		sc_next_rxdma_slot;

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	bus_dmamap_t	sc_rxdmadesc_map;

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	bus_addr_t	sc_rxdmadesc_phys;

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	int		sc_bus, sc_dev;

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	int		sc_wdog_timer;

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	struct callout	sc_tick_ch;

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};

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#define GELIC_GET_MAC_ADDRESS   0x0001

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#define GELIC_GET_LINK_STATUS   0x0002

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#define GELIC_SET_LINK_MODE     0x0003

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#define  GELIC_LINK_UP          0x0001

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#define  GELIC_FULL_DUPLEX      0x0002

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#define  GELIC_AUTO_NEG         0x0004

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#define  GELIC_SPEED_10         0x0010

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#define  GELIC_SPEED_100        0x0020

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#define  GELIC_SPEED_1000       0x0040

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#define GELIC_GET_VLAN_ID       0x0004

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#define  GELIC_VLAN_TX_ETHERNET	0x0002

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#define  GELIC_VLAN_RX_ETHERNET	0x0012

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#define  GELIC_VLAN_TX_WIRELESS	0x0003

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#define  GELIC_VLAN_RX_WIRELESS	0x0013

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/* Command status code */

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#define	GELIC_DESCR_OWNED	0xa0000000

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#define	GELIC_CMDSTAT_DMA_DONE	0x00000000

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#define	GELIC_CMDSTAT_CHAIN_END	0x00000002

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#define GELIC_CMDSTAT_CSUM_TCP	0x00020000

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#define GELIC_CMDSTAT_CSUM_UDP	0x00030000

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#define GELIC_CMDSTAT_NOIPSEC	0x00080000

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#define GELIC_CMDSTAT_LAST	0x00040000

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#define GELIC_RXERRORS		0x7def8000

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/* RX Data Status codes */

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#define GELIC_RX_IPCSUM		0x20000000

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#define GELIC_RX_TCPUDPCSUM	0x10000000

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/* Interrupt options */

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#define GELIC_INT_RXDONE	0x0000000000004000UL

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#define GELIC_INT_RXFRAME	0x1000000000000000UL

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#define GELIC_INT_TXDONE	0x0080000000000000UL

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#define GELIC_INT_TX_CHAIN_END	0x0100000000000000UL

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#define GELIC_INT_PHY		0x0000000020000000UL

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/* Hardware DMA descriptor. Must be 32-byte aligned */

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struct glc_dmadesc {

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	uint32_t paddr;	/* Must be 128 byte aligned for receive */

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	uint32_t len;

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	uint32_t next;

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	uint32_t cmd_stat;

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	uint32_t result_size;

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	uint32_t valid_size;

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	uint32_t data_stat;

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	uint32_t rxerror;

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};

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#endif /* _POWERPC_PS3_IF_GLCREG_H */

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