/*-1* Copyright (c) 2015-2016 Ruslan Bukin <[email protected]>2* All rights reserved.3*4* Portions of this software were developed by SRI International and the5* University of Cambridge Computer Laboratory under DARPA/AFRL contract6* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.7*8* Portions of this software were developed by the University of Cambridge9* Computer Laboratory as part of the CTSRD Project, with support from the10* UK Higher Education Innovation Fund (HEIF).11*12* Redistribution and use in source and binary forms, with or without13* modification, are permitted provided that the following conditions14* are met:15* 1. Redistributions of source code must retain the above copyright16* notice, this list of conditions and the following disclaimer.17* 2. Redistributions in binary form must reproduce the above copyright18* notice, this list of conditions and the following disclaimer in the19* documentation and/or other materials provided with the distribution.20*21* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND22* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE23* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE24* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE25* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL26* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS27* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)28* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT29* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY30* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF31* SUCH DAMAGE.32*/3334#ifndef _MACHINE_CPUFUNC_H_35#define _MACHINE_CPUFUNC_H_3637static __inline void38breakpoint(void)39{4041__asm("ebreak");42}4344#ifdef _KERNEL4546#include <sys/_null.h>4748#include <machine/riscvreg.h>4950static __inline register_t51intr_disable(void)52{53uint64_t ret;5455__asm __volatile(56"csrrci %0, sstatus, %1"57: "=&r" (ret) : "i" (SSTATUS_SIE)58);5960return (ret & (SSTATUS_SIE));61}6263static __inline void64intr_restore(register_t s)65{6667__asm __volatile(68"csrs sstatus, %0"69:: "r" (s)70);71}7273static __inline void74intr_enable(void)75{7677__asm __volatile(78"csrsi sstatus, %0"79:: "i" (SSTATUS_SIE)80);81}8283/* NB: fence() is defined as a macro in <machine/atomic.h>. */8485static __inline void86fence_i(void)87{8889__asm __volatile("fence.i" ::: "memory");90}9192static __inline void93sfence_vma(void)94{9596__asm __volatile("sfence.vma" ::: "memory");97}9899static __inline void100sfence_vma_page(uintptr_t addr)101{102103__asm __volatile("sfence.vma %0" :: "r" (addr) : "memory");104}105106static __inline void107sfence_vma_asid(uint64_t asid)108{109110__asm __volatile("sfence.vma x0, %0" :: "r" (asid) : "memory");111}112113static __inline void114sfence_vma_asid_page(uint64_t asid, uintptr_t addr)115{116117__asm __volatile("sfence.vma %0, %1" :: "r" (addr), "r" (asid)118: "memory");119}120121#define rdcycle() csr_read64(cycle)122#define rdtime() csr_read64(time)123#define rdinstret() csr_read64(instret)124#define rdhpmcounter(n) csr_read64(hpmcounter##n)125126/* Cache hooks. */127128extern int64_t dcache_line_size;129130typedef void (*cache_op_t)(vm_offset_t start, vm_size_t size);131132struct riscv_cache_ops {133cache_op_t dcache_wbinv_range;134cache_op_t dcache_inv_range;135cache_op_t dcache_wb_range;136};137138extern struct riscv_cache_ops cache_ops;139140static __inline void141cpu_dcache_wbinv_range(vm_offset_t addr, vm_size_t size)142{143if (cache_ops.dcache_wbinv_range != NULL)144cache_ops.dcache_wbinv_range(addr, size);145}146147static __inline void148cpu_dcache_inv_range(vm_offset_t addr, vm_size_t size)149{150if (cache_ops.dcache_inv_range != NULL)151cache_ops.dcache_inv_range(addr, size);152}153154static __inline void155cpu_dcache_wb_range(vm_offset_t addr, vm_size_t size)156{157if (cache_ops.dcache_wb_range != NULL)158cache_ops.dcache_wb_range(addr, size);159}160161void riscv_cache_install_hooks(struct riscv_cache_ops *, u_int);162163#define cpufunc_nullop() riscv_nullop()164165void riscv_nullop(void);166167#endif /* _KERNEL */168#endif /* _MACHINE_CPUFUNC_H_ */169170171