/*-1* Copyright (c) 2015-2016 Ruslan Bukin <[email protected]>2* All rights reserved.3*4* Portions of this software were developed by SRI International and the5* University of Cambridge Computer Laboratory under DARPA/AFRL contract6* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.7*8* Portions of this software were developed by the University of Cambridge9* Computer Laboratory as part of the CTSRD Project, with support from the10* UK Higher Education Innovation Fund (HEIF).11*12* Redistribution and use in source and binary forms, with or without13* modification, are permitted provided that the following conditions14* are met:15* 1. Redistributions of source code must retain the above copyright16* notice, this list of conditions and the following disclaimer.17* 2. Redistributions in binary form must reproduce the above copyright18* notice, this list of conditions and the following disclaimer in the19* documentation and/or other materials provided with the distribution.20*21* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND22* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE23* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE24* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE25* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL26* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS27* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)28* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT29* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY30* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF31* SUCH DAMAGE.32*/3334#ifndef _MACHINE_DB_MACHDEP_H_35#define _MACHINE_DB_MACHDEP_H_3637#include <machine/riscvreg.h>38#include <machine/frame.h>39#include <machine/trap.h>4041#define T_BREAKPOINT (SCAUSE_BREAKPOINT)42#define T_WATCHPOINT (0)4344typedef vm_offset_t db_addr_t;45typedef long db_expr_t;4647#define PC_REGS() ((db_addr_t)kdb_frame->tf_sepc)4849#define BKPT_INST (0x00100073)50#define BKPT_SIZE (INSN_SIZE)51#define BKPT_SET(inst) (BKPT_INST)5253#define BKPT_SKIP do { \54uint32_t _instr; \55\56_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE); \57if ((_instr & 0x3) == 0x3) \58kdb_frame->tf_sepc += 4; /* ebreak */ \59else \60kdb_frame->tf_sepc += 2; /* c.ebreak */ \61} while (0)6263#define db_clear_single_step kdb_cpu_clear_singlestep64#define db_set_single_step kdb_cpu_set_singlestep6566#define IS_BREAKPOINT_TRAP(type, code) (type == T_BREAKPOINT)67#define IS_WATCHPOINT_TRAP(type, code) (type == T_WATCHPOINT)6869#define inst_trap_return(ins) (ins == 0x10000073) /* eret */70#define inst_return(ins) (ins == 0x00008067) /* ret */71#define inst_call(ins) (((ins) & 0x7f) == 111 || \72((ins) & 0x7f) == 103) /* jal, jalr */7374#define inst_load(ins) ({ \75uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE); \76is_load_instr(tmp_instr); \77})7879#define inst_store(ins) ({ \80uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE); \81is_store_instr(tmp_instr); \82})8384#define is_load_instr(ins) (((ins) & 0x7f) == 3)85#define is_store_instr(ins) (((ins) & 0x7f) == 35)8687#define next_instr_address(pc, bd) ((bd) ? (pc) : ((pc) + 4))8889#define DB_ELFSIZE 649091#endif /* !_MACHINE_DB_MACHDEP_H_ */929394