/*-1* SPDX-License-Identifier: BSD-2-Clause2*3* Copyright (c) 2018 Chelsio Communications, Inc.4* All rights reserved.5*6* Redistribution and use in source and binary forms, with or without7* modification, are permitted provided that the following conditions8* are met:9* 1. Redistributions of source code must retain the above copyright10* notice, this list of conditions and the following disclaimer.11* 2. Redistributions in binary form must reproduce the above copyright12* notice, this list of conditions and the following disclaimer in the13* documentation and/or other materials provided with the distribution.14*15* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND16* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE17* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE18* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE19* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL20* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS21* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)22* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT23* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY24* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF25* SUCH DAMAGE.26*/2728#include <sys/cdefs.h>29/* Auto-generated file. Avoid direct editing. */30/* Edits will be lost when file regenerated. */31#include <stdio.h>32#include "tcb_common.h"33_TCBVAR g_tcb_info4[]={34{"ulp_type" , 0, 0, 3, /* name,aux,lo,hi */35NULL , 0, 0, /* faka,flo,fhi */36"ulp_type" , /* aka */37COMP_NONE , /* comp */38"ULP mode: 0 =toe, 2=iscsi, 4=rdma, 5=ddp, remaining values are reserved", /*desc*/39NULL, /*akadesc */40},41{"ulp_raw" , 0, 4, 11, /* name,aux,lo,hi */42NULL , 0, 0, /* faka,flo,fhi */43"ulp" , /* aka */44COMP_ULP , /* comp */45"ULP subtype", /*desc*/46NULL, /*akadesc */47},48{"l2t_ix" , 0, 12, 23, /* name,aux,lo,hi */49NULL , 0, 0, /* faka,flo,fhi */50"l2t_ix" , /* aka */51COMP_NONE , /* comp */52"Destination MAC address index", /*desc*/53NULL, /*akadesc */54},55{"smac_sel" , 0, 24, 31, /* name,aux,lo,hi */56NULL , 0, 0, /* faka,flo,fhi */57"smac_sel" , /* aka */58COMP_NONE , /* comp */59"Source MAC address index", /*desc*/60NULL, /*akadesc */61},62{"TF_MIGRATING" , 0, 32, 32, /* name,aux,lo,hi */63"t_flags" , 0, 0, /* faka,flo,fhi */64"migrating" , /* aka */65COMP_NONE , /* comp */66NULL, /*desc*/67NULL, /*akadesc */68},69{"TF_NON_OFFLOAD" , 0, 33, 33, /* name,aux,lo,hi */70"t_flags" , 1, 1, /* faka,flo,fhi */71"non_offload" , /* aka */72COMP_NONE , /* comp */73NULL, /*desc*/74NULL, /*akadesc */75},76{"TF_LOCK_TID" , 0, 34, 34, /* name,aux,lo,hi */77"t_flags" , 2, 2, /* faka,flo,fhi */78"lock_tid" , /* aka */79COMP_NONE , /* comp */80NULL, /*desc*/81NULL, /*akadesc */82},83{"TF_KEEPALIVE" , 0, 35, 35, /* name,aux,lo,hi */84"t_flags" , 3, 3, /* faka,flo,fhi */85"keepalive" , /* aka */86COMP_NONE , /* comp */87NULL, /*desc*/88NULL, /*akadesc */89},90{"TF_DACK" , 0, 36, 36, /* name,aux,lo,hi */91"t_flags" , 4, 4, /* faka,flo,fhi */92"dack" , /* aka */93COMP_NONE , /* comp */94NULL, /*desc*/95NULL, /*akadesc */96},97{"TF_DACK_MSS" , 0, 37, 37, /* name,aux,lo,hi */98"t_flags" , 5, 5, /* faka,flo,fhi */99"dack_mss" , /* aka */100COMP_NONE , /* comp */101NULL, /*desc*/102NULL, /*akadesc */103},104{"TF_DACK_NOT_ACKED" , 0, 38, 38, /* name,aux,lo,hi */105"t_flags" , 6, 6, /* faka,flo,fhi */106"dack_not_acked" , /* aka */107COMP_NONE , /* comp */108NULL, /*desc*/109NULL, /*akadesc */110},111{"TF_NAGLE" , 0, 39, 39, /* name,aux,lo,hi */112"t_flags" , 7, 7, /* faka,flo,fhi */113"nagle" , /* aka */114COMP_NONE , /* comp */115NULL, /*desc*/116NULL, /*akadesc */117},118{"TF_SSWS_DISABLED" , 0, 40, 40, /* name,aux,lo,hi */119"t_flags" , 8, 8, /* faka,flo,fhi */120"ssws_disabled" , /* aka */121COMP_NONE , /* comp */122NULL, /*desc*/123NULL, /*akadesc */124},125{"TF_RX_FLOW_CONTROL_DDP" , 0, 41, 41, /* name,aux,lo,hi */126"t_flags" , 9, 9, /* faka,flo,fhi */127"rx_flow_control_ddp" , /* aka */128COMP_NONE , /* comp */129NULL, /*desc*/130NULL, /*akadesc */131},132{"TF_RX_FLOW_CONTROL_DISABLE" , 0, 42, 42, /* name,aux,lo,hi */133"t_flags" , 10, 10, /* faka,flo,fhi */134"rx_flow_control_disable" , /* aka */135COMP_NONE , /* comp */136NULL, /*desc*/137NULL, /*akadesc */138},139{"TF_RX_CHANNEL" , 0, 43, 43, /* name,aux,lo,hi */140"t_flags" , 11, 11, /* faka,flo,fhi */141"rx_channel" , /* aka */142COMP_NONE , /* comp */143NULL, /*desc*/144NULL, /*akadesc */145},146{"TF_TX_CHANNEL" , 0, 44, 45, /* name,aux,lo,hi */147"t_flags" , 12, 13, /* faka,flo,fhi */148"tx_channel" , /* aka */149COMP_NONE , /* comp */150NULL, /*desc*/151NULL, /*akadesc */152},153{"TF_TX_QUIESCE" , 0, 46, 46, /* name,aux,lo,hi */154"t_flags" , 14, 14, /* faka,flo,fhi */155"tx_quiesce" , /* aka */156COMP_NONE , /* comp */157NULL, /*desc*/158NULL, /*akadesc */159},160{"TF_RX_QUIESCE" , 0, 47, 47, /* name,aux,lo,hi */161"t_flags" , 15, 15, /* faka,flo,fhi */162"rx_quiesce" , /* aka */163COMP_NONE , /* comp */164NULL, /*desc*/165NULL, /*akadesc */166},167{"TF_TX_PACE_AUTO" , 0, 48, 48, /* name,aux,lo,hi */168"t_flags" , 16, 16, /* faka,flo,fhi */169"tx_pace_auto" , /* aka */170COMP_NONE , /* comp */171NULL, /*desc*/172NULL, /*akadesc */173},174{"TF_TX_PACE_FIXED" , 0, 49, 49, /* name,aux,lo,hi */175"t_flags" , 17, 17, /* faka,flo,fhi */176"tx_pace_fixed" , /* aka */177COMP_NONE , /* comp */178NULL, /*desc*/179NULL, /*akadesc */180},181{"TF_TX_QUEUE" , 0, 50, 52, /* name,aux,lo,hi */182"t_flags" , 18, 20, /* faka,flo,fhi */183"tx_queue" , /* aka */184COMP_NONE , /* comp */185NULL, /*desc*/186NULL, /*akadesc */187},188{"TF_TURBO" , 0, 53, 53, /* name,aux,lo,hi */189"t_flags" , 21, 21, /* faka,flo,fhi */190"turbo" , /* aka */191COMP_NONE , /* comp */192NULL, /*desc*/193NULL, /*akadesc */194},195{"TF_CCTRL_SEL0" , 0, 54, 54, /* name,aux,lo,hi */196"t_flags" , 22, 22, /* faka,flo,fhi */197"cctrl_sel0" , /* aka */198COMP_NONE , /* comp */199NULL, /*desc*/200NULL, /*akadesc */201},202{"TF_CCTRL_SEL1" , 0, 55, 55, /* name,aux,lo,hi */203"t_flags" , 23, 23, /* faka,flo,fhi */204"cctrl_sel1" , /* aka */205COMP_NONE , /* comp */206NULL, /*desc*/207NULL, /*akadesc */208},209{"TF_CORE_FIN" , 0, 56, 56, /* name,aux,lo,hi */210"t_flags" , 24, 24, /* faka,flo,fhi */211"core_fin" , /* aka */212COMP_NONE , /* comp */213NULL, /*desc*/214NULL, /*akadesc */215},216{"TF_CORE_URG" , 0, 57, 57, /* name,aux,lo,hi */217"t_flags" , 25, 25, /* faka,flo,fhi */218"core_urg" , /* aka */219COMP_NONE , /* comp */220NULL, /*desc*/221NULL, /*akadesc */222},223{"TF_CORE_MORE" , 0, 58, 58, /* name,aux,lo,hi */224"t_flags" , 26, 26, /* faka,flo,fhi */225"core_more" , /* aka */226COMP_NONE , /* comp */227NULL, /*desc*/228NULL, /*akadesc */229},230{"TF_CORE_PUSH" , 0, 59, 59, /* name,aux,lo,hi */231"t_flags" , 27, 27, /* faka,flo,fhi */232"core_push" , /* aka */233COMP_NONE , /* comp */234NULL, /*desc*/235NULL, /*akadesc */236},237{"TF_CORE_FLUSH" , 0, 60, 60, /* name,aux,lo,hi */238"t_flags" , 28, 28, /* faka,flo,fhi */239"core_flush" , /* aka */240COMP_NONE , /* comp */241NULL, /*desc*/242NULL, /*akadesc */243},244{"TF_RCV_COALESCE_ENABLE" , 0, 61, 61, /* name,aux,lo,hi */245"t_flags" , 29, 29, /* faka,flo,fhi */246"rcv_coalesce_enable" , /* aka */247COMP_NONE , /* comp */248NULL, /*desc*/249NULL, /*akadesc */250},251{"TF_RCV_COALESCE_PUSH" , 0, 62, 62, /* name,aux,lo,hi */252"t_flags" , 30, 30, /* faka,flo,fhi */253"rcv_coalesce_push" , /* aka */254COMP_NONE , /* comp */255NULL, /*desc*/256NULL, /*akadesc */257},258{"TF_RCV_COALESCE_LAST_PSH" , 0, 63, 63, /* name,aux,lo,hi */259"t_flags" , 31, 31, /* faka,flo,fhi */260"rcv_coalesce_last_psh" , /* aka */261COMP_NONE , /* comp */262NULL, /*desc*/263NULL, /*akadesc */264},265{"TF_RCV_COALESCE_HEARTBEAT" , 0, 64, 64, /* name,aux,lo,hi */266"t_flags" , 32, 32, /* faka,flo,fhi */267"rcv_coalesce_heartbeat" , /* aka */268COMP_NONE , /* comp */269NULL, /*desc*/270NULL, /*akadesc */271},272{"TF_INIT" , 0, 65, 65, /* name,aux,lo,hi */273"t_flags" , 33, 33, /* faka,flo,fhi */274"init" , /* aka */275COMP_NONE , /* comp */276NULL, /*desc*/277NULL, /*akadesc */278},279{"TF_ACTIVE_OPEN" , 0, 66, 66, /* name,aux,lo,hi */280"t_flags" , 34, 34, /* faka,flo,fhi */281"active_open" , /* aka */282COMP_NONE , /* comp */283NULL, /*desc*/284NULL, /*akadesc */285},286{"TF_ASK_MODE" , 0, 67, 67, /* name,aux,lo,hi */287"t_flags" , 35, 35, /* faka,flo,fhi */288"ask_mode" , /* aka */289COMP_NONE , /* comp */290NULL, /*desc*/291NULL, /*akadesc */292},293{"TF_MOD_SCHD_REASON0" , 0, 68, 68, /* name,aux,lo,hi */294"t_flags" , 36, 36, /* faka,flo,fhi */295"mod_schd_reason0" , /* aka */296COMP_NONE , /* comp */297NULL, /*desc*/298NULL, /*akadesc */299},300{"TF_MOD_SCHD_REASON1" , 0, 69, 69, /* name,aux,lo,hi */301"t_flags" , 37, 37, /* faka,flo,fhi */302"mod_schd_reason1" , /* aka */303COMP_NONE , /* comp */304NULL, /*desc*/305NULL, /*akadesc */306},307{"TF_MOD_SCHD_REASON2" , 0, 70, 70, /* name,aux,lo,hi */308"t_flags" , 38, 38, /* faka,flo,fhi */309"mod_schd_reason2" , /* aka */310COMP_NONE , /* comp */311NULL, /*desc*/312NULL, /*akadesc */313},314{"TF_MOD_SCHD_TX" , 0, 71, 71, /* name,aux,lo,hi */315"t_flags" , 39, 39, /* faka,flo,fhi */316"mod_schd_tx" , /* aka */317COMP_NONE , /* comp */318NULL, /*desc*/319NULL, /*akadesc */320},321{"TF_MOD_SCHD_RX" , 0, 72, 72, /* name,aux,lo,hi */322"t_flags" , 40, 40, /* faka,flo,fhi */323"mod_schd_rx" , /* aka */324COMP_NONE , /* comp */325NULL, /*desc*/326NULL, /*akadesc */327},328{"TF_TIMER" , 0, 73, 73, /* name,aux,lo,hi */329"t_flags" , 41, 41, /* faka,flo,fhi */330"timer" , /* aka */331COMP_NONE , /* comp */332NULL, /*desc*/333NULL, /*akadesc */334},335{"TF_DACK_TIMER" , 0, 74, 74, /* name,aux,lo,hi */336"t_flags" , 42, 42, /* faka,flo,fhi */337"dack_timer" , /* aka */338COMP_NONE , /* comp */339NULL, /*desc*/340NULL, /*akadesc */341},342{"TF_PEER_FIN" , 0, 75, 75, /* name,aux,lo,hi */343"t_flags" , 43, 43, /* faka,flo,fhi */344"peer_fin" , /* aka */345COMP_NONE , /* comp */346NULL, /*desc*/347NULL, /*akadesc */348},349{"TF_TX_COMPACT" , 0, 76, 76, /* name,aux,lo,hi */350"t_flags" , 44, 44, /* faka,flo,fhi */351"tx_compact" , /* aka */352COMP_NONE , /* comp */353NULL, /*desc*/354NULL, /*akadesc */355},356{"TF_RX_COMPACT" , 0, 77, 77, /* name,aux,lo,hi */357"t_flags" , 45, 45, /* faka,flo,fhi */358"rx_compact" , /* aka */359COMP_NONE , /* comp */360NULL, /*desc*/361NULL, /*akadesc */362},363{"TF_RDMA_ERROR" , 0, 78, 78, /* name,aux,lo,hi */364"t_flags" , 46, 46, /* faka,flo,fhi */365"rdma_error" , /* aka */366COMP_NONE , /* comp */367NULL, /*desc*/368NULL, /*akadesc */369},370{"TF_RDMA_FLM_ERROR" , 0, 79, 79, /* name,aux,lo,hi */371"t_flags" , 47, 47, /* faka,flo,fhi */372"rdma_flm_error" , /* aka */373COMP_NONE , /* comp */374NULL, /*desc*/375NULL, /*akadesc */376},377{"TF_TX_PDU_OUT" , 0, 80, 80, /* name,aux,lo,hi */378"t_flags" , 48, 48, /* faka,flo,fhi */379"tx_pdu_out" , /* aka */380COMP_NONE , /* comp */381NULL, /*desc*/382NULL, /*akadesc */383},384{"TF_RX_PDU_OUT" , 0, 81, 81, /* name,aux,lo,hi */385"t_flags" , 49, 49, /* faka,flo,fhi */386"rx_pdu_out" , /* aka */387COMP_NONE , /* comp */388NULL, /*desc*/389NULL, /*akadesc */390},391{"TF_DUPACK_COUNT_ODD" , 0, 82, 82, /* name,aux,lo,hi */392"t_flags" , 50, 50, /* faka,flo,fhi */393"dupack_count_odd" , /* aka */394COMP_NONE , /* comp */395NULL, /*desc*/396NULL, /*akadesc */397},398{"TF_FAST_RECOVERY" , 0, 83, 83, /* name,aux,lo,hi */399"t_flags" , 51, 51, /* faka,flo,fhi */400"fast_recovery" , /* aka */401COMP_NONE , /* comp */402NULL, /*desc*/403NULL, /*akadesc */404},405{"TF_RECV_SCALE" , 0, 84, 84, /* name,aux,lo,hi */406"t_flags" , 52, 52, /* faka,flo,fhi */407"recv_scale" , /* aka */408COMP_NONE , /* comp */409NULL, /*desc*/410NULL, /*akadesc */411},412{"TF_RECV_TSTMP" , 0, 85, 85, /* name,aux,lo,hi */413"t_flags" , 53, 53, /* faka,flo,fhi */414"recv_tstmp" , /* aka */415COMP_NONE , /* comp */416NULL, /*desc*/417NULL, /*akadesc */418},419{"TF_RECV_SACK" , 0, 86, 86, /* name,aux,lo,hi */420"t_flags" , 54, 54, /* faka,flo,fhi */421"recv_sack" , /* aka */422COMP_NONE , /* comp */423NULL, /*desc*/424NULL, /*akadesc */425},426{"TF_PEND_CTL0" , 0, 87, 87, /* name,aux,lo,hi */427"t_flags" , 55, 55, /* faka,flo,fhi */428"pend_ctl0" , /* aka */429COMP_NONE , /* comp */430NULL, /*desc*/431NULL, /*akadesc */432},433{"TF_PEND_CTL1" , 0, 88, 88, /* name,aux,lo,hi */434"t_flags" , 56, 56, /* faka,flo,fhi */435"pend_ctl1" , /* aka */436COMP_NONE , /* comp */437NULL, /*desc*/438NULL, /*akadesc */439},440{"TF_PEND_CTL2" , 0, 89, 89, /* name,aux,lo,hi */441"t_flags" , 57, 57, /* faka,flo,fhi */442"pend_ctl2" , /* aka */443COMP_NONE , /* comp */444NULL, /*desc*/445NULL, /*akadesc */446},447{"TF_IP_VERSION" , 0, 90, 90, /* name,aux,lo,hi */448"t_flags" , 58, 58, /* faka,flo,fhi */449"ip_version" , /* aka */450COMP_NONE , /* comp */451NULL, /*desc*/452NULL, /*akadesc */453},454{"TF_CCTRL_ECN" , 0, 91, 91, /* name,aux,lo,hi */455"t_flags" , 59, 59, /* faka,flo,fhi */456"cctrl_ecn" , /* aka */457COMP_NONE , /* comp */458NULL, /*desc*/459NULL, /*akadesc */460},461{"TF_CCTRL_ECE" , 0, 92, 92, /* name,aux,lo,hi */462"t_flags" , 60, 60, /* faka,flo,fhi */463"cctrl_ece" , /* aka */464COMP_NONE , /* comp */465NULL, /*desc*/466NULL, /*akadesc */467},468{"TF_CCTRL_CWR" , 0, 93, 93, /* name,aux,lo,hi */469"t_flags" , 61, 61, /* faka,flo,fhi */470"cctrl_cwr" , /* aka */471COMP_NONE , /* comp */472NULL, /*desc*/473NULL, /*akadesc */474},475{"TF_CCTRL_RFR" , 0, 94, 94, /* name,aux,lo,hi */476"t_flags" , 62, 62, /* faka,flo,fhi */477"cctrl_rfr" , /* aka */478COMP_NONE , /* comp */479NULL, /*desc*/480NULL, /*akadesc */481},482{"TF_UNUSED" , 0, 95, 95, /* name,aux,lo,hi */483"t_flags" , 63, 63, /* faka,flo,fhi */484"unused" , /* aka */485COMP_NONE , /* comp */486NULL, /*desc*/487NULL, /*akadesc */488},489{"rss_info" , 0, 96, 105, /* name,aux,lo,hi */490NULL , 0, 0, /* faka,flo,fhi */491"rss_info" , /* aka */492COMP_NONE , /* comp */493"RSS field", /*desc*/494NULL, /*akadesc */495},496{"tos" , 0, 106, 111, /* name,aux,lo,hi */497NULL , 0, 0, /* faka,flo,fhi */498"tos" , /* aka */499COMP_NONE , /* comp */500"TOS field for IP header", /*desc*/501NULL, /*akadesc */502},503{"t_state" , 0, 112, 115, /* name,aux,lo,hi */504NULL , 0, 0, /* faka,flo,fhi */505"t_state" , /* aka */506COMP_NONE , /* comp */507"Connection TCP state (see TCP state table)", /*desc*/508NULL, /*akadesc */509},510{"max_rt" , 0, 116, 119, /* name,aux,lo,hi */511NULL , 0, 0, /* faka,flo,fhi */512"max_rt" , /* aka */513COMP_NONE , /* comp */514"Maximum re-transmissions", /*desc*/515NULL, /*akadesc */516},517{"t_maxseg" , 0, 120, 123, /* name,aux,lo,hi */518NULL , 0, 0, /* faka,flo,fhi */519"t_maxseg" , /* aka */520COMP_NONE , /* comp */521"MTU table index", /*desc*/522NULL, /*akadesc */523},524{"snd_scale" , 0, 124, 127, /* name,aux,lo,hi */525NULL , 0, 0, /* faka,flo,fhi */526"snd_scale" , /* aka */527COMP_NONE , /* comp */528"Scaling for receive window (0-14). Note: this is reverse of common definition.", /*desc*/529NULL, /*akadesc */530},531{"rcv_scale" , 0, 128, 131, /* name,aux,lo,hi */532NULL , 0, 0, /* faka,flo,fhi */533"rcv_scale" , /* aka */534COMP_NONE , /* comp */535"Scaling for send window (0-14). Note: this is reverse of common definition.", /*desc*/536NULL, /*akadesc */537},538{"t_rxtshift" , 0, 132, 135, /* name,aux,lo,hi */539NULL , 0, 0, /* faka,flo,fhi */540"t_rxtshift" , /* aka */541COMP_NONE , /* comp */542"Retransmit exponential backoff", /*desc*/543NULL, /*akadesc */544},545{"t_dupacks" , 0, 136, 139, /* name,aux,lo,hi */546NULL , 0, 0, /* faka,flo,fhi */547"t_dupacks" , /* aka */548COMP_NONE , /* comp */549"Number of duplicate ACKs received", /*desc*/550NULL, /*akadesc */551},552{"timestamp_offset" , 0, 140, 143, /* name,aux,lo,hi */553NULL , 0, 0, /* faka,flo,fhi */554"timestamp_offset" , /* aka */555COMP_NONE , /* comp */556"Timestamp offset from running clock", /*desc*/557NULL, /*akadesc */558},559{"rcv_adv" , 0, 144, 159, /* name,aux,lo,hi */560NULL , 0, 0, /* faka,flo,fhi */561"rcv_adv" , /* aka */562COMP_NONE , /* comp */563"Peer advertised window", /*desc*/564NULL, /*akadesc */565},566{"timestamp" , 0, 160, 191, /* name,aux,lo,hi */567NULL , 0, 0, /* faka,flo,fhi */568"timestamp" , /* aka */569COMP_NONE , /* comp */570"Timer accounting field", /*desc*/571NULL, /*akadesc */572},573{"t_rtt_ts_recent_age" , 0, 192, 223, /* name,aux,lo,hi */574NULL , 0, 0, /* faka,flo,fhi */575"t_rtt_ts_recent_age" , /* aka */576COMP_NONE , /* comp */577"Round-trip time; timestamps: ts_recent_age", /*desc*/578NULL, /*akadesc */579},580{"t_rtseq_recent" , 0, 224, 255, /* name,aux,lo,hi */581NULL , 0, 0, /* faka,flo,fhi */582"t_rtseq_recent" , /* aka */583COMP_NONE , /* comp */584"Sequence number being timed t_rtseq; timestamps t_recent", /*desc*/585NULL, /*akadesc */586},587{"t_srtt" , 0, 256, 271, /* name,aux,lo,hi */588NULL , 0, 0, /* faka,flo,fhi */589"t_srtt" , /* aka */590COMP_NONE , /* comp */591"Smoothed round-trip time", /*desc*/592NULL, /*akadesc */593},594{"t_rttvar" , 0, 272, 287, /* name,aux,lo,hi */595NULL , 0, 0, /* faka,flo,fhi */596"t_rttvar" , /* aka */597COMP_NONE , /* comp */598"Variance in round-trip time", /*desc*/599NULL, /*akadesc */600},601{"tx_max" , 0, 288, 319, /* name,aux,lo,hi */602NULL , 0, 0, /* faka,flo,fhi */603"tx_max" , /* aka */604COMP_NONE , /* comp */605"Highest sequence number in transmit buffer", /*desc*/606NULL, /*akadesc */607},608{"snd_una_raw" , 0, 320, 347, /* name,aux,lo,hi */609NULL , 0, 0, /* faka,flo,fhi */610"snd_una" , /* aka */611COMP_TX_MAX , /* comp */612"Offset of snd_una from tx_max", /*desc*/613"Send unacknowledged", /*akadesc */614},615{"snd_nxt_raw" , 0, 348, 375, /* name,aux,lo,hi */616NULL , 0, 0, /* faka,flo,fhi */617"snd_nxt" , /* aka */618COMP_TX_MAX , /* comp */619"Offset of snd_nxt from tx_max", /*desc*/620"Send next", /*akadesc */621},622{"snd_max_raw" , 0, 376, 403, /* name,aux,lo,hi */623NULL , 0, 0, /* faka,flo,fhi */624"snd_max" , /* aka */625COMP_TX_MAX , /* comp */626"Offset of snd_max from tx_max", /*desc*/627"Highest sequence number sent", /*akadesc */628},629{"snd_rec_raw" , 0, 404, 431, /* name,aux,lo,hi */630NULL , 0, 0, /* faka,flo,fhi */631"snd_rec" , /* aka */632COMP_TX_MAX , /* comp */633"Offset of NewReno fast recovery end sequence from tx_max", /*desc*/634"NewReno fast recovery end sequence number", /*akadesc */635},636{"snd_cwnd" , 0, 432, 459, /* name,aux,lo,hi */637NULL , 0, 0, /* faka,flo,fhi */638"snd_cwnd" , /* aka */639COMP_NONE , /* comp */640"Congestion-control window", /*desc*/641NULL, /*akadesc */642},643{"snd_ssthresh" , 0, 460, 487, /* name,aux,lo,hi */644NULL , 0, 0, /* faka,flo,fhi */645"snd_ssthresh" , /* aka */646COMP_NONE , /* comp */647"Slow Start threshold", /*desc*/648NULL, /*akadesc */649},650{"tx_hdr_ptr_raw" , 0, 488, 504, /* name,aux,lo,hi */651NULL , 0, 0, /* faka,flo,fhi */652"tx_hdr_ptr" , /* aka */653COMP_PTR , /* comp */654"Page pointer for first byte in send buffer", /*desc*/655NULL, /*akadesc */656},657{"tx_last_ptr_raw" , 0, 505, 521, /* name,aux,lo,hi */658NULL , 0, 0, /* faka,flo,fhi */659"tx_last_ptr" , /* aka */660COMP_PTR , /* comp */661"Page pointer for last byte in send buffer", /*desc*/662NULL, /*akadesc */663},664{"rcv_nxt" , 0, 522, 553, /* name,aux,lo,hi */665NULL , 0, 0, /* faka,flo,fhi */666"rcv_nxt" , /* aka */667COMP_NONE , /* comp */668"TCP receive next", /*desc*/669NULL, /*akadesc */670},671{"rcv_wnd" , 0, 554, 581, /* name,aux,lo,hi */672NULL , 0, 0, /* faka,flo,fhi */673"rcv_wnd" , /* aka */674COMP_NONE , /* comp */675"Receive credits (advertised to peer in receive window)", /*desc*/676NULL, /*akadesc */677},678{"rx_hdr_offset" , 0, 582, 609, /* name,aux,lo,hi */679NULL , 0, 0, /* faka,flo,fhi */680"rx_hdr_offset" , /* aka */681COMP_NONE , /* comp */682"Receive in-order buffered data", /*desc*/683NULL, /*akadesc */684},685{"ts_last_ack_sent_raw" , 0, 610, 637, /* name,aux,lo,hi */686NULL , 0, 0, /* faka,flo,fhi */687"ts_last_ack_sent" , /* aka */688COMP_RCV_NXT , /* comp */689"Offset of highest sequence acked from rcv_nxt", /*desc*/690"Highest sequence number acked", /*akadesc */691},692{"rx_frag0_start_idx_raw" , 0, 638, 665, /* name,aux,lo,hi */693NULL , 0, 0, /* faka,flo,fhi */694"rx_frag0_start_idx" , /* aka */695COMP_RCV_NXT , /* comp */696"Offset of receive fragment 0 start sequence from rcv_nxt", /*desc*/697NULL, /*akadesc */698},699{"rx_frag1_start_idx_offset" , 0, 666, 693, /* name,aux,lo,hi */700NULL , 0, 0, /* faka,flo,fhi */701"rx_frag1_start_idx_offset" , /* aka */702COMP_RCV_NXT , /* comp */703"Offset of receive fragment 1 start sequence from rcv_nxt", /*desc*/704NULL, /*akadesc */705},706{"rx_frag0_len" , 0, 694, 721, /* name,aux,lo,hi */707NULL , 0, 0, /* faka,flo,fhi */708"rx_frag0_len" , /* aka */709COMP_NONE , /* comp */710"Receive re-order fragment 0 length", /*desc*/711NULL, /*akadesc */712},713{"rx_frag1_len" , 0, 722, 749, /* name,aux,lo,hi */714NULL , 0, 0, /* faka,flo,fhi */715"rx_frag1_len" , /* aka */716COMP_NONE , /* comp */717"Receive re-order fragment 1 length", /*desc*/718NULL, /*akadesc */719},720{"pdu_len" , 0, 750, 765, /* name,aux,lo,hi */721NULL , 0, 0, /* faka,flo,fhi */722"pdu_len" , /* aka */723COMP_NONE , /* comp */724"Receive recovered PDU length", /*desc*/725NULL, /*akadesc */726},727{"rx_ptr_raw" , 0, 766, 782, /* name,aux,lo,hi */728NULL , 0, 0, /* faka,flo,fhi */729"rx_ptr" , /* aka */730COMP_PTR , /* comp */731"Page pointer for in-order receive buffer", /*desc*/732NULL, /*akadesc */733},734{"rx_frag1_ptr_raw" , 0, 783, 799, /* name,aux,lo,hi */735NULL , 0, 0, /* faka,flo,fhi */736"rx_frag1_ptr" , /* aka */737COMP_PTR , /* comp */738"Page pointer for out-of-order receive buffer", /*desc*/739NULL, /*akadesc */740},741{"main_slush" , 0, 800, 831, /* name,aux,lo,hi */742NULL , 0, 0, /* faka,flo,fhi */743"main_slush" , /* aka */744COMP_NONE , /* comp */745"Reserved", /*desc*/746NULL, /*akadesc */747},748{"aux1_slush0" , 1, 832, 846, /* name,aux,lo,hi */749NULL , 0, 0, /* faka,flo,fhi */750"aux1_slush0" , /* aka */751COMP_NONE , /* comp */752"Reserved", /*desc*/753NULL, /*akadesc */754},755{"rx_frag2_start_idx_offset_raw", 1, 847, 874, /* name,aux,lo,hi */756NULL , 0, 0, /* faka,flo,fhi */757"rx_frag2_start_idx_offset" , /* aka */758COMP_RCV_NXT , /* comp */759"Offset of receive fragment 2 start sequence from rcv_nxt", /*desc*/760NULL, /*akadesc */761},762{"rx_frag2_ptr_raw" , 1, 875, 891, /* name,aux,lo,hi */763NULL , 0, 0, /* faka,flo,fhi */764"rx_frag2_ptr" , /* aka */765COMP_PTR , /* comp */766"Page pointer for out-of-order receive buffer", /*desc*/767NULL, /*akadesc */768},769{"rx_frag2_len_raw" , 1, 892, 919, /* name,aux,lo,hi */770NULL , 0, 0, /* faka,flo,fhi */771"rx_frag2_len" , /* aka */772COMP_LEN , /* comp */773"Receive re-order fragment 2 length", /*desc*/774NULL, /*akadesc */775},776{"rx_frag3_ptr_raw" , 1, 920, 936, /* name,aux,lo,hi */777NULL , 0, 0, /* faka,flo,fhi */778"rx_frag3_ptr" , /* aka */779COMP_PTR , /* comp */780"Page pointer for out-of-order receive buffer", /*desc*/781NULL, /*akadesc */782},783{"rx_frag3_len_raw" , 1, 937, 964, /* name,aux,lo,hi */784NULL , 0, 0, /* faka,flo,fhi */785"rx_frag3_len" , /* aka */786COMP_LEN , /* comp */787"Receive re-order fragment 3 length", /*desc*/788NULL, /*akadesc */789},790{"rx_frag3_start_idx_offset_raw", 1, 965, 992, /* name,aux,lo,hi */791NULL , 0, 0, /* faka,flo,fhi */792"rx_frag3_start_idx_offset" , /* aka */793COMP_RCV_NXT , /* comp */794"Offset of receive fragment 3 start sequence from rcv_nxt", /*desc*/795NULL, /*akadesc */796},797{"pdu_hdr_len" , 1, 993, 1000, /* name,aux,lo,hi */798NULL , 0, 0, /* faka,flo,fhi */799"pdu_hdr_len" , /* aka */800COMP_NONE , /* comp */801"Receive recovered PDU header length", /*desc*/802NULL, /*akadesc */803},804{"aux1_slush1" , 1, 1001, 1023, /* name,aux,lo,hi */805NULL , 0, 0, /* faka,flo,fhi */806"aux1_slush1" , /* aka */807COMP_NONE , /* comp */808"Reserved", /*desc*/809NULL, /*akadesc */810},811812{"irs_ulp" , 2, 832, 840, /* name,aux,lo,hi */813NULL , 0, 0, /* faka,flo,fhi */814"irs_ulp" , /* aka */815COMP_NONE , /* comp */816"IRS modulo marker_interval when enterring iWARP mode", /*desc*/817NULL, /*akadesc */818},819{"iss_ulp" , 2, 841, 849, /* name,aux,lo,hi */820NULL , 0, 0, /* faka,flo,fhi */821"iss_ulp" , /* aka */822COMP_NONE , /* comp */823"ISS modulo marker_interval when entering iWARP mode", /*desc*/824NULL, /*akadesc */825},826{"tx_pdu_len" , 2, 850, 863, /* name,aux,lo,hi */827NULL , 0, 0, /* faka,flo,fhi */828"tx_pdu_len" , /* aka */829COMP_NONE , /* comp */830"Length of Tx FPDU", /*desc*/831NULL, /*akadesc */832},833{"cq_idx_sq" , 2, 864, 879, /* name,aux,lo,hi */834NULL , 0, 0, /* faka,flo,fhi */835"cq_idx_sq" , /* aka */836COMP_NONE , /* comp */837"CQ index of CQ for SQ", /*desc*/838NULL, /*akadesc */839},840{"cq_idx_rq" , 2, 880, 895, /* name,aux,lo,hi */841NULL , 0, 0, /* faka,flo,fhi */842"cq_idx_rq" , /* aka */843COMP_NONE , /* comp */844"CQ index of CQ for RQ", /*desc*/845NULL, /*akadesc */846},847{"qp_id" , 2, 896, 911, /* name,aux,lo,hi */848NULL , 0, 0, /* faka,flo,fhi */849"qp_id" , /* aka */850COMP_NONE , /* comp */851"QP index", /*desc*/852NULL, /*akadesc */853},854{"pd_id" , 2, 912, 927, /* name,aux,lo,hi */855NULL , 0, 0, /* faka,flo,fhi */856"pd_id" , /* aka */857COMP_NONE , /* comp */858"PD index", /*desc*/859NULL, /*akadesc */860},861{"STAG" , 2, 928, 959, /* name,aux,lo,hi */862NULL , 0, 0, /* faka,flo,fhi */863"stag" , /* aka */864COMP_NONE , /* comp */865"PDU response STAG", /*desc*/866NULL, /*akadesc */867},868{"rq_start" , 2, 960, 985, /* name,aux,lo,hi */869NULL , 0, 0, /* faka,flo,fhi */870"rq_start" , /* aka */871COMP_NONE , /* comp */872"DW aligned starting address of RQ", /*desc*/873NULL, /*akadesc */874},875{"rq_MSN" , 2, 986, 998, /* name,aux,lo,hi */876NULL , 0, 0, /* faka,flo,fhi */877"rq_msn" , /* aka */878COMP_NONE , /* comp */879"Current MSN (modulo 8K, further check in ULP_RX)", /*desc*/880NULL, /*akadesc */881},882{"rq_max_offset" , 2, 999, 1002, /* name,aux,lo,hi */883NULL , 0, 0, /* faka,flo,fhi */884"rq_max_offset" , /* aka */885COMP_NONE , /* comp */886"Log size RQ (the size in hardware is rounded up to a power of 2)", /*desc*/887NULL, /*akadesc */888},889{"rq_write_ptr" , 2, 1003, 1015, /* name,aux,lo,hi */890NULL , 0, 0, /* faka,flo,fhi */891"rq_write_ptr" , /* aka */892COMP_NONE , /* comp */893"Host RQ write pointer", /*desc*/894NULL, /*akadesc */895},896{"RDMAP_opcode" , 2, 1016, 1019, /* name,aux,lo,hi */897NULL , 0, 0, /* faka,flo,fhi */898"rdmap_opcode" , /* aka */899COMP_NONE , /* comp */900"Current FPDU command", /*desc*/901NULL, /*akadesc */902},903{"ord_L_bit_vld" , 2, 1020, 1020, /* name,aux,lo,hi */904NULL , 0, 0, /* faka,flo,fhi */905"ord_l_bit_vld" , /* aka */906COMP_NONE , /* comp */907"Current FPDU has L-bit set", /*desc*/908NULL, /*akadesc */909},910{"tx_flush" , 2, 1021, 1021, /* name,aux,lo,hi */911NULL , 0, 0, /* faka,flo,fhi */912"tx_flush" , /* aka */913COMP_NONE , /* comp */914"1 = flush CPL_TX_DATA", /*desc*/915NULL, /*akadesc */916},917{"tx_oos_rxmt" , 2, 1022, 1022, /* name,aux,lo,hi */918NULL , 0, 0, /* faka,flo,fhi */919"tx_oos_rxmt" , /* aka */920COMP_NONE , /* comp */921"Retransmit is out of FPDU sync", /*desc*/922NULL, /*akadesc */923},924{"tx_oos_txmt" , 2, 1023, 1023, /* name,aux,lo,hi */925NULL , 0, 0, /* faka,flo,fhi */926"tx_oos_txmt" , /* aka */927COMP_NONE , /* comp */928"Transmit is out of FPDU sync, or disable aligned transmission", /*desc*/929NULL, /*akadesc */930},931932{"rx_ddp_buf0_offset" , 3, 832, 855, /* name,aux,lo,hi */933NULL , 0, 0, /* faka,flo,fhi */934"rx_ddp_buf0_offset" , /* aka */935COMP_NONE , /* comp */936"Current offset into DDP buffer 0", /*desc*/937NULL, /*akadesc */938},939{"rx_ddp_buf0_len" , 3, 856, 879, /* name,aux,lo,hi */940NULL , 0, 0, /* faka,flo,fhi */941"rx_ddp_buf0_len" , /* aka */942COMP_NONE , /* comp */943"Length of DDP buffer 0", /*desc*/944NULL, /*akadesc */945},946{"TF_DDP_INDICATE_OUT" , 3, 880, 880, /* name,aux,lo,hi */947"rx_ddp_flags" , 0, 0, /* faka,flo,fhi */948"ddp_indicate_out" , /* aka */949COMP_NONE , /* comp */950NULL, /*desc*/951NULL, /*akadesc */952},953{"TF_DDP_ACTIVE_BUF" , 3, 881, 881, /* name,aux,lo,hi */954"rx_ddp_flags" , 1, 1, /* faka,flo,fhi */955"ddp_active_buf" , /* aka */956COMP_NONE , /* comp */957NULL, /*desc*/958NULL, /*akadesc */959},960{"TF_DDP_OFF" , 3, 882, 882, /* name,aux,lo,hi */961"rx_ddp_flags" , 2, 2, /* faka,flo,fhi */962"ddp_off" , /* aka */963COMP_NONE , /* comp */964NULL, /*desc*/965NULL, /*akadesc */966},967{"TF_DDP_WAIT_FRAG" , 3, 883, 883, /* name,aux,lo,hi */968"rx_ddp_flags" , 3, 3, /* faka,flo,fhi */969"ddp_wait_frag" , /* aka */970COMP_NONE , /* comp */971NULL, /*desc*/972NULL, /*akadesc */973},974{"TF_DDP_BUF_INF" , 3, 884, 884, /* name,aux,lo,hi */975"rx_ddp_flags" , 4, 4, /* faka,flo,fhi */976"ddp_buf_inf" , /* aka */977COMP_NONE , /* comp */978NULL, /*desc*/979NULL, /*akadesc */980},981{"TF_DDP_RX2TX" , 3, 885, 885, /* name,aux,lo,hi */982"rx_ddp_flags" , 5, 5, /* faka,flo,fhi */983"ddp_rx2tx" , /* aka */984COMP_NONE , /* comp */985NULL, /*desc*/986NULL, /*akadesc */987},988{"TF_DDP_MAIN_UNUSED" , 3, 886, 887, /* name,aux,lo,hi */989"rx_ddp_flags" , 6, 7, /* faka,flo,fhi */990"ddp_main_unused" , /* aka */991COMP_NONE , /* comp */992NULL, /*desc*/993NULL, /*akadesc */994},995{"TF_DDP_BUF0_VALID" , 3, 888, 888, /* name,aux,lo,hi */996"rx_ddp_flags" , 8, 8, /* faka,flo,fhi */997"ddp_buf0_valid" , /* aka */998COMP_NONE , /* comp */999NULL, /*desc*/1000NULL, /*akadesc */1001},1002{"TF_DDP_BUF0_INDICATE" , 3, 889, 889, /* name,aux,lo,hi */1003"rx_ddp_flags" , 9, 9, /* faka,flo,fhi */1004"ddp_buf0_indicate" , /* aka */1005COMP_NONE , /* comp */1006NULL, /*desc*/1007NULL, /*akadesc */1008},1009{"TF_DDP_BUF0_FLUSH" , 3, 890, 890, /* name,aux,lo,hi */1010"rx_ddp_flags" , 10, 10, /* faka,flo,fhi */1011"ddp_buf0_flush" , /* aka */1012COMP_NONE , /* comp */1013NULL, /*desc*/1014NULL, /*akadesc */1015},1016{"TF_DDP_PSHF_ENABLE_0" , 3, 891, 891, /* name,aux,lo,hi */1017"rx_ddp_flags" , 11, 11, /* faka,flo,fhi */1018"ddp_pshf_enable_0" , /* aka */1019COMP_NONE , /* comp */1020NULL, /*desc*/1021NULL, /*akadesc */1022},1023{"TF_DDP_PUSH_DISABLE_0" , 3, 892, 892, /* name,aux,lo,hi */1024"rx_ddp_flags" , 12, 12, /* faka,flo,fhi */1025"ddp_push_disable_0" , /* aka */1026COMP_NONE , /* comp */1027NULL, /*desc*/1028NULL, /*akadesc */1029},1030{"TF_DDP_PSH_NO_INVALIDATE0" , 3, 893, 893, /* name,aux,lo,hi */1031"rx_ddp_flags" , 13, 13, /* faka,flo,fhi */1032"ddp_psh_no_invalidate0" , /* aka */1033COMP_NONE , /* comp */1034NULL, /*desc*/1035NULL, /*akadesc */1036},1037{"TF_DDP_BUF0_UNUSED" , 3, 894, 895, /* name,aux,lo,hi */1038"rx_ddp_flags" , 14, 15, /* faka,flo,fhi */1039"ddp_buf0_unused" , /* aka */1040COMP_NONE , /* comp */1041NULL, /*desc*/1042NULL, /*akadesc */1043},1044{"TF_DDP_BUF1_VALID" , 3, 896, 896, /* name,aux,lo,hi */1045"rx_ddp_flags" , 16, 16, /* faka,flo,fhi */1046"ddp_buf1_valid" , /* aka */1047COMP_NONE , /* comp */1048NULL, /*desc*/1049NULL, /*akadesc */1050},1051{"TF_DDP_BUF1_INDICATE" , 3, 897, 897, /* name,aux,lo,hi */1052"rx_ddp_flags" , 17, 17, /* faka,flo,fhi */1053"ddp_buf1_indicate" , /* aka */1054COMP_NONE , /* comp */1055NULL, /*desc*/1056NULL, /*akadesc */1057},1058{"TF_DDP_BUF1_FLUSH" , 3, 898, 898, /* name,aux,lo,hi */1059"rx_ddp_flags" , 18, 18, /* faka,flo,fhi */1060"ddp_buf1_flush" , /* aka */1061COMP_NONE , /* comp */1062NULL, /*desc*/1063NULL, /*akadesc */1064},1065{"TF_DDP_PSHF_ENABLE_1" , 3, 899, 899, /* name,aux,lo,hi */1066"rx_ddp_flags" , 19, 19, /* faka,flo,fhi */1067"ddp_pshf_enable_1" , /* aka */1068COMP_NONE , /* comp */1069NULL, /*desc*/1070NULL, /*akadesc */1071},1072{"TF_DDP_PUSH_DISABLE_1" , 3, 900, 900, /* name,aux,lo,hi */1073"rx_ddp_flags" , 20, 20, /* faka,flo,fhi */1074"ddp_push_disable_1" , /* aka */1075COMP_NONE , /* comp */1076NULL, /*desc*/1077NULL, /*akadesc */1078},1079{"TF_DDP_PSH_NO_INVALIDATE1" , 3, 901, 901, /* name,aux,lo,hi */1080"rx_ddp_flags" , 21, 21, /* faka,flo,fhi */1081"ddp_psh_no_invalidate1" , /* aka */1082COMP_NONE , /* comp */1083NULL, /*desc*/1084NULL, /*akadesc */1085},1086{"TF_DDP_BUF1_UNUSED" , 3, 902, 903, /* name,aux,lo,hi */1087"rx_ddp_flags" , 22, 23, /* faka,flo,fhi */1088"ddp_buf1_unused" , /* aka */1089COMP_NONE , /* comp */1090NULL, /*desc*/1091NULL, /*akadesc */1092},1093{"rx_ddp_buf1_offset" , 3, 904, 927, /* name,aux,lo,hi */1094NULL , 0, 0, /* faka,flo,fhi */1095"rx_ddp_buf1_offset" , /* aka */1096COMP_NONE , /* comp */1097"Current offset into DDP buffer 1", /*desc*/1098NULL, /*akadesc */1099},1100{"rx_ddp_buf1_len" , 3, 928, 951, /* name,aux,lo,hi */1101NULL , 0, 0, /* faka,flo,fhi */1102"rx_ddp_buf1_len" , /* aka */1103COMP_NONE , /* comp */1104"Length of DDP buffer 1", /*desc*/1105NULL, /*akadesc */1106},1107{"aux3_slush" , 3, 952, 959, /* name,aux,lo,hi */1108NULL , 0, 0, /* faka,flo,fhi */1109"aux3_slush" , /* aka */1110COMP_NONE , /* comp */1111"Reserved", /*desc*/1112NULL, /*akadesc */1113},1114{"rx_ddp_buf0_tag" , 3, 960, 991, /* name,aux,lo,hi */1115NULL , 0, 0, /* faka,flo,fhi */1116"rx_ddp_buf0_tag" , /* aka */1117COMP_NONE , /* comp */1118"Tag for DDP buffer 0", /*desc*/1119NULL, /*akadesc */1120},1121{"rx_ddp_buf1_tag" , 3, 992, 1023, /* name,aux,lo,hi */1122NULL , 0, 0, /* faka,flo,fhi */1123"rx_ddp_buf1_tag" , /* aka */1124COMP_NONE , /* comp */1125"Tag for DDP buffer 1", /*desc*/1126NULL, /*akadesc */1127},1128{NULL,0,0,0, NULL,0,0, NULL, 0, NULL, NULL}, /*terminator*/1129};11301131/* ====================================================== */1132_TCBVAR g_scb_info4[]={1133{"OPT_1_RSS_INFO" , 0, 0, 11, /* name,aux,lo,hi */1134NULL , 0, 0, /* faka,flo,fhi */1135"OPT_1_RSS_INFO" , /* aka */1136COMP_NONE , /* comp */1137NULL, /*desc*/1138NULL, /*akadesc */1139},1140{"OPT_1_LISTEN_INTERFACE" , 0, 12, 19, /* name,aux,lo,hi */1141NULL , 0, 0, /* faka,flo,fhi */1142"OPT_1_LISTEN_INTERFACE" , /* aka */1143COMP_NONE , /* comp */1144NULL, /*desc*/1145NULL, /*akadesc */1146},1147{"OPT_1_LISTEN_FILTER" , 0, 20, 20, /* name,aux,lo,hi */1148NULL , 0, 0, /* faka,flo,fhi */1149"OPT_1_LISTEN_FILTER" , /* aka */1150COMP_NONE , /* comp */1151NULL, /*desc*/1152NULL, /*akadesc */1153},1154{"OPT_1_SYN_DEFENSE" , 0, 21, 21, /* name,aux,lo,hi */1155NULL , 0, 0, /* faka,flo,fhi */1156"OPT_1_SYN_DEFENSE" , /* aka */1157COMP_NONE , /* comp */1158NULL, /*desc*/1159NULL, /*akadesc */1160},1161{"OPT_1_CONNECTION_POLICY" , 0, 22, 23, /* name,aux,lo,hi */1162NULL , 0, 0, /* faka,flo,fhi */1163"OPT_1_CONNECTION_POLICY" , /* aka */1164COMP_NONE , /* comp */1165NULL, /*desc*/1166NULL, /*akadesc */1167},1168{"OPT_1_FLT_INFO" , 0, 28, 63, /* name,aux,lo,hi */1169NULL , 0, 0, /* faka,flo,fhi */1170"OPT_1_FLT_INFO" , /* aka */1171COMP_NONE , /* comp */1172NULL, /*desc*/1173NULL, /*akadesc */1174},1175{"OPT_0_ACCEPT_MODE" , 0, 64, 65, /* name,aux,lo,hi */1176NULL , 0, 0, /* faka,flo,fhi */1177"OPT_0_ACCEPT_MODE" , /* aka */1178COMP_NONE , /* comp */1179NULL, /*desc*/1180NULL, /*akadesc */1181},1182{"OPT_0_TX_CHANNEL" , 0, 66, 67, /* name,aux,lo,hi */1183NULL , 0, 0, /* faka,flo,fhi */1184"OPT_0_TX_CHANNEL" , /* aka */1185COMP_NONE , /* comp */1186NULL, /*desc*/1187NULL, /*akadesc */1188},1189{"OPT_0_NO_CONGESTION_CONTROL" , 0, 68, 68, /* name,aux,lo,hi */1190NULL , 0, 0, /* faka,flo,fhi */1191"OPT_0_NO_CONGESTION_CONTROL" , /* aka */1192COMP_NONE , /* comp */1193NULL, /*desc*/1194NULL, /*akadesc */1195},1196{"OPT_0_DELAYED_ACK" , 0, 69, 69, /* name,aux,lo,hi */1197NULL , 0, 0, /* faka,flo,fhi */1198"OPT_0_DELAYED_ACK" , /* aka */1199COMP_NONE , /* comp */1200NULL, /*desc*/1201NULL, /*akadesc */1202},1203{"OPT_0_INJECT_TIMER" , 0, 70, 70, /* name,aux,lo,hi */1204NULL , 0, 0, /* faka,flo,fhi */1205"OPT_0_INJECT_TIMER" , /* aka */1206COMP_NONE , /* comp */1207NULL, /*desc*/1208NULL, /*akadesc */1209},1210{"OPT_0_NON_OFFLOAD" , 0, 71, 71, /* name,aux,lo,hi */1211NULL , 0, 0, /* faka,flo,fhi */1212"OPT_0_NON_OFFLOAD" , /* aka */1213COMP_NONE , /* comp */1214NULL, /*desc*/1215NULL, /*akadesc */1216},1217{"OPT_0_ULP_MODE" , 0, 72, 75, /* name,aux,lo,hi */1218NULL , 0, 0, /* faka,flo,fhi */1219"OPT_0_ULP_MODE" , /* aka */1220COMP_NONE , /* comp */1221NULL, /*desc*/1222NULL, /*akadesc */1223},1224{"OPT_0_MAX_RCV_BUFFER" , 0, 76, 85, /* name,aux,lo,hi */1225NULL , 0, 0, /* faka,flo,fhi */1226"OPT_0_MAX_RCV_BUFFER" , /* aka */1227COMP_NONE , /* comp */1228NULL, /*desc*/1229NULL, /*akadesc */1230},1231{"OPT_0_TOS" , 0, 86, 91, /* name,aux,lo,hi */1232NULL , 0, 0, /* faka,flo,fhi */1233"OPT_0_TOS" , /* aka */1234COMP_NONE , /* comp */1235NULL, /*desc*/1236NULL, /*akadesc */1237},1238{"OPT_0_SM_SEL" , 0, 92, 99, /* name,aux,lo,hi */1239NULL , 0, 0, /* faka,flo,fhi */1240"OPT_0_SM_SEL" , /* aka */1241COMP_NONE , /* comp */1242NULL, /*desc*/1243NULL, /*akadesc */1244},1245{"OPT_0_L2T_IX" , 0, 100, 111, /* name,aux,lo,hi */1246NULL , 0, 0, /* faka,flo,fhi */1247"OPT_0_L2T_IX" , /* aka */1248COMP_NONE , /* comp */1249NULL, /*desc*/1250NULL, /*akadesc */1251},1252{"OPT_0_TCAM_BYPASS" , 0, 112, 112, /* name,aux,lo,hi */1253NULL , 0, 0, /* faka,flo,fhi */1254"OPT_0_TCAM_BYPASS" , /* aka */1255COMP_NONE , /* comp */1256NULL, /*desc*/1257NULL, /*akadesc */1258},1259{"OPT_0_NAGLE" , 0, 113, 113, /* name,aux,lo,hi */1260NULL , 0, 0, /* faka,flo,fhi */1261"OPT_0_NAGLE" , /* aka */1262COMP_NONE , /* comp */1263NULL, /*desc*/1264NULL, /*akadesc */1265},1266{"OPT_0_WSF" , 0, 114, 117, /* name,aux,lo,hi */1267NULL , 0, 0, /* faka,flo,fhi */1268"OPT_0_WSF" , /* aka */1269COMP_NONE , /* comp */1270NULL, /*desc*/1271NULL, /*akadesc */1272},1273{"OPT_0_KEEPALIVE" , 0, 118, 118, /* name,aux,lo,hi */1274NULL , 0, 0, /* faka,flo,fhi */1275"OPT_0_KEEPALIVE" , /* aka */1276COMP_NONE , /* comp */1277NULL, /*desc*/1278NULL, /*akadesc */1279},1280{"OPT_0_CONN_MAXRT" , 0, 119, 122, /* name,aux,lo,hi */1281NULL , 0, 0, /* faka,flo,fhi */1282"OPT_0_CONN_MAXRT" , /* aka */1283COMP_NONE , /* comp */1284NULL, /*desc*/1285NULL, /*akadesc */1286},1287{"OPT_0_MAXRT_OVERRIDE" , 0, 123, 123, /* name,aux,lo,hi */1288NULL , 0, 0, /* faka,flo,fhi */1289"OPT_0_MAXRT_OVERRIDE" , /* aka */1290COMP_NONE , /* comp */1291NULL, /*desc*/1292NULL, /*akadesc */1293},1294{"OPT_0_MAX_SEG" , 0, 124, 127, /* name,aux,lo,hi */1295NULL , 0, 0, /* faka,flo,fhi */1296"OPT_0_MAX_SEG" , /* aka */1297COMP_NONE , /* comp */1298NULL, /*desc*/1299NULL, /*akadesc */1300},1301{"scb_slush" , 0, 128, 1023, /* name,aux,lo,hi */1302NULL , 0, 0, /* faka,flo,fhi */1303"scb_slush" , /* aka */1304COMP_NONE , /* comp */1305NULL, /*desc*/1306NULL, /*akadesc */1307},1308{NULL,0,0,0, NULL,0,0, NULL, 0, NULL, NULL}, /*terminator*/1309};13101311/* ====================================================== */1312_TCBVAR g_fcb_info4[]={1313{"filter" , 0, 33, 33, /* name,aux,lo,hi */1314NULL , 0, 0, /* faka,flo,fhi */1315"filter" , /* aka */1316COMP_NONE , /* comp */1317NULL, /*desc*/1318NULL, /*akadesc */1319},1320{"Report_TID" , 0, 53, 53, /* name,aux,lo,hi */1321NULL , 0, 0, /* faka,flo,fhi */1322"Report_TID" , /* aka */1323COMP_NONE , /* comp */1324NULL, /*desc*/1325NULL, /*akadesc */1326},1327{"Drop" , 0, 54, 54, /* name,aux,lo,hi */1328NULL , 0, 0, /* faka,flo,fhi */1329"Drop" , /* aka */1330COMP_NONE , /* comp */1331NULL, /*desc*/1332NULL, /*akadesc */1333},1334{"Direct_Steer" , 0, 55, 55, /* name,aux,lo,hi */1335NULL , 0, 0, /* faka,flo,fhi */1336"Direct_Steer" , /* aka */1337COMP_NONE , /* comp */1338NULL, /*desc*/1339NULL, /*akadesc */1340},1341{"Mask_Hash" , 0, 48, 48, /* name,aux,lo,hi */1342NULL , 0, 0, /* faka,flo,fhi */1343"Mask_Hash" , /* aka */1344COMP_NONE , /* comp */1345NULL, /*desc*/1346NULL, /*akadesc */1347},1348{"Direct_Steer_Hash" , 0, 49, 49, /* name,aux,lo,hi */1349NULL , 0, 0, /* faka,flo,fhi */1350"Direct_Steer_Hash" , /* aka */1351COMP_NONE , /* comp */1352NULL, /*desc*/1353NULL, /*akadesc */1354},1355{"Loopback" , 0, 91, 91, /* name,aux,lo,hi */1356NULL , 0, 0, /* faka,flo,fhi */1357"Loopback" , /* aka */1358COMP_NONE , /* comp */1359NULL, /*desc*/1360NULL, /*akadesc */1361},1362{"Loopback_TX_Channel" , 0, 44, 45, /* name,aux,lo,hi */1363NULL , 0, 0, /* faka,flo,fhi */1364"Loopback_TX_Channel" , /* aka */1365COMP_NONE , /* comp */1366NULL, /*desc*/1367NULL, /*akadesc */1368},1369{"Rewrite_DMAC" , 0, 92, 92, /* name,aux,lo,hi */1370NULL , 0, 0, /* faka,flo,fhi */1371"Rewrite_DMAC" , /* aka */1372COMP_NONE , /* comp */1373NULL, /*desc*/1374NULL, /*akadesc */1375},1376{"Rewrite_SMAC" , 0, 93, 93, /* name,aux,lo,hi */1377NULL , 0, 0, /* faka,flo,fhi */1378"Rewrite_SMAC" , /* aka */1379COMP_NONE , /* comp */1380NULL, /*desc*/1381NULL, /*akadesc */1382},1383{"Insert_VLAN" , 0, 94, 94, /* name,aux,lo,hi */1384NULL , 0, 0, /* faka,flo,fhi */1385"Insert_VLAN" , /* aka */1386COMP_NONE , /* comp */1387NULL, /*desc*/1388NULL, /*akadesc */1389},1390{"Remove_VLAN" , 0, 39, 39, /* name,aux,lo,hi */1391NULL , 0, 0, /* faka,flo,fhi */1392"Remove_VLAN" , /* aka */1393COMP_NONE , /* comp */1394NULL, /*desc*/1395NULL, /*akadesc */1396},1397{"Count_Hits" , 0, 36, 36, /* name,aux,lo,hi */1398NULL , 0, 0, /* faka,flo,fhi */1399"Count_Hits" , /* aka */1400COMP_NONE , /* comp */1401NULL, /*desc*/1402NULL, /*akadesc */1403},1404{"Hits_high" , 0, 224, 255, /* name,aux,lo,hi */1405NULL , 0, 0, /* faka,flo,fhi */1406"Hits_high" , /* aka */1407COMP_NONE , /* comp */1408NULL, /*desc*/1409NULL, /*akadesc */1410},1411{"Hits_low" , 0, 192, 223, /* name,aux,lo,hi */1412NULL , 0, 0, /* faka,flo,fhi */1413"Hits_low" , /* aka */1414COMP_NONE , /* comp */1415NULL, /*desc*/1416NULL, /*akadesc */1417},1418{NULL,0,0,0, NULL,0,0, NULL, 0, NULL, NULL}, /*terminator*/1419};1420142114221423