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godotengine
GitHub Repository: godotengine/godot
 Path: blob/master/thirdparty/basis_universal/encoder/basisu_kernels_sse.cpp
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// basisu_kernels_sse.cpp

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// Copyright (C) 2019-2024 Binomial LLC. All Rights Reserved.

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//

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// Licensed under the Apache License, Version 2.0 (the "License");

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// you may not use this file except in compliance with the License.

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// You may obtain a copy of the License at

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//

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//    http://www.apache.org/licenses/LICENSE-2.0

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//

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// Unless required by applicable law or agreed to in writing, software

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// distributed under the License is distributed on an "AS IS" BASIS,

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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

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// See the License for the specific language governing permissions and

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// limitations under the License.

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#include "basisu_enc.h"

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#if BASISU_SUPPORT_SSE

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#define CPPSPMD_SSE2 0

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#ifdef _MSC_VER

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#include <intrin.h>

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#endif

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#include "cppspmd_sse.h"

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#include "cppspmd_type_aliases.h"

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using namespace basisu;

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#include "basisu_kernels_declares.h"

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#include "basisu_kernels_imp.h"

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namespace basisu

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{

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struct cpu_info

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{

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	cpu_info() { memset(this, 0, sizeof(*this)); }

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	bool m_has_fpu;

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	bool m_has_mmx;

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	bool m_has_sse;

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	bool m_has_sse2;

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	bool m_has_sse3;

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	bool m_has_ssse3;

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	bool m_has_sse41;

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	bool m_has_sse42;

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	bool m_has_avx;

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	bool m_has_avx2;

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	bool m_has_pclmulqdq;

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};

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static void extract_x86_flags(cpu_info &info, uint32_t ecx, uint32_t edx)

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{

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	info.m_has_fpu = (edx & (1 << 0)) != 0;

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	info.m_has_mmx = (edx & (1 << 23)) != 0;

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	info.m_has_sse = (edx & (1 << 25)) != 0;

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	info.m_has_sse2 = (edx & (1 << 26)) != 0;

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	info.m_has_sse3 = (ecx & (1 << 0)) != 0;

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	info.m_has_ssse3 = (ecx & (1 << 9)) != 0;

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	info.m_has_sse41 = (ecx & (1 << 19)) != 0;

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	info.m_has_sse42 = (ecx & (1 << 20)) != 0;

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	info.m_has_pclmulqdq = (ecx & (1 << 1)) != 0;

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	info.m_has_avx = (ecx & (1 << 28)) != 0;

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}

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static void extract_x86_extended_flags(cpu_info &info, uint32_t ebx)

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{

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	info.m_has_avx2 = (ebx & (1 << 5)) != 0;

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}

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#ifndef _MSC_VER

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static void do_cpuid(uint32_t eax, uint32_t ecx, uint32_t* regs)

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{

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	uint32_t ebx = 0, edx = 0;

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#if defined(__PIC__) && defined(__i386__)

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	__asm__("movl %%ebx, %%edi;"

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		"cpuid;"

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		"xchgl %%ebx, %%edi;"

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		: "=D"(ebx), "+a"(eax), "+c"(ecx), "=d"(edx));

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#else

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	__asm__("cpuid;" : "+b"(ebx), "+a"(eax), "+c"(ecx), "=d"(edx));

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#endif

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	regs[0] = eax; regs[1] = ebx; regs[2] = ecx; regs[3] = edx;

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}

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#endif

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static void get_cpuinfo(cpu_info &info)

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{

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	int regs[4];

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#ifdef _MSC_VER

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	__cpuid(regs, 0);

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#else

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	do_cpuid(0, 0, (uint32_t *)regs);

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#endif

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	const uint32_t max_eax = regs[0];

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	if (max_eax >= 1U)

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	{

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#ifdef _MSC_VER

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		__cpuid(regs, 1);

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#else

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		do_cpuid(1, 0, (uint32_t*)regs);

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#endif

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		extract_x86_flags(info, regs[2], regs[3]);

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	}

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	if (max_eax >= 7U)

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	{

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#ifdef _MSC_VER

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		__cpuidex(regs, 7, 0);

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#else

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		do_cpuid(7, 0, (uint32_t*)regs);

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#endif

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		extract_x86_extended_flags(info, regs[1]);

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	}

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}

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void detect_sse41()

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{

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	cpu_info info;

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	get_cpuinfo(info);

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	// Check for everything from SSE to SSE 4.1

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	g_cpu_supports_sse41 = info.m_has_sse && info.m_has_sse2 && info.m_has_sse3 && info.m_has_ssse3 && info.m_has_sse41;

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}

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} // namespace basisu

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#else // #if BASISU_SUPPORT_SSE

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namespace basisu

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{

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void detect_sse41()

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{

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}

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} // namespace basisu

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#endif // #if BASISU_SUPPORT_SSE

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