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godotengine
GitHub Repository: godotengine/godot
 Path: blob/master/thirdparty/libtheora/x86/x86state.c
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/********************************************************************

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 *                                                                  *

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 * THIS FILE IS PART OF THE OggTheora SOFTWARE CODEC SOURCE CODE.   *

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 * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS     *

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 * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *

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 * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING.       *

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 *                                                                  *

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 * THE Theora SOURCE CODE IS COPYRIGHT (C) 2002-2009                *

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 * by the Xiph.Org Foundation and contributors                      *

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 * https://www.xiph.org/                                            *

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 *                                                                  *

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 ********************************************************************

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  function:

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 ********************************************************************/

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#include "x86int.h"

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#if defined(OC_X86_ASM)

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#if defined(OC_STATE_USE_VTABLE)

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/*This table has been modified from OC_FZIG_ZAG by baking a 4x4 transpose into

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   each quadrant of the destination.*/

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static const unsigned char OC_FZIG_ZAG_MMX[128]={

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   0, 8, 1, 2, 9,16,24,17,

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  10, 3,32,11,18,25, 4,12,

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   5,26,19,40,33,34,41,48,

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  27, 6,13,20,28,21,14, 7,

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  56,49,42,35,43,50,57,36,

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  15,22,29,30,23,44,37,58,

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  51,59,38,45,52,31,60,53,

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  46,39,47,54,61,62,55,63,

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  64,64,64,64,64,64,64,64,

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  64,64,64,64,64,64,64,64,

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  64,64,64,64,64,64,64,64,

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  64,64,64,64,64,64,64,64,

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  64,64,64,64,64,64,64,64,

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  64,64,64,64,64,64,64,64,

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  64,64,64,64,64,64,64,64,

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  64,64,64,64,64,64,64,64

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};

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#endif

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/*This table has been modified from OC_FZIG_ZAG by baking an 8x8 transpose into

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   the destination.*/

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static const unsigned char OC_FZIG_ZAG_SSE2[128]={

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   0, 8, 1, 2, 9,16,24,17,

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  10, 3, 4,11,18,25,32,40,

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  33,26,19,12, 5, 6,13,20,

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  27,34,41,48,56,49,42,35,

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  28,21,14, 7,15,22,29,36,

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  43,50,57,58,51,44,37,30,

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  23,31,38,45,52,59,60,53,

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  46,39,47,54,61,62,55,63,

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  64,64,64,64,64,64,64,64,

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  64,64,64,64,64,64,64,64,

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  64,64,64,64,64,64,64,64,

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  64,64,64,64,64,64,64,64,

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  64,64,64,64,64,64,64,64,

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  64,64,64,64,64,64,64,64,

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  64,64,64,64,64,64,64,64,

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  64,64,64,64,64,64,64,64

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};

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void oc_state_accel_init_x86(oc_theora_state *_state){

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  oc_state_accel_init_c(_state);

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  _state->cpu_flags=oc_cpu_flags_get();

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# if defined(OC_STATE_USE_VTABLE)

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  if(_state->cpu_flags&OC_CPU_X86_MMX){

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    _state->opt_vtable.frag_copy=oc_frag_copy_mmx;

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    _state->opt_vtable.frag_copy_list=oc_frag_copy_list_mmx;

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    _state->opt_vtable.frag_recon_intra=oc_frag_recon_intra_mmx;

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    _state->opt_vtable.frag_recon_inter=oc_frag_recon_inter_mmx;

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    _state->opt_vtable.frag_recon_inter2=oc_frag_recon_inter2_mmx;

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    _state->opt_vtable.idct8x8=oc_idct8x8_mmx;

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    _state->opt_vtable.state_frag_recon=oc_state_frag_recon_mmx;

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    _state->opt_vtable.loop_filter_init=oc_loop_filter_init_mmx;

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    _state->opt_vtable.state_loop_filter_frag_rows=

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     oc_state_loop_filter_frag_rows_mmx;

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    _state->opt_vtable.restore_fpu=oc_restore_fpu_mmx;

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    _state->opt_data.dct_fzig_zag=OC_FZIG_ZAG_MMX;

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  }

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  if(_state->cpu_flags&OC_CPU_X86_MMXEXT){

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    _state->opt_vtable.loop_filter_init=oc_loop_filter_init_mmxext;

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    _state->opt_vtable.state_loop_filter_frag_rows=

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     oc_state_loop_filter_frag_rows_mmxext;

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  }

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  if(_state->cpu_flags&OC_CPU_X86_SSE2){

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    _state->opt_vtable.idct8x8=oc_idct8x8_sse2;

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# endif

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    _state->opt_data.dct_fzig_zag=OC_FZIG_ZAG_SSE2;

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# if defined(OC_STATE_USE_VTABLE)

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  }

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# endif

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}

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#endif

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