Path: blob/master/thirdparty/libtheora/x86_vc/x86state.c
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/********************************************************************1* *2* THIS FILE IS PART OF THE OggTheora SOFTWARE CODEC SOURCE CODE. *3* USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *4* GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *5* IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *6* *7* THE Theora SOURCE CODE IS COPYRIGHT (C) 2002-2009 *8* by the Xiph.Org Foundation and contributors *9* https://www.xiph.org/ *10* *11********************************************************************1213function:1415********************************************************************/1617#include "x86int.h"1819#if defined(OC_X86_ASM)2021/*This table has been modified from OC_FZIG_ZAG by baking a 4x4 transpose into22each quadrant of the destination.*/23static const unsigned char OC_FZIG_ZAG_MMX[128]={240, 8, 1, 2, 9,16,24,17,2510, 3,32,11,18,25, 4,12,265,26,19,40,33,34,41,48,2727, 6,13,20,28,21,14, 7,2856,49,42,35,43,50,57,36,2915,22,29,30,23,44,37,58,3051,59,38,45,52,31,60,53,3146,39,47,54,61,62,55,63,3264,64,64,64,64,64,64,64,3364,64,64,64,64,64,64,64,3464,64,64,64,64,64,64,64,3564,64,64,64,64,64,64,64,3664,64,64,64,64,64,64,64,3764,64,64,64,64,64,64,64,3864,64,64,64,64,64,64,64,3964,64,64,64,64,64,64,64,40};4142void oc_state_accel_init_x86(oc_theora_state *_state){43_state->cpu_flags=oc_cpu_flags_get();44if(_state->cpu_flags&OC_CPU_X86_MMX){45_state->opt_vtable.frag_copy=oc_frag_copy_mmx;46_state->opt_vtable.frag_copy_list=oc_frag_copy_list_mmx;47_state->opt_vtable.frag_recon_intra=oc_frag_recon_intra_mmx;48_state->opt_vtable.frag_recon_inter=oc_frag_recon_inter_mmx;49_state->opt_vtable.frag_recon_inter2=oc_frag_recon_inter2_mmx;50_state->opt_vtable.idct8x8=oc_idct8x8_mmx;51_state->opt_vtable.state_frag_recon=oc_state_frag_recon_mmx;52_state->opt_vtable.loop_filter_init=oc_loop_filter_init_mmx;53_state->opt_vtable.state_loop_filter_frag_rows=54oc_state_loop_filter_frag_rows_mmx;55_state->opt_vtable.restore_fpu=oc_restore_fpu_mmx;56_state->opt_data.dct_fzig_zag=OC_FZIG_ZAG_MMX;57}58else oc_state_accel_init_c(_state);59}60#endif616263