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GitHub Repository: google/crosvm
Path: blob/main/hypervisor/src/whpx/whpx_sys/WinHvPlatformDefs.h
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/*++
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Copyright (c) Microsoft Corporation. All rights reserved.
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Module Name:
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WinHvPlatformDefs.h
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Abstract:
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This module contains the constant, type and structure definitions for
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the Windows Hypervisor User-Mode APIs.
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--*/
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#ifndef _WINHVAPIDEFS_H_
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#define _WINHVAPIDEFS_H_
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#if defined(_MSC_VER) && (_MSC_VER >= 1200)
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#pragma once
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#pragma warning(push)
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#pragma warning(disable:4201) /* nonstandard extension used: nameless struct/union */
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#pragma warning(disable:4214) /* nonstandard extension used: bit field types other than int */
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#endif
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//
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// Platform capabilities
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//
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typedef enum WHV_CAPABILITY_CODE
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{
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// Capabilities of the API implementation
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WHvCapabilityCodeHypervisorPresent = 0x00000000,
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WHvCapabilityCodeFeatures = 0x00000001,
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WHvCapabilityCodeExtendedVmExits = 0x00000002,
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WHvCapabilityCodeExceptionExitBitmap = 0x00000003,
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WHvCapabilityCodeX64MsrExitBitmap = 0x00000004,
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// Capabilities of the system's processor
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WHvCapabilityCodeProcessorVendor = 0x00001000,
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WHvCapabilityCodeProcessorFeatures = 0x00001001,
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WHvCapabilityCodeProcessorClFlushSize = 0x00001002,
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WHvCapabilityCodeProcessorXsaveFeatures = 0x00001003,
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WHvCapabilityCodeProcessorClockFrequency = 0x00001004,
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WHvCapabilityCodeInterruptClockFrequency = 0x00001005,
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WHvCapabilityCodeProcessorFeaturesBanks = 0x00001006,
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} WHV_CAPABILITY_CODE;
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//
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// Return values for WhvCapabilityCodeFeatures
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//
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typedef union WHV_CAPABILITY_FEATURES
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{
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struct
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{
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UINT64 PartialUnmap : 1;
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UINT64 LocalApicEmulation : 1;
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UINT64 Xsave : 1;
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UINT64 DirtyPageTracking : 1;
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UINT64 SpeculationControl : 1;
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UINT64 ApicRemoteRead : 1;
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UINT64 IdleSuspend : 1;
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UINT64 Reserved : 57;
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};
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UINT64 AsUINT64;
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} WHV_CAPABILITY_FEATURES;
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C_ASSERT(sizeof(WHV_CAPABILITY_FEATURES) == sizeof(UINT64));
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//
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// Return values for WhvCapabilityCodeExtendedVmExits and input buffer for
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// WHvPartitionPropertyCodeExtendedVmExits
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//
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typedef union WHV_EXTENDED_VM_EXITS
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{
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struct
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{
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UINT64 X64CpuidExit : 1; // WHvRunVpExitReasonX64CPUID supported
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UINT64 X64MsrExit : 1; // WHvRunVpExitX64ReasonMSRAccess supported
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UINT64 ExceptionExit : 1; // WHvRunVpExitReasonException supported
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UINT64 X64RdtscExit : 1; // WHvRunVpExitReasonX64Rdtsc supported
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UINT64 X64ApicSmiExitTrap : 1; // WHvRunVpExitReasonX64ApicSmiTrap supported
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UINT64 HypercallExit : 1; // WHvRunVpExitReasonHypercall supported
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UINT64 X64ApicInitSipiExitTrap : 1; // WHvRunVpExitReasonX64ApicInitSipiTrap supported
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UINT64 Reserved : 57;
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};
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UINT64 AsUINT64;
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} WHV_EXTENDED_VM_EXITS;
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C_ASSERT(sizeof(WHV_EXTENDED_VM_EXITS) == sizeof(UINT64));
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//
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// Return values for WhvCapabilityCodeProcessorVendor
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//
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typedef enum WHV_PROCESSOR_VENDOR
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{
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WHvProcessorVendorAmd = 0x0000,
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WHvProcessorVendorIntel = 0x0001,
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WHvProcessorVendorHygon = 0x0002
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} WHV_PROCESSOR_VENDOR;
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//
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// Return values for WhvCapabilityCodeProcessorFeatures and input buffer for
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// WHvPartitionPropertyCodeProcessorFeatures. Additionally the value is embeded
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// in WHV_PROCESSOR_FEATURES_BANKS.
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//
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typedef union WHV_PROCESSOR_FEATURES
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{
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struct
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{
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UINT64 Sse3Support : 1;
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UINT64 LahfSahfSupport : 1;
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UINT64 Ssse3Support : 1;
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UINT64 Sse4_1Support : 1;
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UINT64 Sse4_2Support : 1;
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UINT64 Sse4aSupport : 1;
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UINT64 XopSupport : 1;
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UINT64 PopCntSupport : 1;
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UINT64 Cmpxchg16bSupport : 1;
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UINT64 Altmovcr8Support : 1;
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UINT64 LzcntSupport : 1;
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UINT64 MisAlignSseSupport : 1;
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UINT64 MmxExtSupport : 1;
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UINT64 Amd3DNowSupport : 1;
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UINT64 ExtendedAmd3DNowSupport : 1;
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UINT64 Page1GbSupport : 1;
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UINT64 AesSupport : 1;
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UINT64 PclmulqdqSupport : 1;
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UINT64 PcidSupport : 1;
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UINT64 Fma4Support : 1;
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UINT64 F16CSupport : 1;
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UINT64 RdRandSupport : 1;
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UINT64 RdWrFsGsSupport : 1;
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UINT64 SmepSupport : 1;
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UINT64 EnhancedFastStringSupport : 1;
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UINT64 Bmi1Support : 1;
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UINT64 Bmi2Support : 1;
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UINT64 Reserved1 : 2;
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UINT64 MovbeSupport : 1;
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UINT64 Npiep1Support : 1;
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UINT64 DepX87FPUSaveSupport : 1;
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UINT64 RdSeedSupport : 1;
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UINT64 AdxSupport : 1;
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UINT64 IntelPrefetchSupport : 1;
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UINT64 SmapSupport : 1;
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UINT64 HleSupport : 1;
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UINT64 RtmSupport : 1;
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UINT64 RdtscpSupport : 1;
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UINT64 ClflushoptSupport : 1;
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UINT64 ClwbSupport : 1;
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UINT64 ShaSupport : 1;
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UINT64 X87PointersSavedSupport : 1;
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UINT64 InvpcidSupport : 1;
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UINT64 IbrsSupport : 1;
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UINT64 StibpSupport : 1;
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UINT64 IbpbSupport : 1;
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UINT64 Reserved2 : 1;
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UINT64 SsbdSupport : 1;
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UINT64 FastShortRepMovSupport : 1;
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UINT64 Reserved3 : 1;
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UINT64 RdclNo : 1;
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UINT64 IbrsAllSupport : 1;
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UINT64 Reserved4 : 1;
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UINT64 SsbNo : 1;
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UINT64 RsbANo : 1;
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UINT64 Reserved5 : 1;
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UINT64 RdPidSupport : 1;
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UINT64 UmipSupport : 1;
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UINT64 MdsNoSupport : 1;
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UINT64 MdClearSupport : 1;
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UINT64 Reserved6 : 3;
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};
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UINT64 AsUINT64;
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} WHV_PROCESSOR_FEATURES;
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C_ASSERT(sizeof(WHV_PROCESSOR_FEATURES) == sizeof(UINT64));
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//
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// Return values for WhvCapabilityCodeProcessorFeaturesBanks and input buffer
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// for WHvPartitionPropertyCodeProcessorFeaturesBanks. BanksCount must be populated
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// before calling WHP APIs.
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//
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typedef union WHV_PROCESSOR_FEATURES1
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{
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struct
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{
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UINT64 Reserved1 : 2;
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UINT64 ClZeroSupport : 1;
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UINT64 Reserved2 : 61;
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};
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UINT64 AsUINT64;
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} WHV_PROCESSOR_FEATURES1;
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C_ASSERT(sizeof(WHV_PROCESSOR_FEATURES1) == sizeof(UINT64));
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#define WHV_PROCESSOR_FEATURES_BANKS_COUNT 2
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typedef struct WHV_PROCESSOR_FEATURES_BANKS
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{
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UINT32 BanksCount;
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UINT32 Reserved0;
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union
207
{
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struct
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{
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WHV_PROCESSOR_FEATURES Bank0;
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WHV_PROCESSOR_FEATURES1 Bank1;
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};
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UINT64 AsUINT64[WHV_PROCESSOR_FEATURES_BANKS_COUNT];
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};
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} WHV_PROCESSOR_FEATURES_BANKS;
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C_ASSERT(sizeof(WHV_PROCESSOR_FEATURES_BANKS) == sizeof(UINT64) * (WHV_PROCESSOR_FEATURES_BANKS_COUNT + 1));
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//
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// Return values for WHvCapabilityCodeProcessorXsaveFeatures and input buffer
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// for WHvPartitionPropertyCodeProcessorXsaveFeatures
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//
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typedef union _WHV_PROCESSOR_XSAVE_FEATURES
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{
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struct
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{
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UINT64 XsaveSupport : 1;
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UINT64 XsaveoptSupport : 1;
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UINT64 AvxSupport : 1;
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UINT64 Avx2Support : 1;
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UINT64 FmaSupport : 1;
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UINT64 MpxSupport : 1;
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UINT64 Avx512Support : 1;
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UINT64 Avx512DQSupport : 1;
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UINT64 Avx512CDSupport : 1;
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UINT64 Avx512BWSupport : 1;
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UINT64 Avx512VLSupport : 1;
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UINT64 XsaveCompSupport : 1;
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UINT64 XsaveSupervisorSupport : 1;
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UINT64 Xcr1Support : 1;
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UINT64 Avx512BitalgSupport : 1;
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UINT64 Avx512IfmaSupport : 1;
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UINT64 Avx512VBmiSupport : 1;
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UINT64 Avx512VBmi2Support : 1;
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UINT64 Avx512VnniSupport : 1;
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UINT64 GfniSupport : 1;
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UINT64 VaesSupport : 1;
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UINT64 Avx512VPopcntdqSupport : 1;
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UINT64 VpclmulqdqSupport : 1;
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UINT64 Avx512Bf16Support:1;
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UINT64 Avx512Vp2IntersectSupport:1;
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UINT64 Reserved : 39;
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};
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UINT64 AsUINT64;
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} WHV_PROCESSOR_XSAVE_FEATURES, *PWHV_PROCESSOR_XSAVE_FEATURES;
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C_ASSERT(sizeof(WHV_PROCESSOR_XSAVE_FEATURES) == sizeof(UINT64));
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//
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// Return value for WHvCapabilityCodeX64MsrExits and input buffer for
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// WHvPartitionPropertyCodeX64MsrcExits
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//
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typedef union WHV_X64_MSR_EXIT_BITMAP
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{
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UINT64 AsUINT64;
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struct
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{
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UINT64 UnhandledMsrs:1;
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UINT64 TscMsrWrite:1;
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UINT64 TscMsrRead:1;
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UINT64 ApicBaseMsrWrite:1;
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UINT64 Reserved:60;
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};
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} WHV_X64_MSR_EXIT_BITMAP;
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C_ASSERT(sizeof(WHV_X64_MSR_EXIT_BITMAP) == sizeof(UINT64));
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//
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// WHvGetCapability output buffer
283
//
284
typedef union WHV_CAPABILITY
285
{
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BOOL HypervisorPresent;
287
WHV_CAPABILITY_FEATURES Features;
288
WHV_EXTENDED_VM_EXITS ExtendedVmExits;
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WHV_PROCESSOR_VENDOR ProcessorVendor;
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WHV_PROCESSOR_FEATURES ProcessorFeatures;
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WHV_PROCESSOR_XSAVE_FEATURES ProcessorXsaveFeatures;
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UINT8 ProcessorClFlushSize;
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UINT64 ExceptionExitBitmap;
294
WHV_X64_MSR_EXIT_BITMAP X64MsrExitBitmap;
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UINT64 ProcessorClockFrequency;
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UINT64 InterruptClockFrequency;
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WHV_PROCESSOR_FEATURES_BANKS ProcessorFeaturesBanks;
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} WHV_CAPABILITY;
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//
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// Partitions
302
//
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304
typedef VOID* WHV_PARTITION_HANDLE;
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typedef enum WHV_PARTITION_PROPERTY_CODE
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{
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WHvPartitionPropertyCodeExtendedVmExits = 0x00000001,
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WHvPartitionPropertyCodeExceptionExitBitmap = 0x00000002,
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WHvPartitionPropertyCodeSeparateSecurityDomain = 0x00000003,
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// Nested virtualization support is experimental and not supported.
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WHvPartitionPropertyCodeNestedVirtualization = 0x00000004,
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WHvPartitionPropertyCodeX64MsrExitBitmap = 0x00000005,
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WHvPartitionPropertyCodeProcessorFeatures = 0x00001001,
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WHvPartitionPropertyCodeProcessorClFlushSize = 0x00001002,
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WHvPartitionPropertyCodeCpuidExitList = 0x00001003,
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WHvPartitionPropertyCodeCpuidResultList = 0x00001004,
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WHvPartitionPropertyCodeLocalApicEmulationMode = 0x00001005,
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WHvPartitionPropertyCodeProcessorXsaveFeatures = 0x00001006,
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WHvPartitionPropertyCodeProcessorClockFrequency = 0x00001007,
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WHvPartitionPropertyCodeInterruptClockFrequency = 0x00001008,
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WHvPartitionPropertyCodeApicRemoteReadSupport = 0x00001009,
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WHvPartitionPropertyCodeProcessorFeaturesBanks = 0x0000100A,
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WHvPartitionPropertyCodeReferenceTime = 0x0000100B,
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WHvPartitionPropertyCodeProcessorCount = 0x00001fff
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} WHV_PARTITION_PROPERTY_CODE;
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//
331
// WHvPartitionPropertyCodeCpuidResultList input buffer list element.
332
//
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typedef struct WHV_X64_CPUID_RESULT
334
{
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UINT32 Function;
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UINT32 Reserved[3];
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UINT32 Eax;
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UINT32 Ebx;
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UINT32 Ecx;
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UINT32 Edx;
341
} WHV_X64_CPUID_RESULT;
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//
344
// WHvPartitionPropertyCodeExceptionBitmap enumeration values.
345
//
346
typedef enum WHV_EXCEPTION_TYPE
347
{
348
WHvX64ExceptionTypeDivideErrorFault = 0x0,
349
WHvX64ExceptionTypeDebugTrapOrFault = 0x1,
350
WHvX64ExceptionTypeBreakpointTrap = 0x3,
351
WHvX64ExceptionTypeOverflowTrap = 0x4,
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WHvX64ExceptionTypeBoundRangeFault = 0x5,
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WHvX64ExceptionTypeInvalidOpcodeFault = 0x6,
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WHvX64ExceptionTypeDeviceNotAvailableFault = 0x7,
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WHvX64ExceptionTypeDoubleFaultAbort = 0x8,
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WHvX64ExceptionTypeInvalidTaskStateSegmentFault = 0x0A,
357
WHvX64ExceptionTypeSegmentNotPresentFault = 0x0B,
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WHvX64ExceptionTypeStackFault = 0x0C,
359
WHvX64ExceptionTypeGeneralProtectionFault = 0x0D,
360
WHvX64ExceptionTypePageFault = 0x0E,
361
WHvX64ExceptionTypeFloatingPointErrorFault = 0x10,
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WHvX64ExceptionTypeAlignmentCheckFault = 0x11,
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WHvX64ExceptionTypeMachineCheckAbort = 0x12,
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WHvX64ExceptionTypeSimdFloatingPointFault = 0x13,
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} WHV_EXCEPTION_TYPE;
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typedef enum WHV_X64_LOCAL_APIC_EMULATION_MODE
368
{
369
WHvX64LocalApicEmulationModeNone,
370
WHvX64LocalApicEmulationModeXApic,
371
WHvX64LocalApicEmulationModeX2Apic
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} WHV_X64_LOCAL_APIC_EMULATION_MODE;
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374
//
375
// WHvGetPartitionProperty output buffer / WHvSetPartitionProperty input buffer
376
//
377
typedef union WHV_PARTITION_PROPERTY
378
{
379
WHV_EXTENDED_VM_EXITS ExtendedVmExits;
380
WHV_PROCESSOR_FEATURES ProcessorFeatures;
381
WHV_PROCESSOR_XSAVE_FEATURES ProcessorXsaveFeatures;
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UINT8 ProcessorClFlushSize;
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UINT32 ProcessorCount;
384
UINT32 CpuidExitList[1];
385
WHV_X64_CPUID_RESULT CpuidResultList[1];
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UINT64 ExceptionExitBitmap;
387
WHV_X64_LOCAL_APIC_EMULATION_MODE LocalApicEmulationMode;
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BOOL SeparateSecurityDomain;
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// Nested virtualization support is experimental and not supported.
390
BOOL NestedVirtualization;
391
WHV_X64_MSR_EXIT_BITMAP X64MsrExitBitmap;
392
UINT64 ProcessorClockFrequency;
393
UINT64 InterruptClockFrequency;
394
BOOL ApicRemoteRead;
395
WHV_PROCESSOR_FEATURES_BANKS ProcessorFeaturesBanks;
396
UINT64 ReferenceTime;
397
} WHV_PARTITION_PROPERTY;
398
399
//
400
// Memory Management
401
//
402
403
//
404
// Guest physical or virtual address
405
//
406
typedef UINT64 WHV_GUEST_PHYSICAL_ADDRESS;
407
typedef UINT64 WHV_GUEST_VIRTUAL_ADDRESS;
408
409
//
410
// Flags used by WHvMapGpaRange
411
//
412
typedef enum WHV_MAP_GPA_RANGE_FLAGS
413
{
414
WHvMapGpaRangeFlagNone = 0x00000000,
415
WHvMapGpaRangeFlagRead = 0x00000001,
416
WHvMapGpaRangeFlagWrite = 0x00000002,
417
WHvMapGpaRangeFlagExecute = 0x00000004,
418
WHvMapGpaRangeFlagTrackDirtyPages = 0x00000008,
419
} WHV_MAP_GPA_RANGE_FLAGS;
420
421
DEFINE_ENUM_FLAG_OPERATORS(WHV_MAP_GPA_RANGE_FLAGS);
422
423
//
424
// Flags used by WHvTranslateGva
425
//
426
typedef enum WHV_TRANSLATE_GVA_FLAGS
427
{
428
WHvTranslateGvaFlagNone = 0x00000000,
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WHvTranslateGvaFlagValidateRead = 0x00000001,
430
WHvTranslateGvaFlagValidateWrite = 0x00000002,
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WHvTranslateGvaFlagValidateExecute = 0x00000004,
432
WHvTranslateGvaFlagPrivilegeExempt = 0x00000008,
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WHvTranslateGvaFlagSetPageTableBits = 0x00000010
434
} WHV_TRANSLATE_GVA_FLAGS;
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436
DEFINE_ENUM_FLAG_OPERATORS(WHV_TRANSLATE_GVA_FLAGS);
437
438
//
439
// Result of an attempt to translate a guest virtual address
440
//
441
typedef enum WHV_TRANSLATE_GVA_RESULT_CODE
442
{
443
WHvTranslateGvaResultSuccess = 0,
444
445
// Translation failures
446
WHvTranslateGvaResultPageNotPresent = 1,
447
WHvTranslateGvaResultPrivilegeViolation = 2,
448
WHvTranslateGvaResultInvalidPageTableFlags = 3,
449
450
// GPA access failures
451
WHvTranslateGvaResultGpaUnmapped = 4,
452
WHvTranslateGvaResultGpaNoReadAccess = 5,
453
WHvTranslateGvaResultGpaNoWriteAccess = 6,
454
WHvTranslateGvaResultGpaIllegalOverlayAccess = 7,
455
WHvTranslateGvaResultIntercept = 8
456
} WHV_TRANSLATE_GVA_RESULT_CODE;
457
458
//
459
// Output buffer of WHvTranslateGva
460
//
461
typedef struct WHV_TRANSLATE_GVA_RESULT
462
{
463
WHV_TRANSLATE_GVA_RESULT_CODE ResultCode;
464
UINT32 Reserved;
465
} WHV_TRANSLATE_GVA_RESULT;
466
467
//
468
// Virtual Processor Register Definitions
469
//
470
typedef enum WHV_REGISTER_NAME
471
{
472
// X64 General purpose registers
473
WHvX64RegisterRax = 0x00000000,
474
WHvX64RegisterRcx = 0x00000001,
475
WHvX64RegisterRdx = 0x00000002,
476
WHvX64RegisterRbx = 0x00000003,
477
WHvX64RegisterRsp = 0x00000004,
478
WHvX64RegisterRbp = 0x00000005,
479
WHvX64RegisterRsi = 0x00000006,
480
WHvX64RegisterRdi = 0x00000007,
481
WHvX64RegisterR8 = 0x00000008,
482
WHvX64RegisterR9 = 0x00000009,
483
WHvX64RegisterR10 = 0x0000000A,
484
WHvX64RegisterR11 = 0x0000000B,
485
WHvX64RegisterR12 = 0x0000000C,
486
WHvX64RegisterR13 = 0x0000000D,
487
WHvX64RegisterR14 = 0x0000000E,
488
WHvX64RegisterR15 = 0x0000000F,
489
WHvX64RegisterRip = 0x00000010,
490
WHvX64RegisterRflags = 0x00000011,
491
492
// X64 Segment registers
493
WHvX64RegisterEs = 0x00000012,
494
WHvX64RegisterCs = 0x00000013,
495
WHvX64RegisterSs = 0x00000014,
496
WHvX64RegisterDs = 0x00000015,
497
WHvX64RegisterFs = 0x00000016,
498
WHvX64RegisterGs = 0x00000017,
499
WHvX64RegisterLdtr = 0x00000018,
500
WHvX64RegisterTr = 0x00000019,
501
502
// X64 Table registers
503
WHvX64RegisterIdtr = 0x0000001A,
504
WHvX64RegisterGdtr = 0x0000001B,
505
506
// X64 Control Registers
507
WHvX64RegisterCr0 = 0x0000001C,
508
WHvX64RegisterCr2 = 0x0000001D,
509
WHvX64RegisterCr3 = 0x0000001E,
510
WHvX64RegisterCr4 = 0x0000001F,
511
WHvX64RegisterCr8 = 0x00000020,
512
513
// X64 Debug Registers
514
WHvX64RegisterDr0 = 0x00000021,
515
WHvX64RegisterDr1 = 0x00000022,
516
WHvX64RegisterDr2 = 0x00000023,
517
WHvX64RegisterDr3 = 0x00000024,
518
WHvX64RegisterDr6 = 0x00000025,
519
WHvX64RegisterDr7 = 0x00000026,
520
521
// X64 Extended Control Registers
522
WHvX64RegisterXCr0 = 0x00000027,
523
524
// X64 Floating Point and Vector Registers
525
WHvX64RegisterXmm0 = 0x00001000,
526
WHvX64RegisterXmm1 = 0x00001001,
527
WHvX64RegisterXmm2 = 0x00001002,
528
WHvX64RegisterXmm3 = 0x00001003,
529
WHvX64RegisterXmm4 = 0x00001004,
530
WHvX64RegisterXmm5 = 0x00001005,
531
WHvX64RegisterXmm6 = 0x00001006,
532
WHvX64RegisterXmm7 = 0x00001007,
533
WHvX64RegisterXmm8 = 0x00001008,
534
WHvX64RegisterXmm9 = 0x00001009,
535
WHvX64RegisterXmm10 = 0x0000100A,
536
WHvX64RegisterXmm11 = 0x0000100B,
537
WHvX64RegisterXmm12 = 0x0000100C,
538
WHvX64RegisterXmm13 = 0x0000100D,
539
WHvX64RegisterXmm14 = 0x0000100E,
540
WHvX64RegisterXmm15 = 0x0000100F,
541
WHvX64RegisterFpMmx0 = 0x00001010,
542
WHvX64RegisterFpMmx1 = 0x00001011,
543
WHvX64RegisterFpMmx2 = 0x00001012,
544
WHvX64RegisterFpMmx3 = 0x00001013,
545
WHvX64RegisterFpMmx4 = 0x00001014,
546
WHvX64RegisterFpMmx5 = 0x00001015,
547
WHvX64RegisterFpMmx6 = 0x00001016,
548
WHvX64RegisterFpMmx7 = 0x00001017,
549
WHvX64RegisterFpControlStatus = 0x00001018,
550
WHvX64RegisterXmmControlStatus = 0x00001019,
551
552
// X64 MSRs
553
WHvX64RegisterTsc = 0x00002000,
554
WHvX64RegisterEfer = 0x00002001,
555
WHvX64RegisterKernelGsBase = 0x00002002,
556
WHvX64RegisterApicBase = 0x00002003,
557
WHvX64RegisterPat = 0x00002004,
558
WHvX64RegisterSysenterCs = 0x00002005,
559
WHvX64RegisterSysenterEip = 0x00002006,
560
WHvX64RegisterSysenterEsp = 0x00002007,
561
WHvX64RegisterStar = 0x00002008,
562
WHvX64RegisterLstar = 0x00002009,
563
WHvX64RegisterCstar = 0x0000200A,
564
WHvX64RegisterSfmask = 0x0000200B,
565
WHvX64RegisterInitialApicId = 0x0000200C,
566
567
WHvX64RegisterMsrMtrrCap = 0x0000200D,
568
WHvX64RegisterMsrMtrrDefType = 0x0000200E,
569
570
WHvX64RegisterMsrMtrrPhysBase0 = 0x00002010,
571
WHvX64RegisterMsrMtrrPhysBase1 = 0x00002011,
572
WHvX64RegisterMsrMtrrPhysBase2 = 0x00002012,
573
WHvX64RegisterMsrMtrrPhysBase3 = 0x00002013,
574
WHvX64RegisterMsrMtrrPhysBase4 = 0x00002014,
575
WHvX64RegisterMsrMtrrPhysBase5 = 0x00002015,
576
WHvX64RegisterMsrMtrrPhysBase6 = 0x00002016,
577
WHvX64RegisterMsrMtrrPhysBase7 = 0x00002017,
578
WHvX64RegisterMsrMtrrPhysBase8 = 0x00002018,
579
WHvX64RegisterMsrMtrrPhysBase9 = 0x00002019,
580
WHvX64RegisterMsrMtrrPhysBaseA = 0x0000201A,
581
WHvX64RegisterMsrMtrrPhysBaseB = 0x0000201B,
582
WHvX64RegisterMsrMtrrPhysBaseC = 0x0000201C,
583
WHvX64RegisterMsrMtrrPhysBaseD = 0x0000201D,
584
WHvX64RegisterMsrMtrrPhysBaseE = 0x0000201E,
585
WHvX64RegisterMsrMtrrPhysBaseF = 0x0000201F,
586
587
WHvX64RegisterMsrMtrrPhysMask0 = 0x00002040,
588
WHvX64RegisterMsrMtrrPhysMask1 = 0x00002041,
589
WHvX64RegisterMsrMtrrPhysMask2 = 0x00002042,
590
WHvX64RegisterMsrMtrrPhysMask3 = 0x00002043,
591
WHvX64RegisterMsrMtrrPhysMask4 = 0x00002044,
592
WHvX64RegisterMsrMtrrPhysMask5 = 0x00002045,
593
WHvX64RegisterMsrMtrrPhysMask6 = 0x00002046,
594
WHvX64RegisterMsrMtrrPhysMask7 = 0x00002047,
595
WHvX64RegisterMsrMtrrPhysMask8 = 0x00002048,
596
WHvX64RegisterMsrMtrrPhysMask9 = 0x00002049,
597
WHvX64RegisterMsrMtrrPhysMaskA = 0x0000204A,
598
WHvX64RegisterMsrMtrrPhysMaskB = 0x0000204B,
599
WHvX64RegisterMsrMtrrPhysMaskC = 0x0000204C,
600
WHvX64RegisterMsrMtrrPhysMaskD = 0x0000204D,
601
WHvX64RegisterMsrMtrrPhysMaskE = 0x0000204E,
602
WHvX64RegisterMsrMtrrPhysMaskF = 0x0000204F,
603
604
WHvX64RegisterMsrMtrrFix64k00000 = 0x00002070,
605
WHvX64RegisterMsrMtrrFix16k80000 = 0x00002071,
606
WHvX64RegisterMsrMtrrFix16kA0000 = 0x00002072,
607
WHvX64RegisterMsrMtrrFix4kC0000 = 0x00002073,
608
WHvX64RegisterMsrMtrrFix4kC8000 = 0x00002074,
609
WHvX64RegisterMsrMtrrFix4kD0000 = 0x00002075,
610
WHvX64RegisterMsrMtrrFix4kD8000 = 0x00002076,
611
WHvX64RegisterMsrMtrrFix4kE0000 = 0x00002077,
612
WHvX64RegisterMsrMtrrFix4kE8000 = 0x00002078,
613
WHvX64RegisterMsrMtrrFix4kF0000 = 0x00002079,
614
WHvX64RegisterMsrMtrrFix4kF8000 = 0x0000207A,
615
616
WHvX64RegisterTscAux = 0x0000207B,
617
WHvX64RegisterSpecCtrl = 0x00002084,
618
WHvX64RegisterPredCmd = 0x00002085,
619
WHvX64RegisterTscVirtualOffset = 0x00002087,
620
621
// APIC state (also accessible via WHv(Get/Set)VirtualProcessorInterruptControllerState)
622
WHvX64RegisterApicId = 0x00003002,
623
WHvX64RegisterApicVersion = 0x00003003,
624
625
// Interrupt / Event Registers
626
WHvRegisterPendingInterruption = 0x80000000,
627
WHvRegisterInterruptState = 0x80000001,
628
WHvRegisterPendingEvent = 0x80000002,
629
WHvX64RegisterDeliverabilityNotifications = 0x80000004,
630
WHvRegisterInternalActivityState = 0x80000005,
631
WHvX64RegisterPendingDebugException = 0x80000006,
632
633
} WHV_REGISTER_NAME;
634
635
typedef union DECLSPEC_ALIGN(16) WHV_UINT128
636
{
637
struct
638
{
639
UINT64 Low64;
640
UINT64 High64;
641
};
642
643
UINT32 Dword[4];
644
} WHV_UINT128;
645
646
typedef union WHV_X64_FP_REGISTER
647
{
648
struct
649
{
650
UINT64 Mantissa;
651
UINT64 BiasedExponent:15;
652
UINT64 Sign:1;
653
UINT64 Reserved:48;
654
};
655
656
WHV_UINT128 AsUINT128;
657
} WHV_X64_FP_REGISTER;
658
659
typedef union WHV_X64_FP_CONTROL_STATUS_REGISTER
660
{
661
struct
662
{
663
UINT16 FpControl;
664
UINT16 FpStatus;
665
UINT8 FpTag;
666
UINT8 Reserved;
667
UINT16 LastFpOp;
668
union
669
{
670
// Long Mode
671
UINT64 LastFpRip;
672
673
// 32 Bit Mode
674
struct
675
{
676
UINT32 LastFpEip;
677
UINT16 LastFpCs;
678
UINT16 Reserved2;
679
};
680
};
681
};
682
683
WHV_UINT128 AsUINT128;
684
} WHV_X64_FP_CONTROL_STATUS_REGISTER;
685
686
typedef union WHV_X64_XMM_CONTROL_STATUS_REGISTER
687
{
688
struct
689
{
690
union
691
{
692
// Long Mode
693
UINT64 LastFpRdp;
694
695
// 32 Bit Mode
696
struct
697
{
698
UINT32 LastFpDp;
699
UINT16 LastFpDs;
700
UINT16 Reserved;
701
};
702
};
703
UINT32 XmmStatusControl;
704
UINT32 XmmStatusControlMask;
705
};
706
707
WHV_UINT128 AsUINT128;
708
} WHV_X64_XMM_CONTROL_STATUS_REGISTER;
709
710
typedef struct WHV_X64_SEGMENT_REGISTER
711
{
712
UINT64 Base;
713
UINT32 Limit;
714
UINT16 Selector;
715
716
union
717
{
718
struct
719
{
720
UINT16 SegmentType:4;
721
UINT16 NonSystemSegment:1;
722
UINT16 DescriptorPrivilegeLevel:2;
723
UINT16 Present:1;
724
UINT16 Reserved:4;
725
UINT16 Available:1;
726
UINT16 Long:1;
727
UINT16 Default:1;
728
UINT16 Granularity:1;
729
};
730
731
UINT16 Attributes;
732
};
733
} WHV_X64_SEGMENT_REGISTER;
734
735
typedef struct WHV_X64_TABLE_REGISTER
736
{
737
UINT16 Pad[3];
738
UINT16 Limit;
739
UINT64 Base;
740
} WHV_X64_TABLE_REGISTER;
741
742
typedef union WHV_X64_INTERRUPT_STATE_REGISTER
743
{
744
struct
745
{
746
UINT64 InterruptShadow:1;
747
UINT64 NmiMasked:1;
748
UINT64 Reserved:62;
749
};
750
751
UINT64 AsUINT64;
752
} WHV_X64_INTERRUPT_STATE_REGISTER;
753
754
typedef union WHV_X64_PENDING_INTERRUPTION_REGISTER
755
{
756
struct
757
{
758
UINT32 InterruptionPending:1;
759
UINT32 InterruptionType:3; // WHV_X64_PENDING_INTERRUPTION_TYPE
760
UINT32 DeliverErrorCode:1;
761
UINT32 InstructionLength:4;
762
UINT32 NestedEvent:1;
763
UINT32 Reserved:6;
764
UINT32 InterruptionVector:16;
765
UINT32 ErrorCode;
766
};
767
768
UINT64 AsUINT64;
769
} WHV_X64_PENDING_INTERRUPTION_REGISTER;
770
771
C_ASSERT(sizeof(WHV_X64_PENDING_INTERRUPTION_REGISTER) == sizeof(UINT64));
772
773
typedef union WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER
774
{
775
struct
776
{
777
UINT64 NmiNotification:1;
778
UINT64 InterruptNotification:1;
779
UINT64 InterruptPriority:4;
780
UINT64 Reserved:58;
781
};
782
783
UINT64 AsUINT64;
784
} WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER;
785
786
C_ASSERT(sizeof(WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER) == sizeof(UINT64));
787
788
789
typedef enum WHV_X64_PENDING_EVENT_TYPE
790
{
791
WHvX64PendingEventException = 0,
792
WHvX64PendingEventExtInt = 5,
793
} WHV_X64_PENDING_EVENT_TYPE;
794
795
typedef union WHV_X64_PENDING_EXCEPTION_EVENT
796
{
797
struct
798
{
799
UINT32 EventPending : 1;
800
UINT32 EventType : 3; // Must be WHvX64PendingEventException
801
UINT32 Reserved0 : 4;
802
803
UINT32 DeliverErrorCode : 1;
804
UINT32 Reserved1 : 7;
805
UINT32 Vector : 16;
806
UINT32 ErrorCode;
807
UINT64 ExceptionParameter;
808
};
809
810
WHV_UINT128 AsUINT128;
811
} WHV_X64_PENDING_EXCEPTION_EVENT;
812
813
C_ASSERT(sizeof(WHV_X64_PENDING_EXCEPTION_EVENT) == sizeof(WHV_UINT128));
814
815
typedef union WHV_X64_PENDING_EXT_INT_EVENT
816
{
817
struct
818
{
819
UINT64 EventPending : 1;
820
UINT64 EventType : 3; // Must be WHvX64PendingEventExtInt
821
UINT64 Reserved0 : 4;
822
UINT64 Vector : 8;
823
UINT64 Reserved1 : 48;
824
825
UINT64 Reserved2;
826
};
827
828
WHV_UINT128 AsUINT128;
829
} WHV_X64_PENDING_EXT_INT_EVENT;
830
831
C_ASSERT(sizeof(WHV_X64_PENDING_EXT_INT_EVENT) == sizeof(WHV_UINT128));
832
833
typedef union WHV_INTERNAL_ACTIVITY_REGISTER
834
{
835
struct
836
{
837
UINT64 StartupSuspend : 1;
838
UINT64 HaltSuspend : 1;
839
UINT64 IdleSuspend : 1;
840
UINT64 Reserved:61;
841
};
842
843
UINT64 AsUINT64;
844
} WHV_INTERNAL_ACTIVITY_REGISTER;
845
846
C_ASSERT(sizeof(WHV_INTERNAL_ACTIVITY_REGISTER) == sizeof(UINT64));
847
848
typedef union WHV_X64_PENDING_DEBUG_EXCEPTION
849
{
850
UINT64 AsUINT64;
851
852
struct
853
{
854
UINT64 Breakpoint0 : 1;
855
UINT64 Breakpoint1 : 1;
856
UINT64 Breakpoint2 : 1;
857
UINT64 Breakpoint3 : 1;
858
UINT64 SingleStep : 1;
859
UINT64 Reserved0 : 59;
860
};
861
862
} WHV_X64_PENDING_DEBUG_EXCEPTION;
863
864
C_ASSERT(sizeof(WHV_X64_PENDING_DEBUG_EXCEPTION) == sizeof(UINT64));
865
866
//
867
// Register values
868
//
869
typedef union WHV_REGISTER_VALUE
870
{
871
WHV_UINT128 Reg128;
872
UINT64 Reg64;
873
UINT32 Reg32;
874
UINT16 Reg16;
875
UINT8 Reg8;
876
WHV_X64_FP_REGISTER Fp;
877
WHV_X64_FP_CONTROL_STATUS_REGISTER FpControlStatus;
878
WHV_X64_XMM_CONTROL_STATUS_REGISTER XmmControlStatus;
879
WHV_X64_SEGMENT_REGISTER Segment;
880
WHV_X64_TABLE_REGISTER Table;
881
WHV_X64_INTERRUPT_STATE_REGISTER InterruptState;
882
WHV_X64_PENDING_INTERRUPTION_REGISTER PendingInterruption;
883
WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER DeliverabilityNotifications;
884
WHV_X64_PENDING_EXCEPTION_EVENT ExceptionEvent;
885
WHV_X64_PENDING_EXT_INT_EVENT ExtIntEvent;
886
WHV_INTERNAL_ACTIVITY_REGISTER InternalActivity;
887
WHV_X64_PENDING_DEBUG_EXCEPTION PendingDebugException;
888
} WHV_REGISTER_VALUE;
889
890
//
891
// Virtual Processor Execution
892
//
893
894
//
895
// Reason for a VM exit
896
//
897
typedef enum WHV_RUN_VP_EXIT_REASON
898
{
899
WHvRunVpExitReasonNone = 0x00000000,
900
901
// Standard exits caused by operations of the virtual processor
902
WHvRunVpExitReasonMemoryAccess = 0x00000001,
903
WHvRunVpExitReasonX64IoPortAccess = 0x00000002,
904
WHvRunVpExitReasonUnrecoverableException = 0x00000004,
905
WHvRunVpExitReasonInvalidVpRegisterValue = 0x00000005,
906
WHvRunVpExitReasonUnsupportedFeature = 0x00000006,
907
WHvRunVpExitReasonX64InterruptWindow = 0x00000007,
908
WHvRunVpExitReasonX64Halt = 0x00000008,
909
WHvRunVpExitReasonX64ApicEoi = 0x00000009,
910
911
// Additional exits that can be configured through partition properties
912
WHvRunVpExitReasonX64MsrAccess = 0x00001000,
913
WHvRunVpExitReasonX64Cpuid = 0x00001001,
914
WHvRunVpExitReasonException = 0x00001002,
915
WHvRunVpExitReasonX64Rdtsc = 0x00001003,
916
WHvRunVpExitReasonX64ApicSmiTrap = 0x00001004,
917
WHvRunVpExitReasonHypercall = 0x00001005,
918
WHvRunVpExitReasonX64ApicInitSipiTrap = 0x00001006,
919
920
// Exits caused by the host
921
WHvRunVpExitReasonCanceled = 0x00002001,
922
} WHV_RUN_VP_EXIT_REASON;
923
924
//
925
// Execution state of the virtual processor
926
//
927
typedef union WHV_X64_VP_EXECUTION_STATE
928
{
929
struct
930
{
931
UINT16 Cpl : 2;
932
UINT16 Cr0Pe : 1;
933
UINT16 Cr0Am : 1;
934
UINT16 EferLma : 1;
935
UINT16 DebugActive : 1;
936
UINT16 InterruptionPending : 1;
937
UINT16 Reserved0 : 5;
938
UINT16 InterruptShadow : 1;
939
UINT16 Reserved1 : 3;
940
};
941
942
UINT16 AsUINT16;
943
} WHV_X64_VP_EXECUTION_STATE;
944
945
C_ASSERT(sizeof(WHV_X64_VP_EXECUTION_STATE) == sizeof(UINT16));
946
947
//
948
// Execution context of a virtual processor at the time of an exit
949
//
950
typedef struct WHV_VP_EXIT_CONTEXT
951
{
952
WHV_X64_VP_EXECUTION_STATE ExecutionState;
953
UINT8 InstructionLength : 4;
954
UINT8 Cr8 : 4;
955
UINT8 Reserved;
956
UINT32 Reserved2;
957
WHV_X64_SEGMENT_REGISTER Cs;
958
UINT64 Rip;
959
UINT64 Rflags;
960
} WHV_VP_EXIT_CONTEXT;
961
962
//
963
// Context data for a VM exit caused by a memory access (WHvRunVpExitReasonMemoryAccess)
964
//
965
typedef enum WHV_MEMORY_ACCESS_TYPE
966
{
967
WHvMemoryAccessRead = 0,
968
WHvMemoryAccessWrite = 1,
969
WHvMemoryAccessExecute = 2
970
} WHV_MEMORY_ACCESS_TYPE;
971
972
typedef union WHV_MEMORY_ACCESS_INFO
973
{
974
struct {
975
UINT32 AccessType : 2; // WHV_MEMORY_ACCESS_TYPE
976
UINT32 GpaUnmapped : 1;
977
UINT32 GvaValid : 1;
978
UINT32 Reserved : 28;
979
};
980
981
UINT32 AsUINT32;
982
} WHV_MEMORY_ACCESS_INFO;
983
984
typedef struct WHV_MEMORY_ACCESS_CONTEXT
985
{
986
// Context of the virtual processor
987
UINT8 InstructionByteCount;
988
UINT8 Reserved[3];
989
UINT8 InstructionBytes[16];
990
991
// Memory access info
992
WHV_MEMORY_ACCESS_INFO AccessInfo;
993
WHV_GUEST_PHYSICAL_ADDRESS Gpa;
994
WHV_GUEST_VIRTUAL_ADDRESS Gva;
995
} WHV_MEMORY_ACCESS_CONTEXT;
996
997
//
998
// Context data for an exit caused by an I/O port access (WHvRunVpExitReasonX64IOPortAccess)
999
//
1000
typedef union WHV_X64_IO_PORT_ACCESS_INFO
1001
{
1002
struct
1003
{
1004
UINT32 IsWrite : 1;
1005
UINT32 AccessSize: 3;
1006
UINT32 StringOp : 1;
1007
UINT32 RepPrefix : 1;
1008
UINT32 Reserved : 26;
1009
};
1010
1011
UINT32 AsUINT32;
1012
} WHV_X64_IO_PORT_ACCESS_INFO;
1013
1014
C_ASSERT(sizeof(WHV_X64_IO_PORT_ACCESS_INFO) == sizeof(UINT32));
1015
1016
typedef struct WHV_X64_IO_PORT_ACCESS_CONTEXT
1017
{
1018
// Context of the virtual processor
1019
UINT8 InstructionByteCount;
1020
UINT8 Reserved[3];
1021
UINT8 InstructionBytes[16];
1022
1023
// I/O port access info
1024
WHV_X64_IO_PORT_ACCESS_INFO AccessInfo;
1025
UINT16 PortNumber;
1026
UINT16 Reserved2[3];
1027
UINT64 Rax;
1028
UINT64 Rcx;
1029
UINT64 Rsi;
1030
UINT64 Rdi;
1031
WHV_X64_SEGMENT_REGISTER Ds;
1032
WHV_X64_SEGMENT_REGISTER Es;
1033
} WHV_X64_IO_PORT_ACCESS_CONTEXT;
1034
1035
//
1036
// Context data for an exit caused by an MSR access (WHvRunVpExitReasonX64MSRAccess)
1037
//
1038
typedef union WHV_X64_MSR_ACCESS_INFO
1039
{
1040
struct
1041
{
1042
UINT32 IsWrite : 1;
1043
UINT32 Reserved : 31;
1044
};
1045
1046
UINT32 AsUINT32;
1047
} WHV_X64_MSR_ACCESS_INFO;
1048
1049
C_ASSERT(sizeof(WHV_X64_MSR_ACCESS_INFO) == sizeof(UINT32));
1050
1051
typedef struct WHV_X64_MSR_ACCESS_CONTEXT
1052
{
1053
// MSR access info
1054
WHV_X64_MSR_ACCESS_INFO AccessInfo;
1055
UINT32 MsrNumber;
1056
UINT64 Rax;
1057
UINT64 Rdx;
1058
} WHV_X64_MSR_ACCESS_CONTEXT;
1059
1060
//
1061
// Context data for an exit caused by a CPUID call (WHvRunVpExitReasonX64CPUID)
1062
//
1063
typedef struct WHV_X64_CPUID_ACCESS_CONTEXT
1064
{
1065
// CPUID access info
1066
UINT64 Rax;
1067
UINT64 Rcx;
1068
UINT64 Rdx;
1069
UINT64 Rbx;
1070
UINT64 DefaultResultRax;
1071
UINT64 DefaultResultRcx;
1072
UINT64 DefaultResultRdx;
1073
UINT64 DefaultResultRbx;
1074
} WHV_X64_CPUID_ACCESS_CONTEXT;
1075
1076
//
1077
// Context data for an exit caused by an exception generated by the virtual processor
1078
// (WHvRunVpExitReasonException)
1079
//
1080
typedef union WHV_VP_EXCEPTION_INFO
1081
{
1082
struct
1083
{
1084
UINT32 ErrorCodeValid : 1;
1085
UINT32 SoftwareException : 1;
1086
UINT32 Reserved : 30;
1087
};
1088
1089
UINT32 AsUINT32;
1090
} WHV_VP_EXCEPTION_INFO;
1091
1092
C_ASSERT(sizeof(WHV_VP_EXCEPTION_INFO) == sizeof(UINT32));
1093
1094
typedef struct WHV_VP_EXCEPTION_CONTEXT
1095
{
1096
UINT8 InstructionByteCount;
1097
UINT8 Reserved[3];
1098
UINT8 InstructionBytes[16];
1099
1100
// Exception info
1101
WHV_VP_EXCEPTION_INFO ExceptionInfo;
1102
UINT8 ExceptionType; // WHV_EXCEPTION_TYPE
1103
UINT8 Reserved2[3];
1104
UINT32 ErrorCode;
1105
UINT64 ExceptionParameter;
1106
} WHV_VP_EXCEPTION_CONTEXT;
1107
1108
//
1109
// Context data for an exit caused by the use of an unsupported processor feature
1110
// (WHvRunVpExitReasonUnsupportedFeature)
1111
//
1112
typedef enum WHV_X64_UNSUPPORTED_FEATURE_CODE
1113
{
1114
WHvUnsupportedFeatureIntercept = 1,
1115
WHvUnsupportedFeatureTaskSwitchTss = 2
1116
} WHV_X64_UNSUPPORTED_FEATURE_CODE;
1117
1118
typedef struct WHV_X64_UNSUPPORTED_FEATURE_CONTEXT
1119
{
1120
WHV_X64_UNSUPPORTED_FEATURE_CODE FeatureCode;
1121
UINT32 Reserved;
1122
UINT64 FeatureParameter;
1123
} WHV_X64_UNSUPPORTED_FEATURE_CONTEXT;
1124
1125
//
1126
// Context data for an exit caused by a cancellation from the host (WHvRunVpExitReasonCanceled)
1127
//
1128
typedef enum WHV_RUN_VP_CANCEL_REASON
1129
{
1130
WHvRunVpCancelReasonUser = 0 // Execution canceled by WHvCancelRunVirtualProcessor
1131
} WHV_RUN_VP_CANCEL_REASON;
1132
1133
//
1134
// Alias for non-standard capitalization found in earlier versions of the header
1135
//
1136
#define WhvRunVpCancelReasonUser WHvRunVpCancelReasonUser
1137
1138
typedef struct WHV_RUN_VP_CANCELED_CONTEXT
1139
{
1140
WHV_RUN_VP_CANCEL_REASON CancelReason;
1141
} WHV_RUN_VP_CANCELED_CONTEXT;
1142
1143
//
1144
// Context data for an exit caused by an interrupt delivery window cancellation from the host
1145
// (WHvRunVpExitReasonX64InterruptWindow)
1146
//
1147
typedef enum WHV_X64_PENDING_INTERRUPTION_TYPE
1148
{
1149
WHvX64PendingInterrupt = 0,
1150
WHvX64PendingNmi = 2,
1151
WHvX64PendingException = 3
1152
} WHV_X64_PENDING_INTERRUPTION_TYPE, *PWHV_X64_PENDING_INTERRUPTION_TYPE;
1153
1154
typedef struct WHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT
1155
{
1156
WHV_X64_PENDING_INTERRUPTION_TYPE DeliverableType;
1157
} WHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT, *PWHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT;
1158
1159
//
1160
// Context data for an exit caused by an APIC EOI of a level-triggered
1161
// interrupt (WHvRunVpExitReasonX64ApicEoi)
1162
//
1163
typedef struct WHV_X64_APIC_EOI_CONTEXT
1164
{
1165
UINT32 InterruptVector;
1166
} WHV_X64_APIC_EOI_CONTEXT;
1167
1168
//
1169
// Context data for an exit caused by a rdtsc(p) instruction (WHvRunVpExitReasonX64Rdtsc)
1170
//
1171
typedef union WHV_X64_RDTSC_INFO
1172
{
1173
struct
1174
{
1175
UINT64 IsRdtscp:1;
1176
UINT64 Reserved:63;
1177
};
1178
1179
UINT64 AsUINT64;
1180
} WHV_X64_RDTSC_INFO;
1181
1182
typedef struct WHV_X64_RDTSC_CONTEXT
1183
{
1184
UINT64 TscAux;
1185
UINT64 VirtualOffset;
1186
UINT64 Tsc;
1187
UINT64 ReferenceTime;
1188
WHV_X64_RDTSC_INFO RdtscInfo;
1189
} WHV_X64_RDTSC_CONTEXT;
1190
1191
//
1192
// Context data for an exit caused by an APIC SMI (WHvRunVpExitReasonX64ApicSmiTrap)
1193
//
1194
typedef struct WHV_X64_APIC_SMI_CONTEXT
1195
{
1196
UINT64 ApicIcr;
1197
} WHV_X64_APIC_SMI_CONTEXT;
1198
1199
//
1200
// Context data for an exit caused by a hypercall (WHvRunVpExitReasonHypercall)
1201
//
1202
1203
#define WHV_HYPERCALL_CONTEXT_MAX_XMM_REGISTERS 6
1204
1205
typedef struct _WHV_HYPERCALL_CONTEXT
1206
{
1207
UINT64 Rax;
1208
UINT64 Rbx;
1209
UINT64 Rcx;
1210
UINT64 Rdx;
1211
UINT64 R8;
1212
UINT64 Rsi;
1213
UINT64 Rdi;
1214
UINT64 Reserved0;
1215
WHV_UINT128 XmmRegisters[WHV_HYPERCALL_CONTEXT_MAX_XMM_REGISTERS];
1216
UINT64 Reserved1[2];
1217
} WHV_HYPERCALL_CONTEXT, *PWHV_HYPERCALL_CONTEXT;
1218
1219
//
1220
// Context data for an exit caused by an APIC INIT SIPI (WHvRunVpExitReasonX64ApicInitSipiTrap)
1221
//
1222
typedef struct WHV_X64_APIC_INIT_SIPI_CONTEXT
1223
{
1224
UINT64 ApicIcr;
1225
} WHV_X64_APIC_INIT_SIPI_CONTEXT;
1226
1227
// WHvRunVirtualProcessor output buffer
1228
typedef struct WHV_RUN_VP_EXIT_CONTEXT
1229
{
1230
WHV_RUN_VP_EXIT_REASON ExitReason;
1231
UINT32 Reserved;
1232
WHV_VP_EXIT_CONTEXT VpContext;
1233
1234
union
1235
{
1236
WHV_MEMORY_ACCESS_CONTEXT MemoryAccess;
1237
WHV_X64_IO_PORT_ACCESS_CONTEXT IoPortAccess;
1238
WHV_X64_MSR_ACCESS_CONTEXT MsrAccess;
1239
WHV_X64_CPUID_ACCESS_CONTEXT CpuidAccess;
1240
WHV_VP_EXCEPTION_CONTEXT VpException;
1241
WHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT InterruptWindow;
1242
WHV_X64_UNSUPPORTED_FEATURE_CONTEXT UnsupportedFeature;
1243
WHV_RUN_VP_CANCELED_CONTEXT CancelReason;
1244
WHV_X64_APIC_EOI_CONTEXT ApicEoi;
1245
WHV_X64_RDTSC_CONTEXT ReadTsc;
1246
WHV_X64_APIC_SMI_CONTEXT ApicSmi;
1247
WHV_HYPERCALL_CONTEXT Hypercall;
1248
WHV_X64_APIC_INIT_SIPI_CONTEXT ApicInitSipi;
1249
};
1250
} WHV_RUN_VP_EXIT_CONTEXT;
1251
1252
typedef enum WHV_INTERRUPT_TYPE
1253
{
1254
WHvX64InterruptTypeFixed = 0,
1255
WHvX64InterruptTypeLowestPriority = 1,
1256
WHvX64InterruptTypeNmi = 4,
1257
WHvX64InterruptTypeInit = 5,
1258
WHvX64InterruptTypeSipi = 6,
1259
WHvX64InterruptTypeLocalInt1 = 9,
1260
} WHV_INTERRUPT_TYPE;
1261
1262
typedef enum WHV_INTERRUPT_DESTINATION_MODE
1263
{
1264
WHvX64InterruptDestinationModePhysical,
1265
WHvX64InterruptDestinationModeLogical,
1266
} WHV_INTERRUPT_DESTINATION_MODE;
1267
1268
typedef enum WHV_INTERRUPT_TRIGGER_MODE
1269
{
1270
WHvX64InterruptTriggerModeEdge,
1271
WHvX64InterruptTriggerModeLevel,
1272
} WHV_INTERRUPT_TRIGGER_MODE;
1273
1274
typedef struct WHV_INTERRUPT_CONTROL
1275
{
1276
UINT64 Type : 8; // WHV_INTERRUPT_TYPE
1277
UINT64 DestinationMode : 4; // WHV_INTERRUPT_DESTINATION_MODE
1278
UINT64 TriggerMode : 4; // WHV_INTERRUPT_TRIGGER_MODE
1279
UINT64 Reserved : 48;
1280
UINT32 Destination;
1281
UINT32 Vector;
1282
} WHV_INTERRUPT_CONTROL;
1283
1284
typedef struct WHV_DOORBELL_MATCH_DATA
1285
{
1286
WHV_GUEST_PHYSICAL_ADDRESS GuestAddress;
1287
UINT64 Value;
1288
UINT32 Length;
1289
UINT32 MatchOnValue:1;
1290
UINT32 MatchOnLength:1;
1291
UINT32 Reserved:30;
1292
} WHV_DOORBELL_MATCH_DATA;
1293
1294
// WHvGetPartitionCounters types
1295
typedef enum WHV_PARTITION_COUNTER_SET
1296
{
1297
WHvPartitionCounterSetMemory,
1298
} WHV_PARTITION_COUNTER_SET;
1299
1300
typedef struct WHV_PARTITION_MEMORY_COUNTERS
1301
{
1302
UINT64 Mapped4KPageCount;
1303
UINT64 Mapped2MPageCount;
1304
UINT64 Mapped1GPageCount;
1305
} WHV_PARTITION_MEMORY_COUNTERS;
1306
1307
// WHvGetVirtualProcessorCounters types
1308
typedef enum WHV_PROCESSOR_COUNTER_SET
1309
{
1310
WHvProcessorCounterSetRuntime,
1311
WHvProcessorCounterSetIntercepts,
1312
WHvProcessorCounterSetEvents,
1313
WHvProcessorCounterSetApic,
1314
} WHV_PROCESSOR_COUNTER_SET;
1315
1316
typedef struct WHV_PROCESSOR_RUNTIME_COUNTERS
1317
{
1318
UINT64 TotalRuntime100ns;
1319
UINT64 HypervisorRuntime100ns;
1320
} WHV_PROCESSOR_RUNTIME_COUNTERS;
1321
1322
typedef struct WHV_PROCESSOR_INTERCEPT_COUNTER
1323
{
1324
UINT64 Count;
1325
UINT64 Time100ns;
1326
} WHV_PROCESSOR_INTERCEPT_COUNTER;
1327
1328
typedef struct WHV_PROCESSOR_INTERCEPT_COUNTERS
1329
{
1330
WHV_PROCESSOR_INTERCEPT_COUNTER PageInvalidations;
1331
WHV_PROCESSOR_INTERCEPT_COUNTER ControlRegisterAccesses;
1332
WHV_PROCESSOR_INTERCEPT_COUNTER IoInstructions;
1333
WHV_PROCESSOR_INTERCEPT_COUNTER HaltInstructions;
1334
WHV_PROCESSOR_INTERCEPT_COUNTER CpuidInstructions;
1335
WHV_PROCESSOR_INTERCEPT_COUNTER MsrAccesses;
1336
WHV_PROCESSOR_INTERCEPT_COUNTER OtherIntercepts;
1337
WHV_PROCESSOR_INTERCEPT_COUNTER PendingInterrupts;
1338
WHV_PROCESSOR_INTERCEPT_COUNTER EmulatedInstructions;
1339
WHV_PROCESSOR_INTERCEPT_COUNTER DebugRegisterAccesses;
1340
WHV_PROCESSOR_INTERCEPT_COUNTER PageFaultIntercepts;
1341
} WHV_PROCESSOR_ACTIVITY_COUNTERS;
1342
1343
typedef struct WHV_PROCESSOR_EVENT_COUNTERS
1344
{
1345
UINT64 PageFaultCount;
1346
UINT64 ExceptionCount;
1347
UINT64 InterruptCount;
1348
} WHV_PROCESSOR_GUEST_EVENT_COUNTERS;
1349
1350
typedef struct WHV_PROCESSOR_APIC_COUNTERS
1351
{
1352
UINT64 MmioAccessCount;
1353
UINT64 EoiAccessCount;
1354
UINT64 TprAccessCount;
1355
UINT64 SentIpiCount;
1356
UINT64 SelfIpiCount;
1357
} WHV_PROCESSOR_APIC_COUNTERS;
1358
1359
#if defined(_MSC_VER) && (_MSC_VER >= 1200)
1360
#pragma warning(pop)
1361
#endif
1362
1363
#endif // _WINHVAPIDEFS_H_
1364
1365