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GitHub Repository: hrydgard/ppsspp
Path: blob/master/Core/MIPS/ARM/ArmJit.h
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// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include "Common/CPUDetect.h"
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#include "Common/ArmCommon.h"
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#include "Common/ArmEmitter.h"
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#include "Core/MIPS/JitCommon/JitState.h"
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#include "Core/MIPS/JitCommon/JitBlockCache.h"
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#include "Core/MIPS/JitCommon/JitCommon.h"
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#include "Core/MIPS/ARM/ArmRegCache.h"
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#include "Core/MIPS/ARM/ArmRegCacheFPU.h"
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#include "Core/MIPS/MIPSVFPUUtils.h"
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#ifndef offsetof
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#include "stddef.h"
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#endif
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namespace MIPSComp {
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class ArmJit : public ArmGen::ARMXCodeBlock, public JitInterface, public MIPSFrontendInterface {
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public:
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	ArmJit(MIPSState *mipsState);
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	virtual ~ArmJit();
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	void DoState(PointerWrap &p) override;
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	const JitOptions &GetJitOptions() { return jo; }
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	// Compiled ops should ignore delay slots
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	// the compiler will take care of them by itself
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	// OR NOT
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	void Comp_Generic(MIPSOpcode op) override;
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	void RunLoopUntil(u64 globalticks) override;
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	void Compile(u32 em_address) override;	// Compiles a block at current MIPS PC
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	const u8 *GetCrashHandler() const override { return crashHandler; }
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	bool CodeInRange(const u8 *ptr) const override { return IsInSpace(ptr); }
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	bool DescribeCodePtr(const u8 *ptr, std::string &name) override;
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	MIPSOpcode GetOriginalOp(MIPSOpcode op) override;
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	void Comp_RunBlock(MIPSOpcode op) override;
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	void Comp_ReplacementFunc(MIPSOpcode op) override;
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	// Ops
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	void Comp_ITypeMem(MIPSOpcode op) override;
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	void Comp_StoreSync(MIPSOpcode op) override;
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	void Comp_Cache(MIPSOpcode op) override;
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	void Comp_RelBranch(MIPSOpcode op) override;
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	void Comp_RelBranchRI(MIPSOpcode op) override;
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	void Comp_FPUBranch(MIPSOpcode op) override;
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	void Comp_FPULS(MIPSOpcode op) override;
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	void Comp_FPUComp(MIPSOpcode op) override;
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	void Comp_Jump(MIPSOpcode op) override;
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	void Comp_JumpReg(MIPSOpcode op) override;
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	void Comp_Syscall(MIPSOpcode op) override;
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	void Comp_Break(MIPSOpcode op) override;
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	void Comp_IType(MIPSOpcode op) override;
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	void Comp_RType2(MIPSOpcode op) override;
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	void Comp_RType3(MIPSOpcode op) override;
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	void Comp_ShiftType(MIPSOpcode op) override;
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	void Comp_Allegrex(MIPSOpcode op) override;
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	void Comp_Allegrex2(MIPSOpcode op) override;
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	void Comp_VBranch(MIPSOpcode op) override;
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	void Comp_MulDivType(MIPSOpcode op) override;
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	void Comp_Special3(MIPSOpcode op) override;
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	void Comp_FPU3op(MIPSOpcode op) override;
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	void Comp_FPU2op(MIPSOpcode op) override;
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	void Comp_mxc1(MIPSOpcode op) override;
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	void Comp_DoNothing(MIPSOpcode op) override;
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	void Comp_SV(MIPSOpcode op) override;
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	void Comp_SVQ(MIPSOpcode op) override;
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	void Comp_VPFX(MIPSOpcode op) override;
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	void Comp_VVectorInit(MIPSOpcode op) override;
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	void Comp_VMatrixInit(MIPSOpcode op) override;
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	void Comp_VDot(MIPSOpcode op) override;
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	void Comp_VecDo3(MIPSOpcode op) override;
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	void Comp_VV2Op(MIPSOpcode op) override;
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	void Comp_Mftv(MIPSOpcode op) override;
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	void Comp_Vmfvc(MIPSOpcode op) override;
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	void Comp_Vmtvc(MIPSOpcode op) override;
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	void Comp_Vmmov(MIPSOpcode op) override;
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	void Comp_VScl(MIPSOpcode op) override;
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	void Comp_Vmmul(MIPSOpcode op) override;
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	void Comp_Vmscl(MIPSOpcode op) override;
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	void Comp_Vtfm(MIPSOpcode op) override;
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	void Comp_VHdp(MIPSOpcode op) override;
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	void Comp_VCrs(MIPSOpcode op) override;
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	void Comp_VDet(MIPSOpcode op) override;
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	void Comp_Vi2x(MIPSOpcode op) override;
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	void Comp_Vx2i(MIPSOpcode op) override;
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	void Comp_Vf2i(MIPSOpcode op) override;
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	void Comp_Vi2f(MIPSOpcode op) override;
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	void Comp_Vh2f(MIPSOpcode op) override;
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	void Comp_Vcst(MIPSOpcode op) override;
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	void Comp_Vhoriz(MIPSOpcode op) override;
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	void Comp_VRot(MIPSOpcode op) override;
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	void Comp_VIdt(MIPSOpcode op) override;
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	void Comp_Vcmp(MIPSOpcode op) override;
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	void Comp_Vcmov(MIPSOpcode op) override;
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	void Comp_Viim(MIPSOpcode op) override;
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	void Comp_Vfim(MIPSOpcode op) override;
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	void Comp_VCrossQuat(MIPSOpcode op) override;
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	void Comp_Vsgn(MIPSOpcode op) override;
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	void Comp_Vocp(MIPSOpcode op) override;
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	void Comp_ColorConv(MIPSOpcode op) override;
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	void Comp_Vbfy(MIPSOpcode op) override;
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	// Non-NEON: VPFX
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	// NEON implementations of the VFPU ops.
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	void CompNEON_SV(MIPSOpcode op);
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	void CompNEON_SVQ(MIPSOpcode op);
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	void CompNEON_VVectorInit(MIPSOpcode op);
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	void CompNEON_VMatrixInit(MIPSOpcode op);
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	void CompNEON_VDot(MIPSOpcode op);
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	void CompNEON_VecDo3(MIPSOpcode op);
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	void CompNEON_VV2Op(MIPSOpcode op);
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	void CompNEON_Mftv(MIPSOpcode op);
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	void CompNEON_Vmfvc(MIPSOpcode op);
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	void CompNEON_Vmtvc(MIPSOpcode op);
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	void CompNEON_Vmmov(MIPSOpcode op);
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	void CompNEON_VScl(MIPSOpcode op);
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	void CompNEON_Vmmul(MIPSOpcode op);
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	void CompNEON_Vmscl(MIPSOpcode op);
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	void CompNEON_Vtfm(MIPSOpcode op);
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	void CompNEON_VHdp(MIPSOpcode op);
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	void CompNEON_VCrs(MIPSOpcode op);
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	void CompNEON_VDet(MIPSOpcode op);
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	void CompNEON_Vi2x(MIPSOpcode op);
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	void CompNEON_Vx2i(MIPSOpcode op);
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	void CompNEON_Vf2i(MIPSOpcode op);
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	void CompNEON_Vi2f(MIPSOpcode op);
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	void CompNEON_Vh2f(MIPSOpcode op);
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	void CompNEON_Vcst(MIPSOpcode op);
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	void CompNEON_Vhoriz(MIPSOpcode op);
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	void CompNEON_VRot(MIPSOpcode op);
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	void CompNEON_VIdt(MIPSOpcode op);
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	void CompNEON_Vcmp(MIPSOpcode op);
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	void CompNEON_Vcmov(MIPSOpcode op);
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	void CompNEON_Viim(MIPSOpcode op);
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	void CompNEON_Vfim(MIPSOpcode op);
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	void CompNEON_VCrossQuat(MIPSOpcode op);
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	void CompNEON_Vsgn(MIPSOpcode op);
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	void CompNEON_Vocp(MIPSOpcode op);
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	void CompNEON_ColorConv(MIPSOpcode op);
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	void CompNEON_Vbfy(MIPSOpcode op);
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	int Replace_fabsf() override;
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	JitBlockCache *GetBlockCache() override { return &blocks; }
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	JitBlockCacheDebugInterface *GetBlockCacheDebugInterface() override { return &blocks; }
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	std::vector<u32> SaveAndClearEmuHackOps() override { return blocks.SaveAndClearEmuHackOps(); }
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	void RestoreSavedEmuHackOps(std::vector<u32> saved) override { blocks.RestoreSavedEmuHackOps(saved); }
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	void ClearCache() override;
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	void InvalidateCacheAt(u32 em_address, int length = 4) override;
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	void UpdateFCR31() override;
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	void EatPrefix() override { js.EatPrefix(); }
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	const u8 *GetDispatcher() const override {
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		return dispatcher;
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	}
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	bool IsAtDispatchFetch(const u8 *ptr) const override {
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		return ptr == dispatcherFetch;
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	}
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	void LinkBlock(u8 *exitPoint, const u8 *checkedEntry) override;
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	void UnlinkBlock(u8 *checkedEntry, u32 originalAddress) override;
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private:
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	const u8 *DoJit(u32 em_address, JitBlock *b);
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	void GenerateFixedCode();
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	void FlushAll();
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	void FlushPrefixV();
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	u32 GetCompilerPC();
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	void CompileDelaySlot(int flags);
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	void EatInstruction(MIPSOpcode op);
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	void AddContinuedBlock(u32 dest);
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	MIPSOpcode GetOffsetInstruction(int offset);
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	void WriteDownCount(int offset = 0);
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	void WriteDownCountR(ArmGen::ARMReg reg);
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	void RestoreRoundingMode(bool force = false);
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	void ApplyRoundingMode(bool force = false);
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	void UpdateRoundingMode(u32 fcr31 = -1);
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	void MovFromPC(ArmGen::ARMReg r);
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	void MovToPC(ArmGen::ARMReg r);
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	bool ReplaceJalTo(u32 dest);
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	void SaveDowncount();
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	void RestoreDowncount();
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	void WriteExit(u32 destination, int exit_num);
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	void WriteExitDestInR(ArmGen::ARMReg Reg);
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	void WriteSyscallExit();
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	bool CheckJitBreakpoint(u32 addr, int downcountOffset);
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	bool CheckMemoryBreakpoint(int instructionOffset = 0);
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	// Utility compilation functions
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	void BranchFPFlag(MIPSOpcode op, CCFlags cc, bool likely);
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	void BranchVFPUFlag(MIPSOpcode op, CCFlags cc, bool likely);
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	void BranchRSZeroComp(MIPSOpcode op, CCFlags cc, bool andLink, bool likely);
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	void BranchRSRTComp(MIPSOpcode op, CCFlags cc, bool likely);
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	// Utilities to reduce duplicated code
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	void CompImmLogic(MIPSGPReg rs, MIPSGPReg rt, u32 uimm, void (ARMXEmitter::*arith)(ArmGen::ARMReg dst, ArmGen::ARMReg src, ArmGen::Operand2 op2), bool (ARMXEmitter::*tryArithI2R)(ArmGen::ARMReg dst, ArmGen::ARMReg src, u32 val), u32 (*eval)(u32 a, u32 b));
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	void CompType3(MIPSGPReg rd, MIPSGPReg rs, MIPSGPReg rt, void (ARMXEmitter::*arithOp2)(ArmGen::ARMReg dst, ArmGen::ARMReg rm, ArmGen::Operand2 rn), bool (ARMXEmitter::*tryArithI2R)(ArmGen::ARMReg dst, ArmGen::ARMReg rm, u32 val), u32 (*eval)(u32 a, u32 b), bool symmetric = false);
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	void CompShiftImm(MIPSOpcode op, ArmGen::ShiftType shiftType, int sa);
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	void CompShiftVar(MIPSOpcode op, ArmGen::ShiftType shiftType);
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	void CompVrotShuffle(u8 *dregs, int imm, VectorSize sz, bool negSin);
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	void ApplyPrefixST(u8 *vregs, u32 prefix, VectorSize sz);
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	void ApplyPrefixD(const u8 *vregs, VectorSize sz);
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	void GetVectorRegsPrefixS(u8 *regs, VectorSize sz, int vectorReg) {
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		_assert_(js.prefixSFlag & JitState::PREFIX_KNOWN);
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		GetVectorRegs(regs, sz, vectorReg);
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		ApplyPrefixST(regs, js.prefixS, sz);
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	}
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	void GetVectorRegsPrefixT(u8 *regs, VectorSize sz, int vectorReg) {
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		_assert_(js.prefixTFlag & JitState::PREFIX_KNOWN);
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		GetVectorRegs(regs, sz, vectorReg);
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		ApplyPrefixST(regs, js.prefixT, sz);
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	}
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	void GetVectorRegsPrefixD(u8 *regs, VectorSize sz, int vectorReg);
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	// For NEON mappings, it will be easier to deal directly in ARM registers.
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	ArmGen::ARMReg NEONMapPrefixST(int vfpuReg, VectorSize sz, u32 prefix, int mapFlags);
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	ArmGen::ARMReg NEONMapPrefixS(int vfpuReg, VectorSize sz, int mapFlags) {
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		return NEONMapPrefixST(vfpuReg, sz, js.prefixS, mapFlags);
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	}
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	ArmGen::ARMReg NEONMapPrefixT(int vfpuReg, VectorSize sz, int mapFlags) {
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		return NEONMapPrefixST(vfpuReg, sz, js.prefixT, mapFlags);
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	}
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	struct DestARMReg {
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		ArmGen::ARMReg rd;
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		ArmGen::ARMReg backingRd;
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		VectorSize sz;
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		operator ArmGen::ARMReg() const { return rd; }
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	};
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	struct MappedRegs {
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		ArmGen::ARMReg vs;
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		ArmGen::ARMReg vt;
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		DestARMReg vd;
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		bool overlap;
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	};
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	MappedRegs NEONMapDirtyInIn(MIPSOpcode op, VectorSize dsize, VectorSize ssize, VectorSize tsize, bool applyPrefixes = true);
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	MappedRegs NEONMapInIn(MIPSOpcode op, VectorSize ssize, VectorSize tsize, bool applyPrefixes = true);
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	MappedRegs NEONMapDirtyIn(MIPSOpcode op, VectorSize dsize, VectorSize ssize, bool applyPrefixes = true);
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	DestARMReg NEONMapPrefixD(int vfpuReg, VectorSize sz, int mapFlags);
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	void NEONApplyPrefixD(DestARMReg dest);
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	// NEON utils
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	void NEONMaskToSize(ArmGen::ARMReg vs, VectorSize sz);
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	void NEONTranspose4x4(ArmGen::ARMReg cols[4]);
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	// Utils
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	void SetR0ToEffectiveAddress(MIPSGPReg rs, s16 offset);
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	void SetCCAndR0ForSafeAddress(MIPSGPReg rs, s16 offset, ArmGen::ARMReg tempReg, bool reverse = false);
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	void Comp_ITypeMemLR(MIPSOpcode op, bool load);
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	JitBlockCache blocks;
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	JitOptions jo;
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	JitState js;
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	ArmRegCache gpr;
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	ArmRegCacheFPU fpr;
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	MIPSState *mips_;
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	int dontLogBlocks;
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	int logBlocks;
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public:
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	// Code pointers
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	const u8 *enterDispatcher;
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	const u8 *outerLoop;
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	const u8 *outerLoopPCInR0;
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	const u8 *dispatcherCheckCoreState;
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	const u8 *dispatcherPCInR0;
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	const u8 *dispatcher;
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	const u8 *dispatcherFetch;
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	const u8 *dispatcherNoCheck;
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	const u8 *restoreRoundingMode;
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	const u8 *applyRoundingMode;
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	const u8 *crashHandler;
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};
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}	// namespace MIPSComp
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