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nu11secur1ty
GitHub Repository: nu11secur1ty/Kali-Linux
Path: blob/master/ALFA-W1F1/RTL8814AU/hal/hal_com_phycfg.c
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#define _HAL_COM_PHYCFG_C_
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#include <drv_types.h>
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#include <hal_data.h>
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#define PG_TXPWR_1PATH_BYTE_NUM_2G 18
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#define PG_TXPWR_BASE_BYTE_NUM_2G 11
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#define PG_TXPWR_1PATH_BYTE_NUM_5G 24
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#define PG_TXPWR_BASE_BYTE_NUM_5G 14
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#define PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) (((_pg_v) & 0xf0) >> 4)
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#define PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) ((_pg_v) & 0x0f)
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#define PG_TXPWR_MSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_MSB_DIFF_S4BIT(_pg_v))
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#define PG_TXPWR_LSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_LSB_DIFF_S4BIT(_pg_v))
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#define IS_PG_TXPWR_BASE_INVALID(hal_spec, _base) ((_base) > hal_spec->txgi_max)
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#define IS_PG_TXPWR_DIFF_INVALID(_diff) ((_diff) > 7 || (_diff) < -8)
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#define PG_TXPWR_INVALID_BASE 255
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#define PG_TXPWR_INVALID_DIFF 8
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#if !IS_PG_TXPWR_DIFF_INVALID(PG_TXPWR_INVALID_DIFF)
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#error "PG_TXPWR_DIFF definition has problem"
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#endif
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#define PG_TXPWR_SRC_PG_DATA 0
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#define PG_TXPWR_SRC_IC_DEF 1
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#define PG_TXPWR_SRC_DEF 2
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#define PG_TXPWR_SRC_NUM 3
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const char *const _pg_txpwr_src_str[] = {
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"PG_DATA",
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"IC_DEF",
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"DEF",
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"UNKNOWN"
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};
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#define pg_txpwr_src_str(src) (((src) >= PG_TXPWR_SRC_NUM) ? _pg_txpwr_src_str[PG_TXPWR_SRC_NUM] : _pg_txpwr_src_str[(src)])
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#ifndef CONFIG_USE_TSSI
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typedef struct _TxPowerInfo24G {
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u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
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u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
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/* If only one tx, only BW20 and OFDM are used. */
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s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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} TxPowerInfo24G;
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typedef struct _TxPowerInfo5G {
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u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
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/* If only one tx, only BW20, OFDM, BW80 and BW160 are used. */
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s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW80_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW160_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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} TxPowerInfo5G;
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#ifndef DBG_PG_TXPWR_READ
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#define DBG_PG_TXPWR_READ 0
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#endif
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#if DBG_PG_TXPWR_READ
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static void dump_pg_txpwr_info_2g(void *sel, TxPowerInfo24G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt)
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{
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int path, group, tx_idx;
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RTW_PRINT_SEL(sel, "2.4G\n");
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RTW_PRINT_SEL(sel, "CCK-1T base:\n");
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RTW_PRINT_SEL(sel, "%4s ", "");
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for (group = 0; group < MAX_CHNL_GROUP_24G; group++)
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_RTW_PRINT_SEL(sel, "G%02d ", group);
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_RTW_PRINT_SEL(sel, "\n");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
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RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
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for (group = 0; group < MAX_CHNL_GROUP_24G; group++)
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_RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexCCK_Base[path][group]);
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_RTW_PRINT_SEL(sel, "\n");
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}
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RTW_PRINT_SEL(sel, "\n");
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RTW_PRINT_SEL(sel, "CCK diff:\n");
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RTW_PRINT_SEL(sel, "%4s ", "");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
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_RTW_PRINT_SEL(sel, "%dT ", path + 1);
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_RTW_PRINT_SEL(sel, "\n");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
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RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
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for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
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_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->CCK_Diff[path][tx_idx]);
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_RTW_PRINT_SEL(sel, "\n");
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}
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RTW_PRINT_SEL(sel, "\n");
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RTW_PRINT_SEL(sel, "BW40-1S base:\n");
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RTW_PRINT_SEL(sel, "%4s ", "");
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for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++)
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_RTW_PRINT_SEL(sel, "G%02d ", group);
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_RTW_PRINT_SEL(sel, "\n");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
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RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
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for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++)
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_RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexBW40_Base[path][group]);
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_RTW_PRINT_SEL(sel, "\n");
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}
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RTW_PRINT_SEL(sel, "\n");
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RTW_PRINT_SEL(sel, "OFDM diff:\n");
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RTW_PRINT_SEL(sel, "%4s ", "");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
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_RTW_PRINT_SEL(sel, "%dT ", path + 1);
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_RTW_PRINT_SEL(sel, "\n");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
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RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
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for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
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_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->OFDM_Diff[path][tx_idx]);
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_RTW_PRINT_SEL(sel, "\n");
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}
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RTW_PRINT_SEL(sel, "\n");
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RTW_PRINT_SEL(sel, "BW20 diff:\n");
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RTW_PRINT_SEL(sel, "%4s ", "");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
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_RTW_PRINT_SEL(sel, "%dS ", path + 1);
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_RTW_PRINT_SEL(sel, "\n");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
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RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
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for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
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_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW20_Diff[path][tx_idx]);
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_RTW_PRINT_SEL(sel, "\n");
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}
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RTW_PRINT_SEL(sel, "\n");
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RTW_PRINT_SEL(sel, "BW40 diff:\n");
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RTW_PRINT_SEL(sel, "%4s ", "");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
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_RTW_PRINT_SEL(sel, "%dS ", path + 1);
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_RTW_PRINT_SEL(sel, "\n");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
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RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
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for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
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_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW40_Diff[path][tx_idx]);
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_RTW_PRINT_SEL(sel, "\n");
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}
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RTW_PRINT_SEL(sel, "\n");
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}
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static void dump_pg_txpwr_info_5g(void *sel, TxPowerInfo5G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt)
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{
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int path, group, tx_idx;
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RTW_PRINT_SEL(sel, "5G\n");
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RTW_PRINT_SEL(sel, "BW40-1S base:\n");
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RTW_PRINT_SEL(sel, "%4s ", "");
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for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
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_RTW_PRINT_SEL(sel, "G%02d ", group);
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_RTW_PRINT_SEL(sel, "\n");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
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RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
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for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
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_RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexBW40_Base[path][group]);
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_RTW_PRINT_SEL(sel, "\n");
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}
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RTW_PRINT_SEL(sel, "\n");
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RTW_PRINT_SEL(sel, "OFDM diff:\n");
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RTW_PRINT_SEL(sel, "%4s ", "");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
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_RTW_PRINT_SEL(sel, "%dT ", path + 1);
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_RTW_PRINT_SEL(sel, "\n");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
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RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
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for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
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_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->OFDM_Diff[path][tx_idx]);
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_RTW_PRINT_SEL(sel, "\n");
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}
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RTW_PRINT_SEL(sel, "\n");
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RTW_PRINT_SEL(sel, "BW20 diff:\n");
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RTW_PRINT_SEL(sel, "%4s ", "");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
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_RTW_PRINT_SEL(sel, "%dS ", path + 1);
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_RTW_PRINT_SEL(sel, "\n");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
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RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
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for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
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_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW20_Diff[path][tx_idx]);
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_RTW_PRINT_SEL(sel, "\n");
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}
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RTW_PRINT_SEL(sel, "\n");
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RTW_PRINT_SEL(sel, "BW40 diff:\n");
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RTW_PRINT_SEL(sel, "%4s ", "");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
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_RTW_PRINT_SEL(sel, "%dS ", path + 1);
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_RTW_PRINT_SEL(sel, "\n");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
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RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
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for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
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_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW40_Diff[path][tx_idx]);
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_RTW_PRINT_SEL(sel, "\n");
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}
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RTW_PRINT_SEL(sel, "\n");
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RTW_PRINT_SEL(sel, "BW80 diff:\n");
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RTW_PRINT_SEL(sel, "%4s ", "");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
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_RTW_PRINT_SEL(sel, "%dS ", path + 1);
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_RTW_PRINT_SEL(sel, "\n");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
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RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
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for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
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_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW80_Diff[path][tx_idx]);
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_RTW_PRINT_SEL(sel, "\n");
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}
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RTW_PRINT_SEL(sel, "\n");
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RTW_PRINT_SEL(sel, "BW160 diff:\n");
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RTW_PRINT_SEL(sel, "%4s ", "");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
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_RTW_PRINT_SEL(sel, "%dS ", path + 1);
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_RTW_PRINT_SEL(sel, "\n");
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for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
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RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
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for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
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_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW160_Diff[path][tx_idx]);
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_RTW_PRINT_SEL(sel, "\n");
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}
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RTW_PRINT_SEL(sel, "\n");
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}
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#endif /* DBG_PG_TXPWR_READ */
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const struct map_t pg_txpwr_def_info =
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MAP_ENT(0xB8, 1, 0xFF
250
, MAPSEG_ARRAY_ENT(0x10, 168,
251
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE,
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0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
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0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
254
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A,
255
0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
256
0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24,
257
0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
258
0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D,
259
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
260
0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE,
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0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE)
262
);
263
264
#ifdef CONFIG_RTL8188E
265
static const struct map_t rtl8188e_pg_txpwr_def_info =
266
MAP_ENT(0xB8, 1, 0xFF
267
, MAPSEG_ARRAY_ENT(0x10, 12,
268
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24)
269
);
270
#endif
271
272
#ifdef CONFIG_RTL8188F
273
static const struct map_t rtl8188f_pg_txpwr_def_info =
274
MAP_ENT(0xB8, 1, 0xFF
275
, MAPSEG_ARRAY_ENT(0x10, 12,
276
0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x27, 0x27, 0x27, 0x27, 0x24)
277
);
278
#endif
279
280
#ifdef CONFIG_RTL8188GTV
281
static const struct map_t rtl8188gtv_pg_txpwr_def_info =
282
MAP_ENT(0xB8, 1, 0xFF
283
, MAPSEG_ARRAY_ENT(0x10, 12,
284
0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x27, 0x27, 0x27, 0x27, 0x24)
285
);
286
#endif
287
288
#ifdef CONFIG_RTL8723B
289
static const struct map_t rtl8723b_pg_txpwr_def_info =
290
MAP_ENT(0xB8, 2, 0xFF
291
, MAPSEG_ARRAY_ENT(0x10, 12,
292
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0xE0)
293
, MAPSEG_ARRAY_ENT(0x3A, 12,
294
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0xE0)
295
);
296
#endif
297
298
#ifdef CONFIG_RTL8703B
299
static const struct map_t rtl8703b_pg_txpwr_def_info =
300
MAP_ENT(0xB8, 1, 0xFF
301
, MAPSEG_ARRAY_ENT(0x10, 12,
302
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
303
);
304
#endif
305
306
#ifdef CONFIG_RTL8723D
307
static const struct map_t rtl8723d_pg_txpwr_def_info =
308
MAP_ENT(0xB8, 2, 0xFF
309
, MAPSEG_ARRAY_ENT(0x10, 12,
310
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
311
, MAPSEG_ARRAY_ENT(0x3A, 12,
312
0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x21, 0x21, 0x21, 0x21, 0x21, 0x02)
313
);
314
#endif
315
316
#ifdef CONFIG_RTL8192E
317
static const struct map_t rtl8192e_pg_txpwr_def_info =
318
MAP_ENT(0xB8, 2, 0xFF
319
, MAPSEG_ARRAY_ENT(0x10, 14,
320
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
321
, MAPSEG_ARRAY_ENT(0x3A, 14,
322
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
323
);
324
#endif
325
326
#ifdef CONFIG_RTL8821A
327
static const struct map_t rtl8821a_pg_txpwr_def_info =
328
MAP_ENT(0xB8, 1, 0xFF
329
, MAPSEG_ARRAY_ENT(0x10, 39,
330
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xFF, 0xFF, 0xFF, 0xFF,
331
0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
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0x04, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00)
333
);
334
#endif
335
336
#ifdef CONFIG_RTL8821C
337
static const struct map_t rtl8821c_pg_txpwr_def_info =
338
MAP_ENT(0xB8, 1, 0xFF
339
, MAPSEG_ARRAY_ENT(0x10, 54,
340
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xFF, 0xFF, 0xFF, 0xFF,
341
0xFF, 0xFF, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
342
0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xEC, 0xFF, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
343
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
344
);
345
#endif
346
347
#ifdef CONFIG_RTL8710B
348
static const struct map_t rtl8710b_pg_txpwr_def_info =
349
MAP_ENT(0xC8, 1, 0xFF
350
, MAPSEG_ARRAY_ENT(0x20, 12,
351
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x20)
352
);
353
#endif
354
355
#ifdef CONFIG_RTL8812A
356
static const struct map_t rtl8812a_pg_txpwr_def_info =
357
MAP_ENT(0xB8, 1, 0xFF
358
, MAPSEG_ARRAY_ENT(0x10, 82,
359
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF,
360
0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
361
0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, 0x00, 0xEE, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
362
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A,
363
0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF,
364
0x00, 0xEE)
365
);
366
#endif
367
368
#ifdef CONFIG_RTL8822B
369
static const struct map_t rtl8822b_pg_txpwr_def_info =
370
MAP_ENT(0xB8, 1, 0xFF
371
, MAPSEG_ARRAY_ENT(0x10, 82,
372
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF,
373
0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
374
0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, 0xEC, 0xEC, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
375
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A,
376
0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF,
377
0xEC, 0xEC)
378
);
379
#endif
380
381
#ifdef CONFIG_RTL8822C
382
static const struct map_t rtl8822c_pg_txpwr_def_info =
383
MAP_ENT(0xB8, 1, 0xFF
384
, MAPSEG_ARRAY_ENT(0x10, 82,
385
0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x02, 0x00, 0x00, 0xFF, 0xFF,
386
0xFF, 0xFF, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33,
387
0x02, 0x00, 0xFF, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0xFF, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33,
388
0x33, 0x33, 0x33, 0x33, 0x33, 0x02, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x33, 0x33, 0x33, 0x33,
389
0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x02, 0x00, 0xFF, 0xFF, 0x00, 0xFF,
390
0x00, 0x00)
391
);
392
#endif
393
394
#ifdef CONFIG_RTL8814A
395
static const struct map_t rtl8814a_pg_txpwr_def_info =
396
MAP_ENT(0xB8, 1, 0xFF
397
, MAPSEG_ARRAY_ENT(0x10, 168,
398
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE,
399
0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
400
0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
401
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A,
402
0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
403
0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02,
404
0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
405
0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D,
406
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
407
0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE,
408
0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE)
409
);
410
#endif
411
412
#ifdef CONFIG_RTL8192F/*use 8192F default,no document*/
413
static const struct map_t rtl8192f_pg_txpwr_def_info =
414
MAP_ENT(0xB8, 2, 0xFF
415
, MAPSEG_ARRAY_ENT(0x10, 14,
416
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
417
, MAPSEG_ARRAY_ENT(0x3A, 14,
418
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
419
);
420
#endif
421
422
#ifdef CONFIG_RTL8814B
423
static const struct map_t rtl8814b_pg_txpwr_def_info =
424
MAP_ENT(0xB8, 1, 0xFF
425
, MAPSEG_ARRAY_ENT(0x10, 168,
426
0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x02, 0xFF, 0xFF, 0xFF, 0xFF,
427
0xFF, 0xFF, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
428
0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xEC, 0xFF, 0xFF, 0xFF, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
429
0x28, 0x28, 0x28, 0x28, 0x28, 0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
430
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
431
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
432
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
433
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
434
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
435
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
436
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF)
437
);
438
#endif
439
440
const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter)
441
{
442
u8 interface_type = 0;
443
const struct map_t *map = NULL;
444
445
interface_type = rtw_get_intf_type(adapter);
446
447
switch (rtw_get_chip_type(adapter)) {
448
#ifdef CONFIG_RTL8723B
449
case RTL8723B:
450
map = &rtl8723b_pg_txpwr_def_info;
451
break;
452
#endif
453
#ifdef CONFIG_RTL8703B
454
case RTL8703B:
455
map = &rtl8703b_pg_txpwr_def_info;
456
break;
457
#endif
458
#ifdef CONFIG_RTL8723D
459
case RTL8723D:
460
map = &rtl8723d_pg_txpwr_def_info;
461
break;
462
#endif
463
#ifdef CONFIG_RTL8188E
464
case RTL8188E:
465
map = &rtl8188e_pg_txpwr_def_info;
466
break;
467
#endif
468
#ifdef CONFIG_RTL8188F
469
case RTL8188F:
470
map = &rtl8188f_pg_txpwr_def_info;
471
break;
472
#endif
473
#ifdef CONFIG_RTL8188GTV
474
case RTL8188GTV:
475
map = &rtl8188gtv_pg_txpwr_def_info;
476
break;
477
#endif
478
#ifdef CONFIG_RTL8812A
479
case RTL8812:
480
map = &rtl8812a_pg_txpwr_def_info;
481
break;
482
#endif
483
#ifdef CONFIG_RTL8821A
484
case RTL8821:
485
map = &rtl8821a_pg_txpwr_def_info;
486
break;
487
#endif
488
#ifdef CONFIG_RTL8192E
489
case RTL8192E:
490
map = &rtl8192e_pg_txpwr_def_info;
491
break;
492
#endif
493
#ifdef CONFIG_RTL8814A
494
case RTL8814A:
495
map = &rtl8814a_pg_txpwr_def_info;
496
break;
497
#endif
498
#ifdef CONFIG_RTL8822B
499
case RTL8822B:
500
map = &rtl8822b_pg_txpwr_def_info;
501
break;
502
#endif
503
#ifdef CONFIG_RTL8821C
504
case RTL8821C:
505
map = &rtl8821c_pg_txpwr_def_info;
506
break;
507
#endif
508
#ifdef CONFIG_RTL8710B
509
case RTL8710B:
510
map = &rtl8710b_pg_txpwr_def_info;
511
break;
512
#endif
513
#ifdef CONFIG_RTL8192F
514
case RTL8192F:
515
map = &rtl8192f_pg_txpwr_def_info;
516
break;
517
#endif
518
#ifdef CONFIG_RTL8822C
519
case RTL8822C:
520
map = &rtl8822c_pg_txpwr_def_info;
521
break;
522
#endif
523
#ifdef CONFIG_RTL8814B
524
case RTL8814B:
525
map = &rtl8814b_pg_txpwr_def_info;
526
break;
527
#endif
528
}
529
530
if (map == NULL) {
531
RTW_ERR("%s: unknown chip_type:%u\n"
532
, __func__, rtw_get_chip_type(adapter));
533
rtw_warn_on(1);
534
}
535
536
return map;
537
}
538
539
static u8 hal_chk_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info)
540
{
541
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
542
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
543
u8 path, group, tx_idx;
544
545
if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G))
546
return _SUCCESS;
547
548
for (path = 0; path < MAX_RF_PATH; path++) {
549
if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path))
550
continue;
551
for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
552
if (IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexCCK_Base[path][group])
553
|| IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group]))
554
return _FAIL;
555
}
556
for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
557
if (tx_idx + 1 > hal_data->max_tx_cnt)
558
continue;
559
if (IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx])
560
|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
561
|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
562
|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx]))
563
return _FAIL;
564
}
565
}
566
567
return _SUCCESS;
568
}
569
570
static u8 hal_chk_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info)
571
{
572
#ifdef CONFIG_IEEE80211_BAND_5GHZ
573
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
574
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
575
u8 path, group, tx_idx;
576
577
if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G))
578
return _SUCCESS;
579
580
for (path = 0; path < MAX_RF_PATH; path++) {
581
if (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
582
continue;
583
for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
584
if (IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group]))
585
return _FAIL;
586
for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
587
if (tx_idx + 1 > hal_data->max_tx_cnt)
588
continue;
589
if (IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
590
|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
591
|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
592
|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx])
593
|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx]))
594
return _FAIL;
595
}
596
}
597
#endif /* CONFIG_IEEE80211_BAND_5GHZ */
598
return _SUCCESS;
599
}
600
601
static inline void hal_init_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info)
602
{
603
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
604
u8 path, group, tx_idx;
605
606
if (pwr_info == NULL)
607
return;
608
609
_rtw_memset(pwr_info, 0, sizeof(TxPowerInfo24G));
610
611
/* init with invalid value */
612
for (path = 0; path < MAX_RF_PATH; path++) {
613
for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
614
pwr_info->IndexCCK_Base[path][group] = PG_TXPWR_INVALID_BASE;
615
pwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE;
616
}
617
for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
618
pwr_info->CCK_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
619
pwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
620
pwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
621
pwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
622
}
623
}
624
625
/* init for dummy base and diff */
626
for (path = 0; path < MAX_RF_PATH; path++) {
627
if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path))
628
break;
629
/* 2.4G BW40 base has 1 less group than CCK base*/
630
pwr_info->IndexBW40_Base[path][MAX_CHNL_GROUP_24G - 1] = 0;
631
632
/* dummy diff */
633
pwr_info->CCK_Diff[path][0] = 0; /* 2.4G CCK-1TX */
634
pwr_info->BW40_Diff[path][0] = 0; /* 2.4G BW40-1S */
635
}
636
}
637
638
static inline void hal_init_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info)
639
{
640
#ifdef CONFIG_IEEE80211_BAND_5GHZ
641
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
642
u8 path, group, tx_idx;
643
644
if (pwr_info == NULL)
645
return;
646
647
_rtw_memset(pwr_info, 0, sizeof(TxPowerInfo5G));
648
649
/* init with invalid value */
650
for (path = 0; path < MAX_RF_PATH; path++) {
651
for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
652
pwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE;
653
for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
654
pwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
655
pwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
656
pwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
657
pwr_info->BW80_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
658
pwr_info->BW160_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
659
}
660
}
661
662
for (path = 0; path < MAX_RF_PATH; path++) {
663
if (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
664
break;
665
/* dummy diff */
666
pwr_info->BW40_Diff[path][0] = 0; /* 5G BW40-1S */
667
}
668
#endif /* CONFIG_IEEE80211_BAND_5GHZ */
669
}
670
671
#if DBG_PG_TXPWR_READ
672
#define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) 1
673
#else
674
#define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) (_txpwr_src > PG_TXPWR_SRC_PG_DATA)
675
#endif
676
677
u16 hal_load_pg_txpwr_info_path_2g(
678
_adapter *adapter,
679
TxPowerInfo24G *pwr_info,
680
u32 path,
681
u8 txpwr_src,
682
const struct map_t *txpwr_map,
683
u16 pg_offset)
684
{
685
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
686
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
687
u16 offset = pg_offset;
688
u8 group, tx_idx;
689
u8 val;
690
u8 tmp_base;
691
s8 tmp_diff;
692
693
if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G)) {
694
offset += PG_TXPWR_1PATH_BYTE_NUM_2G;
695
goto exit;
696
}
697
698
if (DBG_PG_TXPWR_READ)
699
RTW_INFO("%s [%c] offset:0x%03x\n", __func__, rf_path_char(path), offset);
700
701
for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
702
if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
703
tmp_base = map_read8(txpwr_map, offset);
704
if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)
705
&& IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexCCK_Base[path][group])
706
) {
707
pwr_info->IndexCCK_Base[path][group] = tmp_base;
708
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
709
RTW_INFO("[%c] 2G G%02d CCK-1T base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
710
}
711
}
712
offset++;
713
}
714
715
for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
716
if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
717
tmp_base = map_read8(txpwr_map, offset);
718
if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)
719
&& IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group])
720
) {
721
pwr_info->IndexBW40_Base[path][group] = tmp_base;
722
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
723
RTW_INFO("[%c] 2G G%02d BW40-1S base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
724
}
725
}
726
offset++;
727
}
728
729
for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
730
if (tx_idx == 0) {
731
if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
732
val = map_read8(txpwr_map, offset);
733
tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
734
if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
735
&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
736
) {
737
pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
738
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
739
RTW_INFO("[%c] 2G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
740
}
741
tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
742
if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
743
&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
744
) {
745
pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
746
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
747
RTW_INFO("[%c] 2G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
748
}
749
}
750
offset++;
751
} else {
752
if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && tx_idx + 1 <= hal_data->max_tx_cnt) {
753
val = map_read8(txpwr_map, offset);
754
tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
755
if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
756
&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
757
) {
758
pwr_info->BW40_Diff[path][tx_idx] = tmp_diff;
759
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
760
RTW_INFO("[%c] 2G BW40-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
761
762
}
763
tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
764
if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
765
&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
766
) {
767
pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
768
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
769
RTW_INFO("[%c] 2G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
770
}
771
}
772
offset++;
773
774
if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && tx_idx + 1 <= hal_data->max_tx_cnt) {
775
val = map_read8(txpwr_map, offset);
776
tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
777
if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
778
&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
779
) {
780
pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
781
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
782
RTW_INFO("[%c] 2G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
783
}
784
tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
785
if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
786
&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx])
787
) {
788
pwr_info->CCK_Diff[path][tx_idx] = tmp_diff;
789
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
790
RTW_INFO("[%c] 2G CCK-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
791
}
792
}
793
offset++;
794
}
795
}
796
797
if (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_2G) {
798
RTW_ERR("%s parse %d bytes != %d\n", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_2G);
799
rtw_warn_on(1);
800
}
801
802
exit:
803
return offset;
804
}
805
806
u16 hal_load_pg_txpwr_info_path_5g(
807
_adapter *adapter,
808
TxPowerInfo5G *pwr_info,
809
u32 path,
810
u8 txpwr_src,
811
const struct map_t *txpwr_map,
812
u16 pg_offset)
813
{
814
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
815
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
816
u16 offset = pg_offset;
817
u8 group, tx_idx;
818
u8 val;
819
u8 tmp_base;
820
s8 tmp_diff;
821
822
#ifdef CONFIG_IEEE80211_BAND_5GHZ
823
if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G))
824
#endif
825
{
826
offset += PG_TXPWR_1PATH_BYTE_NUM_5G;
827
goto exit;
828
}
829
830
#ifdef CONFIG_IEEE80211_BAND_5GHZ
831
if (DBG_PG_TXPWR_READ)
832
RTW_INFO("%s[%c] eaddr:0x%03x\n", __func__, rf_path_char(path), offset);
833
834
for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
835
if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) {
836
tmp_base = map_read8(txpwr_map, offset);
837
if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)
838
&& IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group])
839
) {
840
pwr_info->IndexBW40_Base[path][group] = tmp_base;
841
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
842
RTW_INFO("[%c] 5G G%02d BW40-1S base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
843
}
844
}
845
offset++;
846
}
847
848
for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
849
if (tx_idx == 0) {
850
if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) {
851
val = map_read8(txpwr_map, offset);
852
tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
853
if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
854
&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
855
) {
856
pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
857
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
858
RTW_INFO("[%c] 5G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
859
}
860
tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
861
if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
862
&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
863
) {
864
pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
865
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
866
RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
867
}
868
}
869
offset++;
870
} else {
871
if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && tx_idx + 1 <= hal_data->max_tx_cnt) {
872
val = map_read8(txpwr_map, offset);
873
tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
874
if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
875
&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
876
) {
877
pwr_info->BW40_Diff[path][tx_idx] = tmp_diff;
878
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
879
RTW_INFO("[%c] 5G BW40-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
880
}
881
tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
882
if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
883
&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
884
) {
885
pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
886
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
887
RTW_INFO("[%c] 5G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
888
}
889
}
890
offset++;
891
}
892
}
893
894
/* OFDM diff 2T ~ 3T */
895
if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && hal_data->max_tx_cnt > 1) {
896
val = map_read8(txpwr_map, offset);
897
tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
898
if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
899
&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][1])
900
) {
901
pwr_info->OFDM_Diff[path][1] = tmp_diff;
902
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
903
RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 2, tmp_diff, pg_txpwr_src_str(txpwr_src));
904
}
905
if (hal_data->max_tx_cnt > 2) {
906
tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
907
if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
908
&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][2])
909
) {
910
pwr_info->OFDM_Diff[path][2] = tmp_diff;
911
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
912
RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 3, tmp_diff, pg_txpwr_src_str(txpwr_src));
913
}
914
}
915
}
916
offset++;
917
918
/* OFDM diff 4T */
919
if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && hal_data->max_tx_cnt > 3) {
920
val = map_read8(txpwr_map, offset);
921
tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
922
if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
923
&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][3])
924
) {
925
pwr_info->OFDM_Diff[path][3] = tmp_diff;
926
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
927
RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 4, tmp_diff, pg_txpwr_src_str(txpwr_src));
928
}
929
}
930
offset++;
931
932
for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
933
if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && tx_idx + 1 <= hal_data->max_tx_cnt) {
934
val = map_read8(txpwr_map, offset);
935
tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
936
if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
937
&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx])
938
) {
939
pwr_info->BW80_Diff[path][tx_idx] = tmp_diff;
940
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
941
RTW_INFO("[%c] 5G BW80-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
942
}
943
tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
944
if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
945
&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx])
946
) {
947
pwr_info->BW160_Diff[path][tx_idx] = tmp_diff;
948
if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
949
RTW_INFO("[%c] 5G BW160-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
950
}
951
}
952
offset++;
953
}
954
955
if (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_5G) {
956
RTW_ERR("%s parse %d bytes != %d\n", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_5G);
957
rtw_warn_on(1);
958
}
959
960
#endif /* #ifdef CONFIG_IEEE80211_BAND_5GHZ */
961
962
exit:
963
return offset;
964
}
965
966
void hal_load_pg_txpwr_info(
967
_adapter *adapter,
968
TxPowerInfo24G *pwr_info_2g,
969
TxPowerInfo5G *pwr_info_5g,
970
u8 *pg_data,
971
BOOLEAN AutoLoadFail
972
)
973
{
974
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
975
u8 path;
976
u16 pg_offset;
977
u8 txpwr_src = PG_TXPWR_SRC_PG_DATA;
978
struct map_t pg_data_map = MAP_ENT(184, 1, 0xFF, MAPSEG_PTR_ENT(0x00, 184, pg_data));
979
const struct map_t *txpwr_map = NULL;
980
981
/* init with invalid value and some dummy base and diff */
982
hal_init_pg_txpwr_info_2g(adapter, pwr_info_2g);
983
hal_init_pg_txpwr_info_5g(adapter, pwr_info_5g);
984
985
select_src:
986
pg_offset = hal_spec->pg_txpwr_saddr;
987
988
switch (txpwr_src) {
989
case PG_TXPWR_SRC_PG_DATA:
990
txpwr_map = &pg_data_map;
991
break;
992
case PG_TXPWR_SRC_IC_DEF:
993
txpwr_map = hal_pg_txpwr_def_info(adapter);
994
break;
995
case PG_TXPWR_SRC_DEF:
996
default:
997
txpwr_map = &pg_txpwr_def_info;
998
break;
999
};
1000
1001
if (txpwr_map == NULL)
1002
goto end_parse;
1003
1004
for (path = 0; path < MAX_RF_PATH ; path++) {
1005
if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
1006
break;
1007
pg_offset = hal_load_pg_txpwr_info_path_2g(adapter, pwr_info_2g, path, txpwr_src, txpwr_map, pg_offset);
1008
pg_offset = hal_load_pg_txpwr_info_path_5g(adapter, pwr_info_5g, path, txpwr_src, txpwr_map, pg_offset);
1009
}
1010
1011
if (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) == _SUCCESS
1012
&& hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) == _SUCCESS)
1013
goto exit;
1014
1015
end_parse:
1016
txpwr_src++;
1017
if (txpwr_src < PG_TXPWR_SRC_NUM)
1018
goto select_src;
1019
1020
if (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) != _SUCCESS
1021
|| hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) != _SUCCESS)
1022
rtw_warn_on(1);
1023
1024
exit:
1025
#if DBG_PG_TXPWR_READ
1026
if (pwr_info_2g)
1027
dump_pg_txpwr_info_2g(RTW_DBGDUMP, pwr_info_2g, 4, 4);
1028
if (pwr_info_5g)
1029
dump_pg_txpwr_info_5g(RTW_DBGDUMP, pwr_info_5g, 4, 4);
1030
#endif
1031
1032
return;
1033
}
1034
#endif /* CONFIG_USE_TSSI */
1035
1036
#ifdef CONFIG_EFUSE_CONFIG_FILE
1037
1038
#define EFUSE_POWER_INDEX_INVALID 0xFF
1039
1040
static u8 _check_phy_efuse_tx_power_info_valid(u8 *pg_data, int base_len, u16 pg_offset)
1041
{
1042
int ff_cnt = 0;
1043
int i;
1044
1045
for (i = 0; i < base_len; i++) {
1046
if (*(pg_data + pg_offset + i) == 0xFF)
1047
ff_cnt++;
1048
}
1049
1050
if (ff_cnt == 0)
1051
return _TRUE;
1052
else if (ff_cnt == base_len)
1053
return _FALSE;
1054
else
1055
return EFUSE_POWER_INDEX_INVALID;
1056
}
1057
1058
int check_phy_efuse_tx_power_info_valid(_adapter *adapter)
1059
{
1060
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
1061
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1062
u8 *pg_data = hal_data->efuse_eeprom_data;
1063
u16 pg_offset = hal_spec->pg_txpwr_saddr;
1064
u8 path;
1065
u8 valid_2g_path_bmp = 0;
1066
#ifdef CONFIG_IEEE80211_BAND_5GHZ
1067
u8 valid_5g_path_bmp = 0;
1068
#endif
1069
1070
for (path = 0; path < MAX_RF_PATH; path++) {
1071
u8 ret = _FALSE;
1072
1073
if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
1074
break;
1075
1076
if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
1077
ret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_2G, pg_offset);
1078
if (ret == _TRUE)
1079
valid_2g_path_bmp |= BIT(path);
1080
else if (ret == EFUSE_POWER_INDEX_INVALID)
1081
return _FALSE;
1082
}
1083
pg_offset += PG_TXPWR_1PATH_BYTE_NUM_2G;
1084
1085
#ifdef CONFIG_IEEE80211_BAND_5GHZ
1086
if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) {
1087
ret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_5G, pg_offset);
1088
if (ret == _TRUE)
1089
valid_5g_path_bmp |= BIT(path);
1090
else if (ret == EFUSE_POWER_INDEX_INVALID)
1091
return _FALSE;
1092
}
1093
#endif
1094
pg_offset += PG_TXPWR_1PATH_BYTE_NUM_5G;
1095
}
1096
1097
if ((hal_chk_band_cap(adapter, BAND_CAP_2G) && valid_2g_path_bmp)
1098
#ifdef CONFIG_IEEE80211_BAND_5GHZ
1099
|| (hal_chk_band_cap(adapter, BAND_CAP_5G) && valid_5g_path_bmp)
1100
#endif
1101
)
1102
return _TRUE;
1103
1104
return _FALSE;
1105
}
1106
#endif /* CONFIG_EFUSE_CONFIG_FILE */
1107
1108
#ifndef CONFIG_USE_TSSI
1109
void hal_load_txpwr_info(_adapter *adapter)
1110
{
1111
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1112
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
1113
u8 max_tx_cnt = hal_data->max_tx_cnt;
1114
u8 *pg_data = hal_data->efuse_eeprom_data;
1115
TxPowerInfo24G *pwr_info_2g = NULL;
1116
TxPowerInfo5G *pwr_info_5g = NULL;
1117
u8 rfpath, ch_idx, group, tx_idx;
1118
1119
if (hal_chk_band_cap(adapter, BAND_CAP_2G))
1120
pwr_info_2g = rtw_vmalloc(sizeof(TxPowerInfo24G));
1121
#ifdef CONFIG_IEEE80211_BAND_5GHZ
1122
if (hal_chk_band_cap(adapter, BAND_CAP_5G))
1123
pwr_info_5g = rtw_vmalloc(sizeof(TxPowerInfo5G));
1124
#endif
1125
1126
/* load from pg data (or default value) */
1127
hal_load_pg_txpwr_info(adapter, pwr_info_2g, pwr_info_5g, pg_data, _FALSE);
1128
1129
/* transform to hal_data */
1130
for (rfpath = 0; rfpath < MAX_RF_PATH; rfpath++) {
1131
1132
if (!pwr_info_2g || !HAL_SPEC_CHK_RF_PATH_2G(hal_spec, rfpath))
1133
goto bypass_2g;
1134
1135
/* 2.4G base */
1136
for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++) {
1137
u8 cck_group;
1138
1139
if (rtw_get_ch_group(ch_idx + 1, &group, &cck_group) != BAND_ON_2_4G)
1140
continue;
1141
1142
hal_data->Index24G_CCK_Base[rfpath][ch_idx] = pwr_info_2g->IndexCCK_Base[rfpath][cck_group];
1143
hal_data->Index24G_BW40_Base[rfpath][ch_idx] = pwr_info_2g->IndexBW40_Base[rfpath][group];
1144
}
1145
1146
/* 2.4G diff */
1147
for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
1148
if (tx_idx + 1 > max_tx_cnt)
1149
break;
1150
1151
hal_data->CCK_24G_Diff[rfpath][tx_idx] = pwr_info_2g->CCK_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
1152
hal_data->OFDM_24G_Diff[rfpath][tx_idx] = pwr_info_2g->OFDM_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
1153
hal_data->BW20_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW20_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
1154
hal_data->BW40_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW40_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
1155
}
1156
bypass_2g:
1157
;
1158
1159
#ifdef CONFIG_IEEE80211_BAND_5GHZ
1160
if (!pwr_info_5g || !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, rfpath))
1161
goto bypass_5g;
1162
1163
/* 5G base */
1164
for (ch_idx = 0; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
1165
if (rtw_get_ch_group(center_ch_5g_all[ch_idx], &group, NULL) != BAND_ON_5G)
1166
continue;
1167
hal_data->Index5G_BW40_Base[rfpath][ch_idx] = pwr_info_5g->IndexBW40_Base[rfpath][group];
1168
}
1169
1170
for (ch_idx = 0 ; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++) {
1171
u8 upper, lower;
1172
1173
if (rtw_get_ch_group(center_ch_5g_80m[ch_idx], &group, NULL) != BAND_ON_5G)
1174
continue;
1175
1176
upper = pwr_info_5g->IndexBW40_Base[rfpath][group];
1177
lower = pwr_info_5g->IndexBW40_Base[rfpath][group + 1];
1178
hal_data->Index5G_BW80_Base[rfpath][ch_idx] = (upper + lower) / 2;
1179
}
1180
1181
/* 5G diff */
1182
for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
1183
if (tx_idx + 1 > max_tx_cnt)
1184
break;
1185
1186
hal_data->OFDM_5G_Diff[rfpath][tx_idx] = pwr_info_5g->OFDM_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
1187
hal_data->BW20_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW20_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
1188
hal_data->BW40_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW40_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
1189
hal_data->BW80_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW80_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
1190
}
1191
bypass_5g:
1192
;
1193
#endif /* CONFIG_IEEE80211_BAND_5GHZ */
1194
}
1195
1196
if (pwr_info_2g)
1197
rtw_vmfree(pwr_info_2g, sizeof(TxPowerInfo24G));
1198
if (pwr_info_5g)
1199
rtw_vmfree(pwr_info_5g, sizeof(TxPowerInfo5G));
1200
}
1201
1202
void dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt)
1203
{
1204
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1205
int path, ch_idx, tx_idx;
1206
1207
RTW_PRINT_SEL(sel, "2.4G\n");
1208
RTW_PRINT_SEL(sel, "CCK-1T base:\n");
1209
RTW_PRINT_SEL(sel, "%4s ", "");
1210
for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
1211
_RTW_PRINT_SEL(sel, "%3d ", center_ch_2g[ch_idx]);
1212
_RTW_PRINT_SEL(sel, "\n");
1213
for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
1214
RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
1215
for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
1216
_RTW_PRINT_SEL(sel, "%3u ", hal_data->Index24G_CCK_Base[path][ch_idx]);
1217
_RTW_PRINT_SEL(sel, "\n");
1218
}
1219
RTW_PRINT_SEL(sel, "\n");
1220
1221
RTW_PRINT_SEL(sel, "CCK diff:\n");
1222
RTW_PRINT_SEL(sel, "%4s ", "");
1223
for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
1224
_RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
1225
_RTW_PRINT_SEL(sel, "\n");
1226
for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
1227
RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
1228
for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
1229
_RTW_PRINT_SEL(sel, "%2d ", hal_data->CCK_24G_Diff[path][tx_idx]);
1230
_RTW_PRINT_SEL(sel, "\n");
1231
}
1232
RTW_PRINT_SEL(sel, "\n");
1233
1234
RTW_PRINT_SEL(sel, "BW40-1S base:\n");
1235
RTW_PRINT_SEL(sel, "%4s ", "");
1236
for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
1237
_RTW_PRINT_SEL(sel, "%3d ", center_ch_2g[ch_idx]);
1238
_RTW_PRINT_SEL(sel, "\n");
1239
for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
1240
RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
1241
for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
1242
_RTW_PRINT_SEL(sel, "%3u ", hal_data->Index24G_BW40_Base[path][ch_idx]);
1243
_RTW_PRINT_SEL(sel, "\n");
1244
}
1245
RTW_PRINT_SEL(sel, "\n");
1246
1247
RTW_PRINT_SEL(sel, "OFDM diff:\n");
1248
RTW_PRINT_SEL(sel, "%4s ", "");
1249
for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
1250
_RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
1251
_RTW_PRINT_SEL(sel, "\n");
1252
for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
1253
RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
1254
for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
1255
_RTW_PRINT_SEL(sel, "%2d ", hal_data->OFDM_24G_Diff[path][tx_idx]);
1256
_RTW_PRINT_SEL(sel, "\n");
1257
}
1258
RTW_PRINT_SEL(sel, "\n");
1259
1260
RTW_PRINT_SEL(sel, "BW20 diff:\n");
1261
RTW_PRINT_SEL(sel, "%4s ", "");
1262
for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
1263
_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
1264
_RTW_PRINT_SEL(sel, "\n");
1265
for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
1266
RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
1267
for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
1268
_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW20_24G_Diff[path][tx_idx]);
1269
_RTW_PRINT_SEL(sel, "\n");
1270
}
1271
RTW_PRINT_SEL(sel, "\n");
1272
1273
RTW_PRINT_SEL(sel, "BW40 diff:\n");
1274
RTW_PRINT_SEL(sel, "%4s ", "");
1275
for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
1276
_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
1277
_RTW_PRINT_SEL(sel, "\n");
1278
for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
1279
RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
1280
for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
1281
_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW40_24G_Diff[path][tx_idx]);
1282
_RTW_PRINT_SEL(sel, "\n");
1283
}
1284
RTW_PRINT_SEL(sel, "\n");
1285
}
1286
1287
void dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt)
1288
{
1289
#ifdef CONFIG_IEEE80211_BAND_5GHZ
1290
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1291
int path, ch_idx, tx_idx;
1292
u8 dump_section = 0;
1293
u8 ch_idx_s = 0;
1294
1295
RTW_PRINT_SEL(sel, "5G\n");
1296
RTW_PRINT_SEL(sel, "BW40-1S base:\n");
1297
do {
1298
#define DUMP_5G_BW40_BASE_SECTION_NUM 3
1299
u8 end[DUMP_5G_BW40_BASE_SECTION_NUM] = {64, 144, 177};
1300
1301
RTW_PRINT_SEL(sel, "%4s ", "");
1302
for (ch_idx = ch_idx_s; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
1303
_RTW_PRINT_SEL(sel, "%3d ", center_ch_5g_all[ch_idx]);
1304
if (end[dump_section] == center_ch_5g_all[ch_idx])
1305
break;
1306
}
1307
_RTW_PRINT_SEL(sel, "\n");
1308
for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
1309
RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
1310
for (ch_idx = ch_idx_s; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
1311
_RTW_PRINT_SEL(sel, "%3u ", hal_data->Index5G_BW40_Base[path][ch_idx]);
1312
if (end[dump_section] == center_ch_5g_all[ch_idx])
1313
break;
1314
}
1315
_RTW_PRINT_SEL(sel, "\n");
1316
}
1317
RTW_PRINT_SEL(sel, "\n");
1318
1319
ch_idx_s = ch_idx + 1;
1320
dump_section++;
1321
if (dump_section >= DUMP_5G_BW40_BASE_SECTION_NUM)
1322
break;
1323
} while (1);
1324
1325
RTW_PRINT_SEL(sel, "BW80-1S base:\n");
1326
RTW_PRINT_SEL(sel, "%4s ", "");
1327
for (ch_idx = 0; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++)
1328
_RTW_PRINT_SEL(sel, "%3d ", center_ch_5g_80m[ch_idx]);
1329
_RTW_PRINT_SEL(sel, "\n");
1330
for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
1331
RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
1332
for (ch_idx = 0; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++)
1333
_RTW_PRINT_SEL(sel, "%3u ", hal_data->Index5G_BW80_Base[path][ch_idx]);
1334
_RTW_PRINT_SEL(sel, "\n");
1335
}
1336
RTW_PRINT_SEL(sel, "\n");
1337
1338
RTW_PRINT_SEL(sel, "OFDM diff:\n");
1339
RTW_PRINT_SEL(sel, "%4s ", "");
1340
for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
1341
_RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
1342
_RTW_PRINT_SEL(sel, "\n");
1343
for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
1344
RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
1345
for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
1346
_RTW_PRINT_SEL(sel, "%2d ", hal_data->OFDM_5G_Diff[path][tx_idx]);
1347
_RTW_PRINT_SEL(sel, "\n");
1348
}
1349
RTW_PRINT_SEL(sel, "\n");
1350
1351
RTW_PRINT_SEL(sel, "BW20 diff:\n");
1352
RTW_PRINT_SEL(sel, "%4s ", "");
1353
for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
1354
_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
1355
_RTW_PRINT_SEL(sel, "\n");
1356
for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
1357
RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
1358
for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
1359
_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW20_5G_Diff[path][tx_idx]);
1360
_RTW_PRINT_SEL(sel, "\n");
1361
}
1362
RTW_PRINT_SEL(sel, "\n");
1363
1364
RTW_PRINT_SEL(sel, "BW40 diff:\n");
1365
RTW_PRINT_SEL(sel, "%4s ", "");
1366
for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
1367
_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
1368
_RTW_PRINT_SEL(sel, "\n");
1369
for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
1370
RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
1371
for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
1372
_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW40_5G_Diff[path][tx_idx]);
1373
_RTW_PRINT_SEL(sel, "\n");
1374
}
1375
RTW_PRINT_SEL(sel, "\n");
1376
1377
RTW_PRINT_SEL(sel, "BW80 diff:\n");
1378
RTW_PRINT_SEL(sel, "%4s ", "");
1379
for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
1380
_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
1381
_RTW_PRINT_SEL(sel, "\n");
1382
for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
1383
RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
1384
for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
1385
_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW80_5G_Diff[path][tx_idx]);
1386
_RTW_PRINT_SEL(sel, "\n");
1387
}
1388
RTW_PRINT_SEL(sel, "\n");
1389
#endif /* CONFIG_IEEE80211_BAND_5GHZ */
1390
}
1391
#endif /* CONFIG_USE_TSSI */
1392
1393
/*
1394
* rtw_regsty_get_target_tx_power -
1395
*
1396
* Return dBm or -1 for undefined
1397
*/
1398
s8 rtw_regsty_get_target_tx_power(
1399
PADAPTER Adapter,
1400
u8 Band,
1401
u8 RfPath,
1402
RATE_SECTION RateSection
1403
)
1404
{
1405
struct registry_priv *regsty = adapter_to_regsty(Adapter);
1406
s8 value = 0;
1407
1408
if (RfPath > RF_PATH_D) {
1409
RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
1410
return -1;
1411
}
1412
1413
if (Band != BAND_ON_2_4G
1414
#ifdef CONFIG_IEEE80211_BAND_5GHZ
1415
&& Band != BAND_ON_5G
1416
#endif
1417
) {
1418
RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
1419
return -1;
1420
}
1421
1422
if (RateSection >= RATE_SECTION_NUM
1423
#ifdef CONFIG_IEEE80211_BAND_5GHZ
1424
|| (Band == BAND_ON_5G && RateSection == CCK)
1425
#endif
1426
) {
1427
RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d\n", __func__
1428
, RateSection, Band, RfPath);
1429
return -1;
1430
}
1431
1432
if (Band == BAND_ON_2_4G)
1433
value = regsty->target_tx_pwr_2g[RfPath][RateSection];
1434
#ifdef CONFIG_IEEE80211_BAND_5GHZ
1435
else /* BAND_ON_5G */
1436
value = regsty->target_tx_pwr_5g[RfPath][RateSection - 1];
1437
#endif
1438
1439
return value;
1440
}
1441
1442
bool rtw_regsty_chk_target_tx_power_valid(_adapter *adapter)
1443
{
1444
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
1445
int path, tx_num, band, rs;
1446
s8 target;
1447
1448
for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
1449
if (!hal_is_band_support(adapter, band))
1450
continue;
1451
1452
for (path = 0; path < RF_PATH_MAX; path++) {
1453
if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
1454
break;
1455
1456
for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
1457
tx_num = rate_section_to_tx_num(rs);
1458
if (tx_num + 1 > GET_HAL_TX_NSS(adapter))
1459
continue;
1460
1461
if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
1462
continue;
1463
1464
if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
1465
continue;
1466
1467
target = rtw_regsty_get_target_tx_power(adapter, band, path, rs);
1468
if (target == -1) {
1469
RTW_PRINT("%s return _FALSE for band:%d, path:%d, rs:%d, t:%d\n", __func__, band, path, rs, target);
1470
return _FALSE;
1471
}
1472
}
1473
}
1474
}
1475
1476
return _TRUE;
1477
}
1478
1479
#ifndef CONFIG_USE_TSSI
1480
/*
1481
* PHY_GetTxPowerByRateBase -
1482
*
1483
* Return value in unit of TX Gain Index
1484
*/
1485
u8
1486
PHY_GetTxPowerByRateBase(
1487
PADAPTER Adapter,
1488
u8 Band,
1489
u8 RfPath,
1490
RATE_SECTION RateSection
1491
)
1492
{
1493
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1494
u8 value = 0;
1495
1496
if (RfPath > RF_PATH_D) {
1497
RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
1498
return 0;
1499
}
1500
1501
if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
1502
RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
1503
return 0;
1504
}
1505
1506
if (RateSection >= RATE_SECTION_NUM
1507
|| (Band == BAND_ON_5G && RateSection == CCK)
1508
) {
1509
RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d\n", __func__
1510
, RateSection, Band, RfPath);
1511
return 0;
1512
}
1513
1514
if (Band == BAND_ON_2_4G)
1515
value = pHalData->TxPwrByRateBase2_4G[RfPath][RateSection];
1516
else /* BAND_ON_5G */
1517
value = pHalData->TxPwrByRateBase5G[RfPath][RateSection - 1];
1518
1519
return value;
1520
}
1521
1522
void
1523
phy_SetTxPowerByRateBase(
1524
PADAPTER Adapter,
1525
u8 Band,
1526
u8 RfPath,
1527
RATE_SECTION RateSection,
1528
u8 Value
1529
)
1530
{
1531
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1532
1533
if (RfPath > RF_PATH_D) {
1534
RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
1535
return;
1536
}
1537
1538
if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
1539
RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
1540
return;
1541
}
1542
1543
if (RateSection >= RATE_SECTION_NUM
1544
|| (Band == BAND_ON_5G && RateSection == CCK)
1545
) {
1546
RTW_PRINT("%s invalid RateSection:%d in %sG, RfPath:%d\n", __func__
1547
, RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath);
1548
return;
1549
}
1550
1551
if (Band == BAND_ON_2_4G)
1552
pHalData->TxPwrByRateBase2_4G[RfPath][RateSection] = Value;
1553
else /* BAND_ON_5G */
1554
pHalData->TxPwrByRateBase5G[RfPath][RateSection - 1] = Value;
1555
}
1556
#endif /* !CONFIG_USE_TSSI */
1557
1558
static inline BOOLEAN phy_is_txpwr_by_rate_undefined_of_band_path(_adapter *adapter, u8 band, u8 path)
1559
{
1560
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1561
u8 rate_idx = 0;
1562
1563
for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++) {
1564
if (hal_data->TxPwrByRateOffset[band][path][rate_idx] != 0)
1565
goto exit;
1566
}
1567
1568
exit:
1569
return rate_idx >= TX_PWR_BY_RATE_NUM_RATE ? _TRUE : _FALSE;
1570
}
1571
1572
static inline void phy_txpwr_by_rate_duplicate_band_path(_adapter *adapter, u8 band, u8 s_path, u8 t_path)
1573
{
1574
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1575
u8 rate_idx = 0;
1576
1577
for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++)
1578
hal_data->TxPwrByRateOffset[band][t_path][rate_idx] = hal_data->TxPwrByRateOffset[band][s_path][rate_idx];
1579
}
1580
1581
static void phy_txpwr_by_rate_chk_for_path_dup(_adapter *adapter)
1582
{
1583
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
1584
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1585
u8 band, path;
1586
s8 src_path;
1587
1588
for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++)
1589
for (path = RF_PATH_A; path < RF_PATH_MAX; path++)
1590
hal_data->txpwr_by_rate_undefined_band_path[band][path] = 0;
1591
1592
for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
1593
if (!hal_is_band_support(adapter, band))
1594
continue;
1595
1596
for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
1597
if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
1598
continue;
1599
1600
if (phy_is_txpwr_by_rate_undefined_of_band_path(adapter, band, path))
1601
hal_data->txpwr_by_rate_undefined_band_path[band][path] = 1;
1602
}
1603
}
1604
1605
for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
1606
if (!hal_is_band_support(adapter, band))
1607
continue;
1608
1609
src_path = -1;
1610
for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
1611
if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
1612
continue;
1613
1614
/* find src */
1615
if (src_path == -1 && hal_data->txpwr_by_rate_undefined_band_path[band][path] == 0)
1616
src_path = path;
1617
}
1618
1619
if (src_path == -1) {
1620
RTW_ERR("%s all power by rate undefined\n", __func__);
1621
continue;
1622
}
1623
1624
for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
1625
if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
1626
continue;
1627
1628
/* duplicate src to undefined one */
1629
if (hal_data->txpwr_by_rate_undefined_band_path[band][path] == 1) {
1630
RTW_INFO("%s duplicate %s [%c] to [%c]\n", __func__
1631
, band_str(band), rf_path_char(src_path), rf_path_char(path));
1632
phy_txpwr_by_rate_duplicate_band_path(adapter, band, src_path, path);
1633
}
1634
}
1635
}
1636
}
1637
1638
#ifdef CONFIG_USE_TSSI
1639
static void phy_save_original_txpwr_by_rate(_adapter *adapter)
1640
{
1641
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1642
1643
_rtw_memcpy(hal_data->TxPwrByRate, hal_data->TxPwrByRateOffset, sizeof(hal_data->TxPwrByRate));
1644
}
1645
#endif
1646
1647
#ifndef CONFIG_USE_TSSI
1648
void
1649
phy_StoreTxPowerByRateBase(
1650
PADAPTER pAdapter
1651
)
1652
{
1653
struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);
1654
struct registry_priv *regsty = adapter_to_regsty(pAdapter);
1655
1656
u8 rate_sec_base[RATE_SECTION_NUM] = {
1657
MGN_11M,
1658
MGN_54M,
1659
MGN_MCS7,
1660
MGN_MCS15,
1661
MGN_MCS23,
1662
MGN_MCS31,
1663
MGN_VHT1SS_MCS7,
1664
MGN_VHT2SS_MCS7,
1665
MGN_VHT3SS_MCS7,
1666
MGN_VHT4SS_MCS7,
1667
};
1668
1669
u8 band, path, rs, tx_num, base;
1670
1671
for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
1672
if (!hal_is_band_support(pAdapter, band))
1673
continue;
1674
1675
for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
1676
if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
1677
break;
1678
1679
for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
1680
tx_num = rate_section_to_tx_num(rs);
1681
if (tx_num + 1 > GET_HAL_TX_NSS(pAdapter))
1682
continue;
1683
1684
if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
1685
continue;
1686
1687
if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
1688
continue;
1689
1690
if (regsty->target_tx_pwr_valid == _TRUE)
1691
base = hal_spec->txgi_pdbm * rtw_regsty_get_target_tx_power(pAdapter, band, path, rs);
1692
else
1693
base = _PHY_GetTxPowerByRate(pAdapter, band, path, rate_sec_base[rs]);
1694
phy_SetTxPowerByRateBase(pAdapter, band, path, rs, base);
1695
}
1696
}
1697
}
1698
}
1699
#endif
1700
1701
static u8 get_val_from_dhex(u32 dhex, u8 i)
1702
{
1703
return (((dhex >> (i * 8 + 4)) & 0xF)) * 10 + ((dhex >> (i * 8)) & 0xF);
1704
}
1705
1706
static u8 get_val_from_hex(u32 hex, u8 i)
1707
{
1708
return (hex >> (i * 8)) & 0xFF;
1709
}
1710
1711
void
1712
PHY_GetRateValuesOfTxPowerByRate(
1713
PADAPTER pAdapter,
1714
u32 RegAddr,
1715
u32 BitMask,
1716
u32 Value,
1717
u8 *Rate,
1718
s8 *PwrByRateVal,
1719
u8 *RateNum
1720
)
1721
{
1722
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1723
struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1724
u8 i = 0;
1725
u8 (*get_val)(u32, u8);
1726
1727
if (pDM_Odm->phy_reg_pg_version == 1)
1728
get_val = get_val_from_dhex;
1729
else
1730
get_val = get_val_from_hex;
1731
1732
switch (RegAddr) {
1733
case rTxAGC_A_Rate18_06:
1734
case rTxAGC_B_Rate18_06:
1735
Rate[0] = MGN_6M;
1736
Rate[1] = MGN_9M;
1737
Rate[2] = MGN_12M;
1738
Rate[3] = MGN_18M;
1739
for (i = 0; i < 4; ++i)
1740
PwrByRateVal[i] = (s8)get_val(Value, i);
1741
*RateNum = 4;
1742
break;
1743
1744
case rTxAGC_A_Rate54_24:
1745
case rTxAGC_B_Rate54_24:
1746
Rate[0] = MGN_24M;
1747
Rate[1] = MGN_36M;
1748
Rate[2] = MGN_48M;
1749
Rate[3] = MGN_54M;
1750
for (i = 0; i < 4; ++i)
1751
PwrByRateVal[i] = (s8)get_val(Value, i);
1752
*RateNum = 4;
1753
break;
1754
1755
case rTxAGC_A_CCK1_Mcs32:
1756
Rate[0] = MGN_1M;
1757
PwrByRateVal[0] = (s8)get_val(Value, 1);
1758
*RateNum = 1;
1759
break;
1760
1761
case rTxAGC_B_CCK11_A_CCK2_11:
1762
if (BitMask == 0xffffff00) {
1763
Rate[0] = MGN_2M;
1764
Rate[1] = MGN_5_5M;
1765
Rate[2] = MGN_11M;
1766
for (i = 1; i < 4; ++i)
1767
PwrByRateVal[i - 1] = (s8)get_val(Value, i);
1768
*RateNum = 3;
1769
} else if (BitMask == 0x000000ff) {
1770
Rate[0] = MGN_11M;
1771
PwrByRateVal[0] = (s8)get_val(Value, 0);
1772
*RateNum = 1;
1773
}
1774
break;
1775
1776
case rTxAGC_A_Mcs03_Mcs00:
1777
case rTxAGC_B_Mcs03_Mcs00:
1778
Rate[0] = MGN_MCS0;
1779
Rate[1] = MGN_MCS1;
1780
Rate[2] = MGN_MCS2;
1781
Rate[3] = MGN_MCS3;
1782
for (i = 0; i < 4; ++i)
1783
PwrByRateVal[i] = (s8)get_val(Value, i);
1784
*RateNum = 4;
1785
break;
1786
1787
case rTxAGC_A_Mcs07_Mcs04:
1788
case rTxAGC_B_Mcs07_Mcs04:
1789
Rate[0] = MGN_MCS4;
1790
Rate[1] = MGN_MCS5;
1791
Rate[2] = MGN_MCS6;
1792
Rate[3] = MGN_MCS7;
1793
for (i = 0; i < 4; ++i)
1794
PwrByRateVal[i] = (s8)get_val(Value, i);
1795
*RateNum = 4;
1796
break;
1797
1798
case rTxAGC_A_Mcs11_Mcs08:
1799
case rTxAGC_B_Mcs11_Mcs08:
1800
Rate[0] = MGN_MCS8;
1801
Rate[1] = MGN_MCS9;
1802
Rate[2] = MGN_MCS10;
1803
Rate[3] = MGN_MCS11;
1804
for (i = 0; i < 4; ++i)
1805
PwrByRateVal[i] = (s8)get_val(Value, i);
1806
*RateNum = 4;
1807
break;
1808
1809
case rTxAGC_A_Mcs15_Mcs12:
1810
case rTxAGC_B_Mcs15_Mcs12:
1811
Rate[0] = MGN_MCS12;
1812
Rate[1] = MGN_MCS13;
1813
Rate[2] = MGN_MCS14;
1814
Rate[3] = MGN_MCS15;
1815
for (i = 0; i < 4; ++i)
1816
PwrByRateVal[i] = (s8)get_val(Value, i);
1817
*RateNum = 4;
1818
break;
1819
1820
case rTxAGC_B_CCK1_55_Mcs32:
1821
Rate[0] = MGN_1M;
1822
Rate[1] = MGN_2M;
1823
Rate[2] = MGN_5_5M;
1824
for (i = 1; i < 4; ++i)
1825
PwrByRateVal[i - 1] = (s8)get_val(Value, i);
1826
*RateNum = 3;
1827
break;
1828
1829
case 0xC20:
1830
case 0xE20:
1831
case 0x1820:
1832
case 0x1a20:
1833
Rate[0] = MGN_1M;
1834
Rate[1] = MGN_2M;
1835
Rate[2] = MGN_5_5M;
1836
Rate[3] = MGN_11M;
1837
for (i = 0; i < 4; ++i)
1838
PwrByRateVal[i] = (s8)get_val(Value, i);
1839
*RateNum = 4;
1840
break;
1841
1842
case 0xC24:
1843
case 0xE24:
1844
case 0x1824:
1845
case 0x1a24:
1846
Rate[0] = MGN_6M;
1847
Rate[1] = MGN_9M;
1848
Rate[2] = MGN_12M;
1849
Rate[3] = MGN_18M;
1850
for (i = 0; i < 4; ++i)
1851
PwrByRateVal[i] = (s8)get_val(Value, i);
1852
*RateNum = 4;
1853
break;
1854
1855
case 0xC28:
1856
case 0xE28:
1857
case 0x1828:
1858
case 0x1a28:
1859
Rate[0] = MGN_24M;
1860
Rate[1] = MGN_36M;
1861
Rate[2] = MGN_48M;
1862
Rate[3] = MGN_54M;
1863
for (i = 0; i < 4; ++i)
1864
PwrByRateVal[i] = (s8)get_val(Value, i);
1865
*RateNum = 4;
1866
break;
1867
1868
case 0xC2C:
1869
case 0xE2C:
1870
case 0x182C:
1871
case 0x1a2C:
1872
Rate[0] = MGN_MCS0;
1873
Rate[1] = MGN_MCS1;
1874
Rate[2] = MGN_MCS2;
1875
Rate[3] = MGN_MCS3;
1876
for (i = 0; i < 4; ++i)
1877
PwrByRateVal[i] = (s8)get_val(Value, i);
1878
*RateNum = 4;
1879
break;
1880
1881
case 0xC30:
1882
case 0xE30:
1883
case 0x1830:
1884
case 0x1a30:
1885
Rate[0] = MGN_MCS4;
1886
Rate[1] = MGN_MCS5;
1887
Rate[2] = MGN_MCS6;
1888
Rate[3] = MGN_MCS7;
1889
for (i = 0; i < 4; ++i)
1890
PwrByRateVal[i] = (s8)get_val(Value, i);
1891
*RateNum = 4;
1892
break;
1893
1894
case 0xC34:
1895
case 0xE34:
1896
case 0x1834:
1897
case 0x1a34:
1898
Rate[0] = MGN_MCS8;
1899
Rate[1] = MGN_MCS9;
1900
Rate[2] = MGN_MCS10;
1901
Rate[3] = MGN_MCS11;
1902
for (i = 0; i < 4; ++i)
1903
PwrByRateVal[i] = (s8)get_val(Value, i);
1904
*RateNum = 4;
1905
break;
1906
1907
case 0xC38:
1908
case 0xE38:
1909
case 0x1838:
1910
case 0x1a38:
1911
Rate[0] = MGN_MCS12;
1912
Rate[1] = MGN_MCS13;
1913
Rate[2] = MGN_MCS14;
1914
Rate[3] = MGN_MCS15;
1915
for (i = 0; i < 4; ++i)
1916
PwrByRateVal[i] = (s8)get_val(Value, i);
1917
*RateNum = 4;
1918
break;
1919
1920
case 0xC3C:
1921
case 0xE3C:
1922
case 0x183C:
1923
case 0x1a3C:
1924
Rate[0] = MGN_VHT1SS_MCS0;
1925
Rate[1] = MGN_VHT1SS_MCS1;
1926
Rate[2] = MGN_VHT1SS_MCS2;
1927
Rate[3] = MGN_VHT1SS_MCS3;
1928
for (i = 0; i < 4; ++i)
1929
PwrByRateVal[i] = (s8)get_val(Value, i);
1930
*RateNum = 4;
1931
break;
1932
1933
case 0xC40:
1934
case 0xE40:
1935
case 0x1840:
1936
case 0x1a40:
1937
Rate[0] = MGN_VHT1SS_MCS4;
1938
Rate[1] = MGN_VHT1SS_MCS5;
1939
Rate[2] = MGN_VHT1SS_MCS6;
1940
Rate[3] = MGN_VHT1SS_MCS7;
1941
for (i = 0; i < 4; ++i)
1942
PwrByRateVal[i] = (s8)get_val(Value, i);
1943
*RateNum = 4;
1944
break;
1945
1946
case 0xC44:
1947
case 0xE44:
1948
case 0x1844:
1949
case 0x1a44:
1950
Rate[0] = MGN_VHT1SS_MCS8;
1951
Rate[1] = MGN_VHT1SS_MCS9;
1952
Rate[2] = MGN_VHT2SS_MCS0;
1953
Rate[3] = MGN_VHT2SS_MCS1;
1954
for (i = 0; i < 4; ++i)
1955
PwrByRateVal[i] = (s8)get_val(Value, i);
1956
*RateNum = 4;
1957
break;
1958
1959
case 0xC48:
1960
case 0xE48:
1961
case 0x1848:
1962
case 0x1a48:
1963
Rate[0] = MGN_VHT2SS_MCS2;
1964
Rate[1] = MGN_VHT2SS_MCS3;
1965
Rate[2] = MGN_VHT2SS_MCS4;
1966
Rate[3] = MGN_VHT2SS_MCS5;
1967
for (i = 0; i < 4; ++i)
1968
PwrByRateVal[i] = (s8)get_val(Value, i);
1969
*RateNum = 4;
1970
break;
1971
1972
case 0xC4C:
1973
case 0xE4C:
1974
case 0x184C:
1975
case 0x1a4C:
1976
Rate[0] = MGN_VHT2SS_MCS6;
1977
Rate[1] = MGN_VHT2SS_MCS7;
1978
Rate[2] = MGN_VHT2SS_MCS8;
1979
Rate[3] = MGN_VHT2SS_MCS9;
1980
for (i = 0; i < 4; ++i)
1981
PwrByRateVal[i] = (s8)get_val(Value, i);
1982
*RateNum = 4;
1983
break;
1984
1985
case 0xCD8:
1986
case 0xED8:
1987
case 0x18D8:
1988
case 0x1aD8:
1989
Rate[0] = MGN_MCS16;
1990
Rate[1] = MGN_MCS17;
1991
Rate[2] = MGN_MCS18;
1992
Rate[3] = MGN_MCS19;
1993
for (i = 0; i < 4; ++i)
1994
PwrByRateVal[i] = (s8)get_val(Value, i);
1995
*RateNum = 4;
1996
break;
1997
1998
case 0xCDC:
1999
case 0xEDC:
2000
case 0x18DC:
2001
case 0x1aDC:
2002
Rate[0] = MGN_MCS20;
2003
Rate[1] = MGN_MCS21;
2004
Rate[2] = MGN_MCS22;
2005
Rate[3] = MGN_MCS23;
2006
for (i = 0; i < 4; ++i)
2007
PwrByRateVal[i] = (s8)get_val(Value, i);
2008
*RateNum = 4;
2009
break;
2010
2011
case 0x3a24: /* HT MCS24-27 */
2012
Rate[0] = MGN_MCS24;
2013
Rate[1] = MGN_MCS25;
2014
Rate[2] = MGN_MCS26;
2015
Rate[3] = MGN_MCS27;
2016
for (i = 0; i < 4; ++i)
2017
PwrByRateVal[i] = (s8)get_val(Value, i);
2018
*RateNum = 4;
2019
break;
2020
2021
case 0x3a28: /* HT MCS28-31 */
2022
Rate[0] = MGN_MCS28;
2023
Rate[1] = MGN_MCS29;
2024
Rate[2] = MGN_MCS30;
2025
Rate[3] = MGN_MCS31;
2026
for (i = 0; i < 4; ++i)
2027
PwrByRateVal[i] = (s8)get_val(Value, i);
2028
*RateNum = 4;
2029
break;
2030
2031
case 0xCE0:
2032
case 0xEE0:
2033
case 0x18E0:
2034
case 0x1aE0:
2035
Rate[0] = MGN_VHT3SS_MCS0;
2036
Rate[1] = MGN_VHT3SS_MCS1;
2037
Rate[2] = MGN_VHT3SS_MCS2;
2038
Rate[3] = MGN_VHT3SS_MCS3;
2039
for (i = 0; i < 4; ++i)
2040
PwrByRateVal[i] = (s8)get_val(Value, i);
2041
*RateNum = 4;
2042
break;
2043
2044
case 0xCE4:
2045
case 0xEE4:
2046
case 0x18E4:
2047
case 0x1aE4:
2048
Rate[0] = MGN_VHT3SS_MCS4;
2049
Rate[1] = MGN_VHT3SS_MCS5;
2050
Rate[2] = MGN_VHT3SS_MCS6;
2051
Rate[3] = MGN_VHT3SS_MCS7;
2052
for (i = 0; i < 4; ++i)
2053
PwrByRateVal[i] = (s8)get_val(Value, i);
2054
*RateNum = 4;
2055
break;
2056
2057
case 0xCE8:
2058
case 0xEE8:
2059
case 0x18E8:
2060
case 0x1aE8:
2061
case 0x3a48:
2062
Rate[0] = MGN_VHT3SS_MCS8;
2063
Rate[1] = MGN_VHT3SS_MCS9;
2064
Rate[2] = MGN_VHT4SS_MCS0;
2065
Rate[3] = MGN_VHT4SS_MCS1;
2066
for (i = 0; i < 4; ++i)
2067
PwrByRateVal[i] = (s8)get_val(Value, i);
2068
*RateNum = 4;
2069
break;
2070
2071
case 0x3a4c:
2072
Rate[0] = MGN_VHT4SS_MCS2;
2073
Rate[1] = MGN_VHT4SS_MCS3;
2074
Rate[2] = MGN_VHT4SS_MCS4;
2075
Rate[3] = MGN_VHT4SS_MCS5;
2076
for (i = 0; i < 4; ++i)
2077
PwrByRateVal[i] = (s8)get_val(Value, i);
2078
*RateNum = 4;
2079
break;
2080
2081
case 0x3a50:
2082
Rate[0] = MGN_VHT4SS_MCS6;
2083
Rate[1] = MGN_VHT4SS_MCS7;
2084
Rate[2] = MGN_VHT4SS_MCS8;
2085
Rate[3] = MGN_VHT4SS_MCS9;
2086
for (i = 0; i < 4; ++i)
2087
PwrByRateVal[i] = (s8)get_val(Value, i);
2088
*RateNum = 4;
2089
break;
2090
2091
default:
2092
RTW_PRINT("Invalid RegAddr 0x%x in %s()\n", RegAddr, __func__);
2093
break;
2094
};
2095
}
2096
2097
void
2098
PHY_StoreTxPowerByRateNew(
2099
PADAPTER pAdapter,
2100
u32 Band,
2101
u32 RfPath,
2102
u32 RegAddr,
2103
u32 BitMask,
2104
u32 Data
2105
)
2106
{
2107
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2108
u8 i = 0, rates[4] = {0}, rateNum = 0;
2109
s8 PwrByRateVal[4] = {0};
2110
2111
PHY_GetRateValuesOfTxPowerByRate(pAdapter, RegAddr, BitMask, Data, rates, PwrByRateVal, &rateNum);
2112
2113
if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
2114
RTW_PRINT("Invalid Band %d\n", Band);
2115
return;
2116
}
2117
2118
if (RfPath > RF_PATH_D) {
2119
RTW_PRINT("Invalid RfPath %d\n", RfPath);
2120
return;
2121
}
2122
2123
for (i = 0; i < rateNum; ++i) {
2124
u8 rate_idx = PHY_GetRateIndexOfTxPowerByRate(rates[i]);
2125
2126
pHalData->TxPwrByRateOffset[Band][RfPath][rate_idx] = PwrByRateVal[i];
2127
}
2128
}
2129
2130
void
2131
PHY_InitTxPowerByRate(
2132
PADAPTER pAdapter
2133
)
2134
{
2135
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2136
u8 band = 0, rfPath = 0, rate = 0;
2137
2138
for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band)
2139
for (rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath)
2140
for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate)
2141
pHalData->TxPwrByRateOffset[band][rfPath][rate] = 0;
2142
}
2143
2144
void
2145
phy_store_tx_power_by_rate(
2146
PADAPTER pAdapter,
2147
u32 Band,
2148
u32 RfPath,
2149
u32 TxNum,
2150
u32 RegAddr,
2151
u32 BitMask,
2152
u32 Data
2153
)
2154
{
2155
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2156
struct dm_struct *pDM_Odm = &pHalData->odmpriv;
2157
2158
if (pDM_Odm->phy_reg_pg_version > 0)
2159
PHY_StoreTxPowerByRateNew(pAdapter, Band, RfPath, RegAddr, BitMask, Data);
2160
else
2161
RTW_INFO("Invalid PHY_REG_PG.txt version %d\n", pDM_Odm->phy_reg_pg_version);
2162
2163
}
2164
2165
#ifdef CONFIG_USE_TSSI
2166
void
2167
phy_ConvertTxPowerByRateInDbmToRelativeValues_TSSI(
2168
PADAPTER pAdapter
2169
)
2170
{
2171
u8 base = 0, i = 0, value = 0,
2172
band = 0, path = 0;
2173
u8 cckRates[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M},
2174
ofdmRates[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M},
2175
mcs0_7Rates[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7},
2176
mcs8_15Rates[8] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15},
2177
mcs16_23Rates[8] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23},
2178
mcs24_31Rates[8] = {MGN_MCS24, MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29, MGN_MCS30, MGN_MCS31},
2179
vht1ssRates[10] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
2180
MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9},
2181
vht2ssRates[10] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
2182
MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9},
2183
vht3ssRates[10] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
2184
MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9},
2185
vht4ssRates[10] = {MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
2186
MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9};
2187
2188
/* RTW_INFO("===>%s()\n", __func__); */
2189
2190
for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) {
2191
for (path = RF_PATH_A; path <= RF_PATH_D; ++path) {
2192
base = PHY_GetTxPowerByRate(pAdapter, band, path, MGN_MCS7);
2193
2194
/* CCK */
2195
for (i = 0; i < sizeof(cckRates); ++i) {
2196
value = PHY_GetTxPowerByRate(pAdapter, band, path, cckRates[i]);
2197
PHY_SetTxPowerByRate(pAdapter, band, path, cckRates[i], value - base);
2198
}
2199
2200
/* OFDM */
2201
for (i = 0; i < sizeof(ofdmRates); ++i) {
2202
value = PHY_GetTxPowerByRate(pAdapter, band, path, ofdmRates[i]);
2203
PHY_SetTxPowerByRate(pAdapter, band, path, ofdmRates[i], value - base);
2204
}
2205
2206
/* HT MCS0~7 */
2207
for (i = 0; i < sizeof(mcs0_7Rates); ++i) {
2208
value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs0_7Rates[i]);
2209
PHY_SetTxPowerByRate(pAdapter, band, path, mcs0_7Rates[i], value - base);
2210
}
2211
2212
/* HT MCS8~15 */
2213
for (i = 0; i < sizeof(mcs8_15Rates); ++i) {
2214
value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs8_15Rates[i]);
2215
PHY_SetTxPowerByRate(pAdapter, band, path, mcs8_15Rates[i], value - base);
2216
}
2217
2218
/* HT MCS16~23 */
2219
for (i = 0; i < sizeof(mcs16_23Rates); ++i) {
2220
value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs16_23Rates[i]);
2221
PHY_SetTxPowerByRate(pAdapter, band, path, mcs16_23Rates[i], value - base);
2222
}
2223
2224
/* HT MCS24~31 */
2225
for (i = 0; i < sizeof(mcs24_31Rates); ++i) {
2226
value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs24_31Rates[i]);
2227
PHY_SetTxPowerByRate(pAdapter, band, path, mcs24_31Rates[i], value - base);
2228
}
2229
2230
/* VHT 1SS */
2231
for (i = 0; i < sizeof(vht1ssRates); ++i) {
2232
value = PHY_GetTxPowerByRate(pAdapter, band, path, vht1ssRates[i]);
2233
PHY_SetTxPowerByRate(pAdapter, band, path, vht1ssRates[i], value - base);
2234
}
2235
2236
/* VHT 2SS */
2237
for (i = 0; i < sizeof(vht2ssRates); ++i) {
2238
value = PHY_GetTxPowerByRate(pAdapter, band, path, vht2ssRates[i]);
2239
PHY_SetTxPowerByRate(pAdapter, band, path, vht2ssRates[i], value - base);
2240
}
2241
2242
/* VHT 3SS */
2243
for (i = 0; i < sizeof(vht3ssRates); ++i) {
2244
value = PHY_GetTxPowerByRate(pAdapter, band, path, vht3ssRates[i]);
2245
PHY_SetTxPowerByRate(pAdapter, band, path, vht3ssRates[i], value - base);
2246
}
2247
2248
/* VHT 4SS */
2249
for (i = 0; i < sizeof(vht4ssRates); ++i) {
2250
value = PHY_GetTxPowerByRate(pAdapter, band, path, vht4ssRates[i]);
2251
PHY_SetTxPowerByRate(pAdapter, band, path, vht4ssRates[i], value - base);
2252
}
2253
}
2254
}
2255
2256
/* RTW_INFO("<===%s()\n", __func__); */
2257
}
2258
#else
2259
void
2260
phy_ConvertTxPowerByRateInDbmToRelativeValues(
2261
PADAPTER pAdapter
2262
)
2263
{
2264
u8 base = 0, i = 0, value = 0,
2265
band = 0, path = 0;
2266
u8 cckRates[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M},
2267
ofdmRates[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M},
2268
mcs0_7Rates[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7},
2269
mcs8_15Rates[8] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15},
2270
mcs16_23Rates[8] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23},
2271
mcs24_31Rates[8] = {MGN_MCS24, MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29, MGN_MCS30, MGN_MCS31},
2272
vht1ssRates[10] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
2273
MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9},
2274
vht2ssRates[10] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
2275
MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9},
2276
vht3ssRates[10] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
2277
MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9},
2278
vht4ssRates[10] = {MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
2279
MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9};
2280
2281
/* RTW_INFO("===>PHY_ConvertTxPowerByRateInDbmToRelativeValues()\n" ); */
2282
2283
for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) {
2284
for (path = RF_PATH_A; path <= RF_PATH_D; ++path) {
2285
/* CCK */
2286
if (band == BAND_ON_2_4G) {
2287
base = PHY_GetTxPowerByRateBase(pAdapter, band, path, CCK);
2288
for (i = 0; i < sizeof(cckRates); ++i) {
2289
value = PHY_GetTxPowerByRate(pAdapter, band, path, cckRates[i]);
2290
PHY_SetTxPowerByRate(pAdapter, band, path, cckRates[i], value - base);
2291
}
2292
}
2293
2294
/* OFDM */
2295
base = PHY_GetTxPowerByRateBase(pAdapter, band, path, OFDM);
2296
for (i = 0; i < sizeof(ofdmRates); ++i) {
2297
value = PHY_GetTxPowerByRate(pAdapter, band, path, ofdmRates[i]);
2298
PHY_SetTxPowerByRate(pAdapter, band, path, ofdmRates[i], value - base);
2299
}
2300
2301
/* HT MCS0~7 */
2302
base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_1SS);
2303
for (i = 0; i < sizeof(mcs0_7Rates); ++i) {
2304
value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs0_7Rates[i]);
2305
PHY_SetTxPowerByRate(pAdapter, band, path, mcs0_7Rates[i], value - base);
2306
}
2307
2308
/* HT MCS8~15 */
2309
base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_2SS);
2310
for (i = 0; i < sizeof(mcs8_15Rates); ++i) {
2311
value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs8_15Rates[i]);
2312
PHY_SetTxPowerByRate(pAdapter, band, path, mcs8_15Rates[i], value - base);
2313
}
2314
2315
/* HT MCS16~23 */
2316
base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_3SS);
2317
for (i = 0; i < sizeof(mcs16_23Rates); ++i) {
2318
value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs16_23Rates[i]);
2319
PHY_SetTxPowerByRate(pAdapter, band, path, mcs16_23Rates[i], value - base);
2320
}
2321
2322
/* HT MCS24~31 */
2323
base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_4SS);
2324
for (i = 0; i < sizeof(mcs24_31Rates); ++i) {
2325
value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs24_31Rates[i]);
2326
PHY_SetTxPowerByRate(pAdapter, band, path, mcs24_31Rates[i], value - base);
2327
}
2328
2329
/* VHT 1SS */
2330
base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_1SS);
2331
for (i = 0; i < sizeof(vht1ssRates); ++i) {
2332
value = PHY_GetTxPowerByRate(pAdapter, band, path, vht1ssRates[i]);
2333
PHY_SetTxPowerByRate(pAdapter, band, path, vht1ssRates[i], value - base);
2334
}
2335
2336
/* VHT 2SS */
2337
base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_2SS);
2338
for (i = 0; i < sizeof(vht2ssRates); ++i) {
2339
value = PHY_GetTxPowerByRate(pAdapter, band, path, vht2ssRates[i]);
2340
PHY_SetTxPowerByRate(pAdapter, band, path, vht2ssRates[i], value - base);
2341
}
2342
2343
/* VHT 3SS */
2344
base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_3SS);
2345
for (i = 0; i < sizeof(vht3ssRates); ++i) {
2346
value = PHY_GetTxPowerByRate(pAdapter, band, path, vht3ssRates[i]);
2347
PHY_SetTxPowerByRate(pAdapter, band, path, vht3ssRates[i], value - base);
2348
}
2349
2350
/* VHT 4SS */
2351
base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_4SS);
2352
for (i = 0; i < sizeof(vht4ssRates); ++i) {
2353
value = PHY_GetTxPowerByRate(pAdapter, band, path, vht4ssRates[i]);
2354
PHY_SetTxPowerByRate(pAdapter, band, path, vht4ssRates[i], value - base);
2355
}
2356
}
2357
}
2358
2359
/* RTW_INFO("<===PHY_ConvertTxPowerByRateInDbmToRelativeValues()\n" ); */
2360
}
2361
#endif /* CONFIG_USE_TSSI */
2362
2363
/*
2364
* This function must be called if the value in the PHY_REG_PG.txt(or header)
2365
* is exact dBm values
2366
*/
2367
void
2368
PHY_TxPowerByRateConfiguration(
2369
PADAPTER pAdapter
2370
)
2371
{
2372
phy_txpwr_by_rate_chk_for_path_dup(pAdapter);
2373
#ifdef CONFIG_USE_TSSI
2374
phy_save_original_txpwr_by_rate(pAdapter);
2375
phy_ConvertTxPowerByRateInDbmToRelativeValues_TSSI(pAdapter);
2376
#else
2377
phy_StoreTxPowerByRateBase(pAdapter);
2378
phy_ConvertTxPowerByRateInDbmToRelativeValues(pAdapter);
2379
#endif
2380
}
2381
2382
void
2383
phy_set_tx_power_index_by_rate_section(
2384
PADAPTER pAdapter,
2385
enum rf_path RFPath,
2386
u8 Channel,
2387
u8 RateSection
2388
)
2389
{
2390
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
2391
2392
if (RateSection >= RATE_SECTION_NUM) {
2393
RTW_INFO("Invalid RateSection %d in %s", RateSection, __func__);
2394
rtw_warn_on(1);
2395
goto exit;
2396
}
2397
2398
if (RateSection == CCK && pHalData->current_band_type != BAND_ON_2_4G)
2399
goto exit;
2400
2401
PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->current_channel_bw, Channel,
2402
rates_by_sections[RateSection].rates, rates_by_sections[RateSection].rate_num);
2403
2404
exit:
2405
return;
2406
}
2407
2408
BOOLEAN
2409
phy_GetChnlIndex(
2410
u8 Channel,
2411
u8 *ChannelIdx
2412
)
2413
{
2414
u8 i = 0;
2415
BOOLEAN bIn24G = _TRUE;
2416
2417
if (Channel <= 14) {
2418
bIn24G = _TRUE;
2419
*ChannelIdx = Channel - 1;
2420
} else {
2421
bIn24G = _FALSE;
2422
2423
for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) {
2424
if (center_ch_5g_all[i] == Channel) {
2425
*ChannelIdx = i;
2426
return bIn24G;
2427
}
2428
}
2429
}
2430
2431
return bIn24G;
2432
}
2433
2434
#ifndef CONFIG_USE_TSSI
2435
u8 phy_get_pg_txpwr_idx(
2436
PADAPTER pAdapter,
2437
enum rf_path RFPath,
2438
u8 Rate,
2439
u8 ntx_idx,
2440
enum channel_width BandWidth,
2441
u8 Channel,
2442
PBOOLEAN bIn24G
2443
)
2444
{
2445
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
2446
u8 i = 0; /* default set to 1S */
2447
u8 txPower = 0;
2448
u8 chnlIdx = (Channel - 1);
2449
2450
if (HAL_IsLegalChannel(pAdapter, Channel) == _FALSE) {
2451
chnlIdx = 0;
2452
RTW_INFO("Illegal channel!!\n");
2453
}
2454
2455
*bIn24G = phy_GetChnlIndex(Channel, &chnlIdx);
2456
2457
if (0)
2458
RTW_INFO("[%s] Channel Index: %d\n", (*bIn24G ? "2.4G" : "5G"), chnlIdx);
2459
2460
if (*bIn24G) {
2461
if (IS_CCK_RATE(Rate)) {
2462
/* CCK-nTX */
2463
txPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx];
2464
txPower += pHalData->CCK_24G_Diff[RFPath][RF_1TX];
2465
if (ntx_idx >= RF_2TX)
2466
txPower += pHalData->CCK_24G_Diff[RFPath][RF_2TX];
2467
if (ntx_idx >= RF_3TX)
2468
txPower += pHalData->CCK_24G_Diff[RFPath][RF_3TX];
2469
if (ntx_idx >= RF_4TX)
2470
txPower += pHalData->CCK_24G_Diff[RFPath][RF_4TX];
2471
goto exit;
2472
}
2473
2474
txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx];
2475
2476
/* OFDM-nTX */
2477
if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) {
2478
txPower += pHalData->OFDM_24G_Diff[RFPath][RF_1TX];
2479
if (ntx_idx >= RF_2TX)
2480
txPower += pHalData->OFDM_24G_Diff[RFPath][RF_2TX];
2481
if (ntx_idx >= RF_3TX)
2482
txPower += pHalData->OFDM_24G_Diff[RFPath][RF_3TX];
2483
if (ntx_idx >= RF_4TX)
2484
txPower += pHalData->OFDM_24G_Diff[RFPath][RF_4TX];
2485
goto exit;
2486
}
2487
2488
/* BW20-nS */
2489
if (BandWidth == CHANNEL_WIDTH_20) {
2490
if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2491
txPower += pHalData->BW20_24G_Diff[RFPath][RF_1TX];
2492
if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2493
txPower += pHalData->BW20_24G_Diff[RFPath][RF_2TX];
2494
if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2495
txPower += pHalData->BW20_24G_Diff[RFPath][RF_3TX];
2496
if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2497
txPower += pHalData->BW20_24G_Diff[RFPath][RF_4TX];
2498
goto exit;
2499
}
2500
2501
/* BW40-nS */
2502
if (BandWidth == CHANNEL_WIDTH_40) {
2503
if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2504
txPower += pHalData->BW40_24G_Diff[RFPath][RF_1TX];
2505
if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2506
txPower += pHalData->BW40_24G_Diff[RFPath][RF_2TX];
2507
if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2508
txPower += pHalData->BW40_24G_Diff[RFPath][RF_3TX];
2509
if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2510
txPower += pHalData->BW40_24G_Diff[RFPath][RF_4TX];
2511
goto exit;
2512
}
2513
2514
/* Willis suggest adopt BW 40M power index while in BW 80 mode */
2515
if (BandWidth == CHANNEL_WIDTH_80) {
2516
if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2517
txPower += pHalData->BW40_24G_Diff[RFPath][RF_1TX];
2518
if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2519
txPower += pHalData->BW40_24G_Diff[RFPath][RF_2TX];
2520
if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2521
txPower += pHalData->BW40_24G_Diff[RFPath][RF_3TX];
2522
if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2523
txPower += pHalData->BW40_24G_Diff[RFPath][RF_4TX];
2524
goto exit;
2525
}
2526
}
2527
#ifdef CONFIG_IEEE80211_BAND_5GHZ
2528
else {
2529
if (Rate >= MGN_6M)
2530
txPower = pHalData->Index5G_BW40_Base[RFPath][chnlIdx];
2531
else {
2532
RTW_INFO("===>%s: INVALID Rate(0x%02x).\n", __func__, Rate);
2533
goto exit;
2534
}
2535
2536
/* OFDM-nTX */
2537
if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) {
2538
txPower += pHalData->OFDM_5G_Diff[RFPath][RF_1TX];
2539
if (ntx_idx >= RF_2TX)
2540
txPower += pHalData->OFDM_5G_Diff[RFPath][RF_2TX];
2541
if (ntx_idx >= RF_3TX)
2542
txPower += pHalData->OFDM_5G_Diff[RFPath][RF_3TX];
2543
if (ntx_idx >= RF_4TX)
2544
txPower += pHalData->OFDM_5G_Diff[RFPath][RF_4TX];
2545
goto exit;
2546
}
2547
2548
/* BW20-nS */
2549
if (BandWidth == CHANNEL_WIDTH_20) {
2550
if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2551
txPower += pHalData->BW20_5G_Diff[RFPath][RF_1TX];
2552
if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2553
txPower += pHalData->BW20_5G_Diff[RFPath][RF_2TX];
2554
if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2555
txPower += pHalData->BW20_5G_Diff[RFPath][RF_3TX];
2556
if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2557
txPower += pHalData->BW20_5G_Diff[RFPath][RF_4TX];
2558
goto exit;
2559
}
2560
2561
/* BW40-nS */
2562
if (BandWidth == CHANNEL_WIDTH_40) {
2563
if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2564
txPower += pHalData->BW40_5G_Diff[RFPath][RF_1TX];
2565
if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2566
txPower += pHalData->BW40_5G_Diff[RFPath][RF_2TX];
2567
if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2568
txPower += pHalData->BW40_5G_Diff[RFPath][RF_3TX];
2569
if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2570
txPower += pHalData->BW40_5G_Diff[RFPath][RF_4TX];
2571
goto exit;
2572
}
2573
2574
/* BW80-nS */
2575
if (BandWidth == CHANNEL_WIDTH_80) {
2576
/* get 80MHz cch index */
2577
for (i = 0; i < CENTER_CH_5G_80M_NUM; ++i) {
2578
if (center_ch_5g_80m[i] == Channel) {
2579
chnlIdx = i;
2580
break;
2581
}
2582
}
2583
if (i >= CENTER_CH_5G_80M_NUM) {
2584
#ifdef CONFIG_MP_INCLUDED
2585
if (rtw_mp_mode_check(pAdapter) == _FALSE)
2586
#endif
2587
rtw_warn_on(1);
2588
txPower = 0;
2589
goto exit;
2590
}
2591
2592
txPower = pHalData->Index5G_BW80_Base[RFPath][chnlIdx];
2593
2594
if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2595
txPower += + pHalData->BW80_5G_Diff[RFPath][RF_1TX];
2596
if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2597
txPower += pHalData->BW80_5G_Diff[RFPath][RF_2TX];
2598
if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2599
txPower += pHalData->BW80_5G_Diff[RFPath][RF_3TX];
2600
if ((MGN_MCS23 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
2601
txPower += pHalData->BW80_5G_Diff[RFPath][RF_4TX];
2602
goto exit;
2603
}
2604
2605
/* TODO: BW160-nS */
2606
rtw_warn_on(1);
2607
}
2608
#endif /* CONFIG_IEEE80211_BAND_5GHZ */
2609
2610
exit:
2611
return txPower;
2612
}
2613
#endif /* CONFIG_USE_TSSI */
2614
2615
s8
2616
PHY_GetTxPowerTrackingOffset(
2617
PADAPTER pAdapter,
2618
enum rf_path RFPath,
2619
u8 Rate
2620
)
2621
{
2622
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
2623
struct dm_struct *pDM_Odm = &pHalData->odmpriv;
2624
s8 offset = 0;
2625
2626
if (pDM_Odm->rf_calibrate_info.txpowertrack_control == _FALSE)
2627
return offset;
2628
2629
if ((Rate == MGN_1M) || (Rate == MGN_2M) || (Rate == MGN_5_5M) || (Rate == MGN_11M)) {
2630
offset = pDM_Odm->rf_calibrate_info.remnant_cck_swing_idx;
2631
/*RTW_INFO("+Remnant_CCKSwingIdx = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_CCKSwingIdx);*/
2632
} else {
2633
offset = pDM_Odm->rf_calibrate_info.remnant_ofdm_swing_idx[RFPath];
2634
/*RTW_INFO("+Remanant_OFDMSwingIdx[RFPath %u][Rate 0x%x] = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]); */
2635
2636
}
2637
2638
return offset;
2639
}
2640
2641
/*The same as MRateToHwRate in hal_com.c*/
2642
u8
2643
PHY_GetRateIndexOfTxPowerByRate(
2644
u8 Rate
2645
)
2646
{
2647
u8 index = 0;
2648
switch (Rate) {
2649
case MGN_1M:
2650
index = 0;
2651
break;
2652
case MGN_2M:
2653
index = 1;
2654
break;
2655
case MGN_5_5M:
2656
index = 2;
2657
break;
2658
case MGN_11M:
2659
index = 3;
2660
break;
2661
case MGN_6M:
2662
index = 4;
2663
break;
2664
case MGN_9M:
2665
index = 5;
2666
break;
2667
case MGN_12M:
2668
index = 6;
2669
break;
2670
case MGN_18M:
2671
index = 7;
2672
break;
2673
case MGN_24M:
2674
index = 8;
2675
break;
2676
case MGN_36M:
2677
index = 9;
2678
break;
2679
case MGN_48M:
2680
index = 10;
2681
break;
2682
case MGN_54M:
2683
index = 11;
2684
break;
2685
case MGN_MCS0:
2686
index = 12;
2687
break;
2688
case MGN_MCS1:
2689
index = 13;
2690
break;
2691
case MGN_MCS2:
2692
index = 14;
2693
break;
2694
case MGN_MCS3:
2695
index = 15;
2696
break;
2697
case MGN_MCS4:
2698
index = 16;
2699
break;
2700
case MGN_MCS5:
2701
index = 17;
2702
break;
2703
case MGN_MCS6:
2704
index = 18;
2705
break;
2706
case MGN_MCS7:
2707
index = 19;
2708
break;
2709
case MGN_MCS8:
2710
index = 20;
2711
break;
2712
case MGN_MCS9:
2713
index = 21;
2714
break;
2715
case MGN_MCS10:
2716
index = 22;
2717
break;
2718
case MGN_MCS11:
2719
index = 23;
2720
break;
2721
case MGN_MCS12:
2722
index = 24;
2723
break;
2724
case MGN_MCS13:
2725
index = 25;
2726
break;
2727
case MGN_MCS14:
2728
index = 26;
2729
break;
2730
case MGN_MCS15:
2731
index = 27;
2732
break;
2733
case MGN_MCS16:
2734
index = 28;
2735
break;
2736
case MGN_MCS17:
2737
index = 29;
2738
break;
2739
case MGN_MCS18:
2740
index = 30;
2741
break;
2742
case MGN_MCS19:
2743
index = 31;
2744
break;
2745
case MGN_MCS20:
2746
index = 32;
2747
break;
2748
case MGN_MCS21:
2749
index = 33;
2750
break;
2751
case MGN_MCS22:
2752
index = 34;
2753
break;
2754
case MGN_MCS23:
2755
index = 35;
2756
break;
2757
case MGN_MCS24:
2758
index = 36;
2759
break;
2760
case MGN_MCS25:
2761
index = 37;
2762
break;
2763
case MGN_MCS26:
2764
index = 38;
2765
break;
2766
case MGN_MCS27:
2767
index = 39;
2768
break;
2769
case MGN_MCS28:
2770
index = 40;
2771
break;
2772
case MGN_MCS29:
2773
index = 41;
2774
break;
2775
case MGN_MCS30:
2776
index = 42;
2777
break;
2778
case MGN_MCS31:
2779
index = 43;
2780
break;
2781
case MGN_VHT1SS_MCS0:
2782
index = 44;
2783
break;
2784
case MGN_VHT1SS_MCS1:
2785
index = 45;
2786
break;
2787
case MGN_VHT1SS_MCS2:
2788
index = 46;
2789
break;
2790
case MGN_VHT1SS_MCS3:
2791
index = 47;
2792
break;
2793
case MGN_VHT1SS_MCS4:
2794
index = 48;
2795
break;
2796
case MGN_VHT1SS_MCS5:
2797
index = 49;
2798
break;
2799
case MGN_VHT1SS_MCS6:
2800
index = 50;
2801
break;
2802
case MGN_VHT1SS_MCS7:
2803
index = 51;
2804
break;
2805
case MGN_VHT1SS_MCS8:
2806
index = 52;
2807
break;
2808
case MGN_VHT1SS_MCS9:
2809
index = 53;
2810
break;
2811
case MGN_VHT2SS_MCS0:
2812
index = 54;
2813
break;
2814
case MGN_VHT2SS_MCS1:
2815
index = 55;
2816
break;
2817
case MGN_VHT2SS_MCS2:
2818
index = 56;
2819
break;
2820
case MGN_VHT2SS_MCS3:
2821
index = 57;
2822
break;
2823
case MGN_VHT2SS_MCS4:
2824
index = 58;
2825
break;
2826
case MGN_VHT2SS_MCS5:
2827
index = 59;
2828
break;
2829
case MGN_VHT2SS_MCS6:
2830
index = 60;
2831
break;
2832
case MGN_VHT2SS_MCS7:
2833
index = 61;
2834
break;
2835
case MGN_VHT2SS_MCS8:
2836
index = 62;
2837
break;
2838
case MGN_VHT2SS_MCS9:
2839
index = 63;
2840
break;
2841
case MGN_VHT3SS_MCS0:
2842
index = 64;
2843
break;
2844
case MGN_VHT3SS_MCS1:
2845
index = 65;
2846
break;
2847
case MGN_VHT3SS_MCS2:
2848
index = 66;
2849
break;
2850
case MGN_VHT3SS_MCS3:
2851
index = 67;
2852
break;
2853
case MGN_VHT3SS_MCS4:
2854
index = 68;
2855
break;
2856
case MGN_VHT3SS_MCS5:
2857
index = 69;
2858
break;
2859
case MGN_VHT3SS_MCS6:
2860
index = 70;
2861
break;
2862
case MGN_VHT3SS_MCS7:
2863
index = 71;
2864
break;
2865
case MGN_VHT3SS_MCS8:
2866
index = 72;
2867
break;
2868
case MGN_VHT3SS_MCS9:
2869
index = 73;
2870
break;
2871
case MGN_VHT4SS_MCS0:
2872
index = 74;
2873
break;
2874
case MGN_VHT4SS_MCS1:
2875
index = 75;
2876
break;
2877
case MGN_VHT4SS_MCS2:
2878
index = 76;
2879
break;
2880
case MGN_VHT4SS_MCS3:
2881
index = 77;
2882
break;
2883
case MGN_VHT4SS_MCS4:
2884
index = 78;
2885
break;
2886
case MGN_VHT4SS_MCS5:
2887
index = 79;
2888
break;
2889
case MGN_VHT4SS_MCS6:
2890
index = 80;
2891
break;
2892
case MGN_VHT4SS_MCS7:
2893
index = 81;
2894
break;
2895
case MGN_VHT4SS_MCS8:
2896
index = 82;
2897
break;
2898
case MGN_VHT4SS_MCS9:
2899
index = 83;
2900
break;
2901
default:
2902
RTW_INFO("Invalid rate 0x%x in %s\n", Rate, __FUNCTION__);
2903
break;
2904
};
2905
2906
return index;
2907
}
2908
2909
#ifdef CONFIG_USE_TSSI
2910
s8 PHY_GetTxPowerByRateOriginal(
2911
PADAPTER pAdapter,
2912
u8 Band,
2913
enum rf_path RFPath,
2914
u8 Rate
2915
)
2916
{
2917
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2918
s8 value = 0;
2919
u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
2920
2921
if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
2922
RTW_INFO("Invalid band %d in %s\n", Band, __func__);
2923
goto exit;
2924
}
2925
if (RFPath > RF_PATH_D) {
2926
RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __func__);
2927
goto exit;
2928
}
2929
if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) {
2930
RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __func__);
2931
goto exit;
2932
}
2933
2934
value = pHalData->TxPwrByRate[Band][RFPath][rateIndex];
2935
2936
exit:
2937
return value;
2938
}
2939
#endif /* CONFIG_USE_TSSI */
2940
2941
s8
2942
_PHY_GetTxPowerByRate(
2943
PADAPTER pAdapter,
2944
u8 Band,
2945
enum rf_path RFPath,
2946
u8 Rate
2947
)
2948
{
2949
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2950
s8 value = 0;
2951
u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
2952
2953
if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
2954
RTW_INFO("Invalid band %d in %s\n", Band, __func__);
2955
goto exit;
2956
}
2957
if (RFPath > RF_PATH_D) {
2958
RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __func__);
2959
goto exit;
2960
}
2961
if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) {
2962
RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __func__);
2963
goto exit;
2964
}
2965
2966
value = pHalData->TxPwrByRateOffset[Band][RFPath][rateIndex];
2967
2968
exit:
2969
return value;
2970
}
2971
2972
2973
s8
2974
PHY_GetTxPowerByRate(
2975
PADAPTER pAdapter,
2976
u8 Band,
2977
enum rf_path RFPath,
2978
u8 Rate
2979
)
2980
{
2981
if (!phy_is_tx_power_by_rate_needed(pAdapter))
2982
return 0;
2983
2984
return _PHY_GetTxPowerByRate(pAdapter, Band, RFPath, Rate);
2985
}
2986
2987
void
2988
PHY_SetTxPowerByRate(
2989
PADAPTER pAdapter,
2990
u8 Band,
2991
enum rf_path RFPath,
2992
u8 Rate,
2993
s8 Value
2994
)
2995
{
2996
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2997
u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
2998
2999
if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
3000
RTW_INFO("Invalid band %d in %s\n", Band, __FUNCTION__);
3001
return;
3002
}
3003
if (RFPath > RF_PATH_D) {
3004
RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __FUNCTION__);
3005
return;
3006
}
3007
if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) {
3008
RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __FUNCTION__);
3009
return;
3010
}
3011
3012
pHalData->TxPwrByRateOffset[Band][RFPath][rateIndex] = Value;
3013
}
3014
3015
u8 phy_check_under_survey_ch(_adapter *adapter)
3016
{
3017
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
3018
_adapter *iface;
3019
struct mlme_ext_priv *mlmeext;
3020
u8 ret = _FALSE;
3021
int i;
3022
3023
for (i = 0; i < dvobj->iface_nums; i++) {
3024
iface = dvobj->padapters[i];
3025
if (!iface)
3026
continue;
3027
mlmeext = &iface->mlmeextpriv;
3028
3029
/* check scan state */
3030
if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE
3031
&& mlmeext_scan_state(mlmeext) != SCAN_COMPLETE
3032
&& mlmeext_scan_state(mlmeext) != SCAN_BACKING_OP) {
3033
ret = _TRUE;
3034
} else if (mlmeext_scan_state(mlmeext) == SCAN_BACKING_OP
3035
&& !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME)) {
3036
ret = _TRUE;
3037
}
3038
}
3039
3040
return ret;
3041
}
3042
3043
void
3044
phy_set_tx_power_level_by_path(
3045
PADAPTER Adapter,
3046
u8 channel,
3047
u8 path
3048
)
3049
{
3050
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
3051
BOOLEAN bIsIn24G = (pHalData->current_band_type == BAND_ON_2_4G);
3052
u8 under_survey_ch = phy_check_under_survey_ch(Adapter);
3053
3054
3055
/* if ( pMgntInfo->RegNByteAccess == 0 ) */
3056
{
3057
if (bIsIn24G)
3058
phy_set_tx_power_index_by_rate_section(Adapter, path, channel, CCK);
3059
3060
phy_set_tx_power_index_by_rate_section(Adapter, path, channel, OFDM);
3061
3062
if (!under_survey_ch) {
3063
phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS0_MCS7);
3064
3065
if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))
3066
phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_1SSMCS0_1SSMCS9);
3067
3068
if (pHalData->NumTotalRFPath >= 2) {
3069
phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS8_MCS15);
3070
3071
if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))
3072
phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_2SSMCS0_2SSMCS9);
3073
3074
if (IS_HARDWARE_TYPE_8814A(Adapter)) {
3075
phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS16_MCS23);
3076
phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_3SSMCS0_3SSMCS9);
3077
}
3078
}
3079
}
3080
}
3081
}
3082
3083
#ifndef DBG_TX_POWER_IDX
3084
#define DBG_TX_POWER_IDX 0
3085
#endif
3086
3087
void
3088
PHY_SetTxPowerIndexByRateArray(
3089
PADAPTER pAdapter,
3090
enum rf_path RFPath,
3091
enum channel_width BandWidth,
3092
u8 Channel,
3093
u8 *Rates,
3094
u8 RateArraySize
3095
)
3096
{
3097
u32 powerIndex = 0;
3098
int i = 0;
3099
3100
for (i = 0; i < RateArraySize; ++i) {
3101
#if DBG_TX_POWER_IDX
3102
struct txpwr_idx_comp tic;
3103
3104
powerIndex = rtw_hal_get_tx_power_index(pAdapter, RFPath, Rates[i], BandWidth, Channel, &tic);
3105
RTW_INFO("TXPWR: [%c][%s]ch:%u, %s %uT, pwr_idx:%u(0x%02x) = %u + (%d=%d:%d) + (%d) + (%d) + (%d) + (%d)\n"
3106
, rf_path_char(RFPath), ch_width_str(BandWidth), Channel, MGN_RATE_STR(Rates[i]), tic.ntx_idx + 1
3107
, powerIndex, powerIndex, tic.pg, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt
3108
, tic.ebias, tic.btc, tic.dpd);
3109
#else
3110
powerIndex = phy_get_tx_power_index(pAdapter, RFPath, Rates[i], BandWidth, Channel);
3111
#endif
3112
PHY_SetTxPowerIndex(pAdapter, powerIndex, RFPath, Rates[i]);
3113
}
3114
}
3115
3116
#if CONFIG_TXPWR_LIMIT
3117
const char *const _txpwr_lmt_rs_str[] = {
3118
"CCK",
3119
"OFDM",
3120
"HT",
3121
"VHT",
3122
"UNKNOWN",
3123
};
3124
3125
static s8
3126
phy_GetChannelIndexOfTxPowerLimit(
3127
u8 Band,
3128
u8 Channel
3129
)
3130
{
3131
s8 channelIndex = -1;
3132
u8 i = 0;
3133
3134
if (Band == BAND_ON_2_4G)
3135
channelIndex = Channel - 1;
3136
else if (Band == BAND_ON_5G) {
3137
for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) {
3138
if (center_ch_5g_all[i] == Channel)
3139
channelIndex = i;
3140
}
3141
} else
3142
RTW_PRINT("Invalid Band %d in %s\n", Band, __func__);
3143
3144
if (channelIndex == -1)
3145
RTW_PRINT("Invalid Channel %d of Band %d in %s\n", Channel, Band, __func__);
3146
3147
return channelIndex;
3148
}
3149
3150
static s8 phy_txpwr_ww_lmt_value(_adapter *adapter)
3151
{
3152
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
3153
3154
if (hal_spec->txgi_max == 63)
3155
return -63;
3156
else if (hal_spec->txgi_max == 127)
3157
return -128;
3158
3159
rtw_warn_on(1);
3160
return -128;
3161
}
3162
3163
/*
3164
* return txpwr limit absolute value
3165
* hsl_spec->txgi_max is returned when NO limit
3166
*/
3167
s8 phy_get_txpwr_lmt_abs(
3168
PADAPTER Adapter,
3169
const char *regd_name,
3170
BAND_TYPE Band,
3171
enum channel_width bw,
3172
u8 tlrs,
3173
u8 ntx_idx,
3174
u8 cch,
3175
u8 lock
3176
)
3177
{
3178
struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);
3179
struct rf_ctl_t *rfctl = adapter_to_rfctl(Adapter);
3180
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(Adapter);
3181
struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
3182
struct txpwr_lmt_ent *ent = NULL;
3183
_irqL irqL;
3184
_list *cur, *head;
3185
s8 ch_idx;
3186
u8 is_ww_regd = 0;
3187
s8 ww_lmt_val = phy_txpwr_ww_lmt_value(Adapter);
3188
s8 lmt = hal_spec->txgi_max;
3189
3190
if ((Adapter->registrypriv.RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory != 1) ||
3191
Adapter->registrypriv.RegEnableTxPowerLimit == 0)
3192
goto exit;
3193
3194
if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
3195
RTW_ERR("%s invalid band:%u\n", __func__, Band);
3196
rtw_warn_on(1);
3197
goto exit;
3198
}
3199
3200
if (Band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK) {
3201
RTW_ERR("5G has no CCK\n");
3202
goto exit;
3203
}
3204
3205
if (lock)
3206
_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
3207
3208
if (!regd_name) /* no regd_name specified, use currnet */
3209
regd_name = rfctl->regd_name;
3210
3211
if (rfctl->txpwr_regd_num == 0
3212
|| strcmp(regd_name, regd_str(TXPWR_LMT_NONE)) == 0)
3213
goto release_lock;
3214
3215
if (strcmp(regd_name, regd_str(TXPWR_LMT_WW)) == 0)
3216
is_ww_regd = 1;
3217
3218
if (!is_ww_regd) {
3219
ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name);
3220
if (!ent)
3221
goto release_lock;
3222
}
3223
3224
ch_idx = phy_GetChannelIndexOfTxPowerLimit(Band, cch);
3225
if (ch_idx == -1)
3226
goto release_lock;
3227
3228
if (Band == BAND_ON_2_4G) {
3229
if (!is_ww_regd) {
3230
lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx];
3231
if (lmt != ww_lmt_val)
3232
goto release_lock;
3233
}
3234
3235
/* search for min value for WW regd or WW limit */
3236
lmt = hal_spec->txgi_max;
3237
head = &rfctl->txpwr_lmt_list;
3238
cur = get_next(head);
3239
while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
3240
ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
3241
cur = get_next(cur);
3242
if (ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] != ww_lmt_val)
3243
lmt = rtw_min(lmt, ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx]);
3244
}
3245
}
3246
#ifdef CONFIG_IEEE80211_BAND_5GHZ
3247
else if (Band == BAND_ON_5G) {
3248
if (!is_ww_regd) {
3249
lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx];
3250
if (lmt != ww_lmt_val)
3251
goto release_lock;
3252
}
3253
3254
/* search for min value for WW regd or WW limit */
3255
lmt = hal_spec->txgi_max;
3256
head = &rfctl->txpwr_lmt_list;
3257
cur = get_next(head);
3258
while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
3259
ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
3260
cur = get_next(cur);
3261
if (ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] != ww_lmt_val)
3262
lmt = rtw_min(lmt, ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx]);
3263
}
3264
}
3265
#endif
3266
3267
release_lock:
3268
if (lock)
3269
_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
3270
3271
exit:
3272
return lmt;
3273
}
3274
3275
/*
3276
* return txpwr limit diff value
3277
* hal_spec->txgi_max is returned when NO limit
3278
*/
3279
inline s8 phy_get_txpwr_lmt(_adapter *adapter
3280
, const char *regd_name
3281
, BAND_TYPE band, enum channel_width bw
3282
, u8 rfpath, u8 rs, u8 ntx_idx, u8 cch, u8 lock
3283
)
3284
{
3285
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
3286
u8 tlrs;
3287
s8 lmt = hal_spec->txgi_max;
3288
3289
if (IS_CCK_RATE_SECTION(rs))
3290
tlrs = TXPWR_LMT_RS_CCK;
3291
else if (IS_OFDM_RATE_SECTION(rs))
3292
tlrs = TXPWR_LMT_RS_OFDM;
3293
else if (IS_HT_RATE_SECTION(rs))
3294
tlrs = TXPWR_LMT_RS_HT;
3295
else if (IS_VHT_RATE_SECTION(rs))
3296
tlrs = TXPWR_LMT_RS_VHT;
3297
else {
3298
RTW_ERR("%s invalid rs %u\n", __func__, rs);
3299
rtw_warn_on(1);
3300
goto exit;
3301
}
3302
3303
lmt = phy_get_txpwr_lmt_abs(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock);
3304
3305
if (lmt != hal_spec->txgi_max) {
3306
/* return diff value */
3307
#ifdef CONFIG_USE_TSSI
3308
lmt = lmt - PHY_GetTxPowerByRateOriginal(adapter, band, rfpath, MGN_MCS7);
3309
#else
3310
lmt = lmt - PHY_GetTxPowerByRateBase(adapter, band, rfpath, rs);
3311
#endif
3312
}
3313
3314
exit:
3315
return lmt;
3316
}
3317
3318
#ifdef CONFIG_USE_TSSI
3319
static
3320
s8 PHY_GetTxPowerLimitOriginal(_adapter *adapter
3321
, const char *regd_name
3322
, BAND_TYPE band, enum channel_width bw
3323
, u8 rfpath, u8 rate, u8 ntx_idx, u8 cch
3324
)
3325
{
3326
/* input may be ch=155 bw=2 for OFDM */
3327
s8 lmt;
3328
3329
lmt = _PHY_GetTxPowerLimit(adapter, regd_name, band, bw, rfpath, rate, ntx_idx, cch, true);
3330
3331
return lmt;
3332
}
3333
#endif
3334
3335
/*
3336
* May search for secondary channels for min limit
3337
* return txpwr limit diff value
3338
*/
3339
s8
3340
_PHY_GetTxPowerLimit(_adapter *adapter
3341
, const char *regd_name
3342
, BAND_TYPE band, enum channel_width bw
3343
, u8 rfpath, u8 rate, u8 ntx_idx, u8 cch, bool orig)
3344
{
3345
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
3346
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
3347
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
3348
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
3349
BOOLEAN no_sc = _FALSE;
3350
s8 tlrs = -1, rs = -1;
3351
s8 lmt = hal_spec->txgi_max;
3352
u8 tmp_cch = 0;
3353
u8 tmp_bw;
3354
u8 bw_bmp = 0;
3355
s8 min_lmt = hal_spec->txgi_max;
3356
u8 final_bw = bw, final_cch = cch;
3357
_irqL irqL;
3358
3359
#ifdef CONFIG_MP_INCLUDED
3360
/* MP mode channel don't use secondary channel */
3361
if (rtw_mp_mode_check(adapter) == _TRUE)
3362
no_sc = _TRUE;
3363
#endif
3364
if (IS_CCK_RATE(rate)) {
3365
tlrs = TXPWR_LMT_RS_CCK;
3366
rs = CCK;
3367
} else if (IS_OFDM_RATE(rate)) {
3368
tlrs = TXPWR_LMT_RS_OFDM;
3369
rs = OFDM;
3370
} else if (IS_HT_RATE(rate)) {
3371
tlrs = TXPWR_LMT_RS_HT;
3372
rs = HT_1SS + (IS_HT1SS_RATE(rate) ? 0 : IS_HT2SS_RATE(rate) ? 1 : IS_HT3SS_RATE(rate) ? 2 : IS_HT4SS_RATE(rate) ? 3 : 0);
3373
} else if (IS_VHT_RATE(rate)) {
3374
tlrs = TXPWR_LMT_RS_VHT;
3375
rs = VHT_1SS + (IS_VHT1SS_RATE(rate) ? 0 : IS_VHT2SS_RATE(rate) ? 1 : IS_VHT3SS_RATE(rate) ? 2 : IS_VHT4SS_RATE(rate) ? 3 : 0);
3376
} else {
3377
RTW_ERR("%s invalid rate 0x%x\n", __func__, rate);
3378
rtw_warn_on(1);
3379
goto exit;
3380
}
3381
3382
if (no_sc == _TRUE) {
3383
/* use the input center channel and bandwidth directly */
3384
tmp_cch = cch;
3385
bw_bmp = ch_width_to_bw_cap(bw);
3386
} else {
3387
/*
3388
* find the possible tx bandwidth bmp for this rate, and then will get center channel for each bandwidth
3389
* if no possible tx bandwidth bmp, select valid bandwidth up to current RF bandwidth into bmp
3390
*/
3391
if (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM)
3392
bw_bmp = BW_CAP_20M; /* CCK, OFDM only BW 20M */
3393
else if (tlrs == TXPWR_LMT_RS_HT) {
3394
bw_bmp = rtw_get_tx_bw_bmp_of_ht_rate(dvobj, rate, bw);
3395
if (bw_bmp == 0)
3396
bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_40 ? CHANNEL_WIDTH_40 : bw);
3397
} else if (tlrs == TXPWR_LMT_RS_VHT) {
3398
bw_bmp = rtw_get_tx_bw_bmp_of_vht_rate(dvobj, rate, bw);
3399
if (bw_bmp == 0)
3400
bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_160 ? CHANNEL_WIDTH_160 : bw);
3401
} else
3402
rtw_warn_on(1);
3403
}
3404
3405
if (bw_bmp == 0)
3406
goto exit;
3407
3408
_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
3409
3410
/* loop for each possible tx bandwidth to find minimum limit */
3411
for (tmp_bw = CHANNEL_WIDTH_20; tmp_bw <= bw; tmp_bw++) {
3412
if (!(ch_width_to_bw_cap(tmp_bw) & bw_bmp))
3413
continue;
3414
3415
if (no_sc == _FALSE) {
3416
if (tmp_bw == CHANNEL_WIDTH_20)
3417
tmp_cch = hal_data->cch_20;
3418
else if (tmp_bw == CHANNEL_WIDTH_40)
3419
tmp_cch = hal_data->cch_40;
3420
else if (tmp_bw == CHANNEL_WIDTH_80)
3421
tmp_cch = hal_data->cch_80;
3422
else {
3423
tmp_cch = 0;
3424
rtw_warn_on(1);
3425
}
3426
}
3427
3428
lmt = phy_get_txpwr_lmt_abs(adapter, regd_name, band, tmp_bw, tlrs, ntx_idx, tmp_cch, 0);
3429
3430
if (min_lmt >= lmt) {
3431
min_lmt = lmt;
3432
final_cch = tmp_cch;
3433
final_bw = tmp_bw;
3434
}
3435
3436
}
3437
3438
_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
3439
3440
if (!orig && min_lmt != hal_spec->txgi_max) {
3441
/* return diff value */
3442
#ifdef CONFIG_USE_TSSI
3443
min_lmt = min_lmt - PHY_GetTxPowerByRateOriginal(adapter, band, rfpath, MGN_MCS7);
3444
#else
3445
min_lmt = min_lmt - PHY_GetTxPowerByRateBase(adapter, band, rfpath, rs);
3446
#endif
3447
}
3448
3449
exit:
3450
3451
if (0) {
3452
if (final_bw != bw && (IS_HT_RATE(rate) || IS_VHT_RATE(rate)))
3453
RTW_INFO("%s min_lmt: %s ch%u -> %s ch%u\n"
3454
, MGN_RATE_STR(rate)
3455
, ch_width_str(bw), cch
3456
, ch_width_str(final_bw), final_cch);
3457
}
3458
3459
return min_lmt;
3460
}
3461
3462
static void phy_txpwr_lmt_cck_ofdm_mt_chk(_adapter *adapter)
3463
{
3464
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
3465
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
3466
struct txpwr_lmt_ent *ent;
3467
_list *cur, *head;
3468
u8 channel, tlrs, ntx_idx;
3469
3470
rfctl->txpwr_lmt_2g_cck_ofdm_state = 0;
3471
#ifdef CONFIG_IEEE80211_BAND_5GHZ
3472
rfctl->txpwr_lmt_5g_cck_ofdm_state = 0;
3473
#endif
3474
3475
head = &rfctl->txpwr_lmt_list;
3476
cur = get_next(head);
3477
3478
while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
3479
ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
3480
cur = get_next(cur);
3481
3482
/* check 2G CCK, OFDM state*/
3483
for (tlrs = TXPWR_LMT_RS_CCK; tlrs <= TXPWR_LMT_RS_OFDM; tlrs++) {
3484
for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
3485
for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) {
3486
if (ent->lmt_2g[CHANNEL_WIDTH_20][tlrs][channel][ntx_idx] != hal_spec->txgi_max) {
3487
if (tlrs == TXPWR_LMT_RS_CCK)
3488
rfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_CCK_1T << ntx_idx;
3489
else
3490
rfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx;
3491
break;
3492
}
3493
}
3494
}
3495
}
3496
3497
/* if 2G OFDM multi-TX is not defined, reference HT20 */
3498
for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) {
3499
for (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
3500
if (rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))
3501
continue;
3502
ent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM][channel][ntx_idx] =
3503
ent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT][channel][ntx_idx];
3504
}
3505
}
3506
3507
#ifdef CONFIG_IEEE80211_BAND_5GHZ
3508
/* check 5G OFDM state*/
3509
for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
3510
for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
3511
if (ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] != hal_spec->txgi_max) {
3512
rfctl->txpwr_lmt_5g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx;
3513
break;
3514
}
3515
}
3516
}
3517
3518
for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
3519
for (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
3520
if (rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))
3521
continue;
3522
/* if 5G OFDM multi-TX is not defined, reference HT20 */
3523
ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] =
3524
ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT - 1][channel][ntx_idx];
3525
}
3526
}
3527
#endif /* CONFIG_IEEE80211_BAND_5GHZ */
3528
}
3529
}
3530
3531
#ifdef CONFIG_IEEE80211_BAND_5GHZ
3532
static void phy_txpwr_lmt_cross_ref_ht_vht(_adapter *adapter)
3533
{
3534
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
3535
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
3536
struct txpwr_lmt_ent *ent;
3537
_list *cur, *head;
3538
u8 bw, channel, tlrs, ref_tlrs, ntx_idx;
3539
int ht_ref_vht_5g_20_40 = 0;
3540
int vht_ref_ht_5g_20_40 = 0;
3541
int ht_has_ref_5g_20_40 = 0;
3542
int vht_has_ref_5g_20_40 = 0;
3543
3544
rfctl->txpwr_lmt_5g_20_40_ref = 0;
3545
3546
head = &rfctl->txpwr_lmt_list;
3547
cur = get_next(head);
3548
3549
while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
3550
ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
3551
cur = get_next(cur);
3552
3553
for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {
3554
3555
for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
3556
3557
for (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; ++tlrs) {
3558
3559
/* 5G 20M 40M VHT and HT can cross reference */
3560
if (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40) {
3561
if (tlrs == TXPWR_LMT_RS_HT)
3562
ref_tlrs = TXPWR_LMT_RS_VHT;
3563
else if (tlrs == TXPWR_LMT_RS_VHT)
3564
ref_tlrs = TXPWR_LMT_RS_HT;
3565
else
3566
continue;
3567
3568
for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
3569
3570
if (ent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx] == hal_spec->txgi_max)
3571
continue;
3572
3573
if (tlrs == TXPWR_LMT_RS_HT)
3574
ht_has_ref_5g_20_40++;
3575
else if (tlrs == TXPWR_LMT_RS_VHT)
3576
vht_has_ref_5g_20_40++;
3577
else
3578
continue;
3579
3580
if (ent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] != hal_spec->txgi_max)
3581
continue;
3582
3583
if (tlrs == TXPWR_LMT_RS_HT && ref_tlrs == TXPWR_LMT_RS_VHT)
3584
ht_ref_vht_5g_20_40++;
3585
else if (tlrs == TXPWR_LMT_RS_VHT && ref_tlrs == TXPWR_LMT_RS_HT)
3586
vht_ref_ht_5g_20_40++;
3587
3588
if (0)
3589
RTW_INFO("reg:%s, bw:%u, ch:%u, %s-%uT ref %s-%uT\n"
3590
, ent->regd_name, bw, channel
3591
, txpwr_lmt_rs_str(tlrs), ntx_idx + 1
3592
, txpwr_lmt_rs_str(ref_tlrs), ntx_idx + 1);
3593
3594
ent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] =
3595
ent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx];
3596
}
3597
}
3598
3599
}
3600
}
3601
}
3602
}
3603
3604
if (0) {
3605
RTW_INFO("ht_ref_vht_5g_20_40:%d, ht_has_ref_5g_20_40:%d\n", ht_ref_vht_5g_20_40, ht_has_ref_5g_20_40);
3606
RTW_INFO("vht_ref_ht_5g_20_40:%d, vht_has_ref_5g_20_40:%d\n", vht_ref_ht_5g_20_40, vht_has_ref_5g_20_40);
3607
}
3608
3609
/* 5G 20M&40M HT all come from VHT*/
3610
if (ht_ref_vht_5g_20_40 && ht_has_ref_5g_20_40 == ht_ref_vht_5g_20_40)
3611
rfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_HT_FROM_VHT;
3612
3613
/* 5G 20M&40M VHT all come from HT*/
3614
if (vht_ref_ht_5g_20_40 && vht_has_ref_5g_20_40 == vht_ref_ht_5g_20_40)
3615
rfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_VHT_FROM_HT;
3616
}
3617
#endif /* CONFIG_IEEE80211_BAND_5GHZ */
3618
3619
#ifndef DBG_TXPWR_LMT_BAND_CHK
3620
#define DBG_TXPWR_LMT_BAND_CHK 0
3621
#endif
3622
3623
#if DBG_TXPWR_LMT_BAND_CHK
3624
/* check if larger bandwidth limit is less than smaller bandwidth for HT & VHT rate */
3625
void phy_txpwr_limit_bandwidth_chk(_adapter *adapter)
3626
{
3627
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
3628
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
3629
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
3630
u8 band, bw, path, tlrs, ntx_idx, cch, offset, scch;
3631
u8 ch_num, n, i;
3632
3633
for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
3634
if (!hal_is_band_support(adapter, band))
3635
continue;
3636
3637
for (bw = CHANNEL_WIDTH_40; bw <= CHANNEL_WIDTH_80; bw++) {
3638
if (bw >= CHANNEL_WIDTH_160)
3639
continue;
3640
if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80)
3641
continue;
3642
3643
if (band == BAND_ON_2_4G)
3644
ch_num = center_chs_2g_num(bw);
3645
else
3646
ch_num = center_chs_5g_num(bw);
3647
3648
if (ch_num == 0) {
3649
rtw_warn_on(1);
3650
break;
3651
}
3652
3653
for (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; tlrs++) {
3654
3655
if (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT)
3656
continue;
3657
if (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK)
3658
continue;
3659
if (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM))
3660
continue;
3661
if (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT)
3662
continue;
3663
if (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
3664
continue;
3665
3666
for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
3667
struct txpwr_lmt_ent *ent;
3668
_list *cur, *head;
3669
3670
if (ntx_idx + 1 > hal_data->max_tx_cnt)
3671
continue;
3672
3673
/* bypass CCK multi-TX is not defined */
3674
if (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) {
3675
if (band == BAND_ON_2_4G
3676
&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx)))
3677
continue;
3678
}
3679
3680
/* bypass OFDM multi-TX is not defined */
3681
if (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) {
3682
if (band == BAND_ON_2_4G
3683
&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
3684
continue;
3685
#ifdef CONFIG_IEEE80211_BAND_5GHZ
3686
if (band == BAND_ON_5G
3687
&& !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
3688
continue;
3689
#endif
3690
}
3691
3692
/* bypass 5G 20M, 40M pure reference */
3693
#ifdef CONFIG_IEEE80211_BAND_5GHZ
3694
if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) {
3695
if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) {
3696
if (tlrs == TXPWR_LMT_RS_HT)
3697
continue;
3698
} else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) {
3699
if (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40)
3700
continue;
3701
}
3702
}
3703
#endif
3704
3705
for (n = 0; n < ch_num; n++) {
3706
u8 cch_by_bw[3];
3707
u8 offset_by_bw; /* bitmap, 0 for lower, 1 for upper */
3708
u8 bw_pos;
3709
s8 lmt[3];
3710
3711
if (band == BAND_ON_2_4G)
3712
cch = center_chs_2g(bw, n);
3713
else
3714
cch = center_chs_5g(bw, n);
3715
3716
if (cch == 0) {
3717
rtw_warn_on(1);
3718
break;
3719
}
3720
3721
_rtw_memset(cch_by_bw, 0, 3);
3722
cch_by_bw[bw] = cch;
3723
offset_by_bw = 0x01;
3724
3725
do {
3726
for (bw_pos = bw; bw_pos >= CHANNEL_WIDTH_40; bw_pos--)
3727
cch_by_bw[bw_pos - 1] = rtw_get_scch_by_cch_offset(cch_by_bw[bw_pos], bw_pos, offset_by_bw & BIT(bw_pos) ? HAL_PRIME_CHNL_OFFSET_UPPER : HAL_PRIME_CHNL_OFFSET_LOWER);
3728
3729
head = &rfctl->txpwr_lmt_list;
3730
cur = get_next(head);
3731
while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
3732
ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
3733
cur = get_next(cur);
3734
3735
for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
3736
lmt[bw_pos] = phy_get_txpwr_lmt_abs(adapter, ent->regd_name, band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0);
3737
3738
for (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--)
3739
if (lmt[bw_pos] > lmt[bw_pos - 1])
3740
break;
3741
if (bw_pos == CHANNEL_WIDTH_20)
3742
continue;
3743
3744
RTW_PRINT_SEL(RTW_DBGDUMP, "[%s][%s][%s][%uT][%-4s] cch:"
3745
, band_str(band)
3746
, ch_width_str(bw)
3747
, txpwr_lmt_rs_str(tlrs)
3748
, ntx_idx + 1
3749
, ent->regd_name
3750
);
3751
for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
3752
_RTW_PRINT_SEL(RTW_DBGDUMP, "%03u ", cch_by_bw[bw_pos]);
3753
_RTW_PRINT_SEL(RTW_DBGDUMP, "limit:");
3754
for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) {
3755
if (lmt[bw_pos] == hal_spec->txgi_max)
3756
_RTW_PRINT_SEL(RTW_DBGDUMP, "N/A ");
3757
else if (lmt[bw_pos] > -hal_spec->txgi_pdbm && lmt[bw_pos] < 0) /* -1 < value < 0 */
3758
_RTW_PRINT_SEL(RTW_DBGDUMP, "-0.%d", (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
3759
else if (lmt[bw_pos] % hal_spec->txgi_pdbm)
3760
_RTW_PRINT_SEL(RTW_DBGDUMP, "%2d.%d ", lmt[bw_pos] / hal_spec->txgi_pdbm, (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
3761
else
3762
_RTW_PRINT_SEL(RTW_DBGDUMP, "%2d ", lmt[bw_pos] / hal_spec->txgi_pdbm);
3763
}
3764
_RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
3765
}
3766
for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
3767
lmt[bw_pos] = phy_get_txpwr_lmt_abs(adapter, regd_str(TXPWR_LMT_WW), band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0);
3768
3769
for (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--)
3770
if (lmt[bw_pos] > lmt[bw_pos - 1])
3771
break;
3772
if (bw_pos != CHANNEL_WIDTH_20) {
3773
RTW_PRINT_SEL(RTW_DBGDUMP, "[%s][%s][%s][%uT][%-4s] cch:"
3774
, band_str(band)
3775
, ch_width_str(bw)
3776
, txpwr_lmt_rs_str(tlrs)
3777
, ntx_idx + 1
3778
, regd_str(TXPWR_LMT_WW)
3779
);
3780
for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
3781
_RTW_PRINT_SEL(RTW_DBGDUMP, "%03u ", cch_by_bw[bw_pos]);
3782
_RTW_PRINT_SEL(RTW_DBGDUMP, "limit:");
3783
for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) {
3784
if (lmt[bw_pos] == hal_spec->txgi_max)
3785
_RTW_PRINT_SEL(RTW_DBGDUMP, "N/A ");
3786
else if (lmt[bw_pos] > -hal_spec->txgi_pdbm && lmt[bw_pos] < 0) /* -1 < value < 0 */
3787
_RTW_PRINT_SEL(RTW_DBGDUMP, "-0.%d", (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
3788
else if (lmt[bw_pos] % hal_spec->txgi_pdbm)
3789
_RTW_PRINT_SEL(RTW_DBGDUMP, "%2d.%d ", lmt[bw_pos] / hal_spec->txgi_pdbm, (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
3790
else
3791
_RTW_PRINT_SEL(RTW_DBGDUMP, "%2d ", lmt[bw_pos] / hal_spec->txgi_pdbm);
3792
}
3793
_RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
3794
}
3795
3796
offset_by_bw += 2;
3797
if (offset_by_bw & BIT(bw + 1))
3798
break;
3799
} while (1); /* loop for all ch combinations */
3800
} /* loop for center channels */
3801
} /* loop fo each ntx_idx */
3802
} /* loop for tlrs */
3803
} /* loop for bandwidth */
3804
} /* loop for band */
3805
}
3806
#endif /* DBG_TXPWR_LMT_BAND_CHK */
3807
3808
static void phy_txpwr_lmt_post_hdl(_adapter *adapter)
3809
{
3810
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
3811
_irqL irqL;
3812
3813
_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
3814
3815
#ifdef CONFIG_IEEE80211_BAND_5GHZ
3816
if (IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
3817
phy_txpwr_lmt_cross_ref_ht_vht(adapter);
3818
#endif
3819
phy_txpwr_lmt_cck_ofdm_mt_chk(adapter);
3820
3821
#if DBG_TXPWR_LMT_BAND_CHK
3822
phy_txpwr_limit_bandwidth_chk(adapter);
3823
#endif
3824
3825
_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
3826
}
3827
3828
BOOLEAN
3829
GetS1ByteIntegerFromStringInDecimal(
3830
char *str,
3831
s8 *val
3832
)
3833
{
3834
u8 negative = 0;
3835
u16 i = 0;
3836
3837
*val = 0;
3838
3839
while (str[i] != '\0') {
3840
if (i == 0 && (str[i] == '+' || str[i] == '-')) {
3841
if (str[i] == '-')
3842
negative = 1;
3843
} else if (str[i] >= '0' && str[i] <= '9') {
3844
*val *= 10;
3845
*val += (str[i] - '0');
3846
} else
3847
return _FALSE;
3848
++i;
3849
}
3850
3851
if (negative)
3852
*val = -*val;
3853
3854
return _TRUE;
3855
}
3856
#endif /* CONFIG_TXPWR_LIMIT */
3857
3858
/*
3859
* phy_set_tx_power_limit - Parsing TX power limit from phydm array, called by odm_ConfigBB_TXPWR_LMT_XXX in phydm
3860
*/
3861
void
3862
phy_set_tx_power_limit(
3863
struct dm_struct *pDM_Odm,
3864
u8 *Regulation,
3865
u8 *Band,
3866
u8 *Bandwidth,
3867
u8 *RateSection,
3868
u8 *ntx,
3869
u8 *Channel,
3870
u8 *PowerLimit
3871
)
3872
{
3873
#if CONFIG_TXPWR_LIMIT
3874
PADAPTER Adapter = pDM_Odm->adapter;
3875
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3876
struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
3877
u8 band = 0, bandwidth = 0, tlrs = 0, channel;
3878
u8 ntx_idx;
3879
s8 powerLimit = 0, prevPowerLimit, channelIndex;
3880
s8 ww_lmt_val = phy_txpwr_ww_lmt_value(Adapter);
3881
3882
if (0)
3883
RTW_INFO("Index of power limit table [regulation %s][band %s][bw %s][rate section %s][ntx %s][chnl %s][val %s]\n"
3884
, Regulation, Band, Bandwidth, RateSection, ntx, Channel, PowerLimit);
3885
3886
if (GetU1ByteIntegerFromStringInDecimal((char *)Channel, &channel) == _FALSE
3887
|| GetS1ByteIntegerFromStringInDecimal((char *)PowerLimit, &powerLimit) == _FALSE
3888
) {
3889
RTW_PRINT("Illegal index of power limit table [ch %s][val %s]\n", Channel, PowerLimit);
3890
return;
3891
}
3892
3893
if (powerLimit != ww_lmt_val) {
3894
if (powerLimit < -hal_spec->txgi_max || powerLimit > hal_spec->txgi_max)
3895
RTW_PRINT("Illegal power limit value [ch %s][val %s]\n", Channel, PowerLimit);
3896
3897
if (powerLimit > hal_spec->txgi_max)
3898
powerLimit = hal_spec->txgi_max;
3899
else if (powerLimit < -hal_spec->txgi_max)
3900
powerLimit = ww_lmt_val + 1;
3901
}
3902
3903
if (eqNByte(RateSection, (u8 *)("CCK"), 3))
3904
tlrs = TXPWR_LMT_RS_CCK;
3905
else if (eqNByte(RateSection, (u8 *)("OFDM"), 4))
3906
tlrs = TXPWR_LMT_RS_OFDM;
3907
else if (eqNByte(RateSection, (u8 *)("HT"), 2))
3908
tlrs = TXPWR_LMT_RS_HT;
3909
else if (eqNByte(RateSection, (u8 *)("VHT"), 3))
3910
tlrs = TXPWR_LMT_RS_VHT;
3911
else {
3912
RTW_PRINT("Wrong rate section:%s\n", RateSection);
3913
return;
3914
}
3915
3916
if (eqNByte(ntx, (u8 *)("1T"), 2))
3917
ntx_idx = RF_1TX;
3918
else if (eqNByte(ntx, (u8 *)("2T"), 2))
3919
ntx_idx = RF_2TX;
3920
else if (eqNByte(ntx, (u8 *)("3T"), 2))
3921
ntx_idx = RF_3TX;
3922
else if (eqNByte(ntx, (u8 *)("4T"), 2))
3923
ntx_idx = RF_4TX;
3924
else {
3925
RTW_PRINT("Wrong tx num:%s\n", ntx);
3926
return;
3927
}
3928
3929
if (eqNByte(Bandwidth, (u8 *)("20M"), 3))
3930
bandwidth = CHANNEL_WIDTH_20;
3931
else if (eqNByte(Bandwidth, (u8 *)("40M"), 3))
3932
bandwidth = CHANNEL_WIDTH_40;
3933
else if (eqNByte(Bandwidth, (u8 *)("80M"), 3))
3934
bandwidth = CHANNEL_WIDTH_80;
3935
else if (eqNByte(Bandwidth, (u8 *)("160M"), 4))
3936
bandwidth = CHANNEL_WIDTH_160;
3937
else {
3938
RTW_PRINT("unknown bandwidth: %s\n", Bandwidth);
3939
return;
3940
}
3941
3942
if (eqNByte(Band, (u8 *)("2.4G"), 4)) {
3943
band = BAND_ON_2_4G;
3944
channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, channel);
3945
3946
if (channelIndex == -1) {
3947
RTW_PRINT("unsupported channel: %d at 2.4G\n", channel);
3948
return;
3949
}
3950
3951
if (bandwidth >= MAX_2_4G_BANDWIDTH_NUM) {
3952
RTW_PRINT("unsupported bandwidth: %s at 2.4G\n", Bandwidth);
3953
return;
3954
}
3955
3956
rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);
3957
}
3958
#ifdef CONFIG_IEEE80211_BAND_5GHZ
3959
else if (eqNByte(Band, (u8 *)("5G"), 2)) {
3960
band = BAND_ON_5G;
3961
channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, channel);
3962
3963
if (channelIndex == -1) {
3964
RTW_PRINT("unsupported channel: %d at 5G\n", channel);
3965
return;
3966
}
3967
3968
rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);
3969
}
3970
#endif
3971
else {
3972
RTW_PRINT("unknown/unsupported band:%s\n", Band);
3973
return;
3974
}
3975
#endif
3976
}
3977
3978
u8
3979
phy_get_tx_power_index(
3980
PADAPTER pAdapter,
3981
enum rf_path RFPath,
3982
u8 Rate,
3983
enum channel_width BandWidth,
3984
u8 Channel
3985
)
3986
{
3987
return rtw_hal_get_tx_power_index(pAdapter, RFPath, Rate, BandWidth, Channel, NULL);
3988
}
3989
3990
void
3991
PHY_SetTxPowerIndex(
3992
PADAPTER pAdapter,
3993
u32 PowerIndex,
3994
enum rf_path RFPath,
3995
u8 Rate
3996
)
3997
{
3998
rtw_hal_set_tx_power_index(pAdapter, PowerIndex, RFPath, Rate);
3999
}
4000
4001
void dump_tx_power_idx_title(void *sel, _adapter *adapter)
4002
{
4003
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
4004
u8 bw = hal_data->current_channel_bw;
4005
4006
RTW_PRINT_SEL(sel, "%s", ch_width_str(bw));
4007
if (bw >= CHANNEL_WIDTH_80)
4008
_RTW_PRINT_SEL(sel, ", cch80:%u", hal_data->cch_80);
4009
if (bw >= CHANNEL_WIDTH_40)
4010
_RTW_PRINT_SEL(sel, ", cch40:%u", hal_data->cch_40);
4011
_RTW_PRINT_SEL(sel, ", cch20:%u\n", hal_data->cch_20);
4012
4013
RTW_PRINT_SEL(sel, "%-4s %-9s %2s %-3s%6s %-3s %-3s %-4s %-4s %-3s %-5s %-3s %-3s\n"
4014
, "path", "rate", "", "pwr", "", "pg", "", "(byr", "lmt)", "tpt", "ebias", "btc", "dpd");
4015
}
4016
4017
void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath, u8 rs)
4018
{
4019
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
4020
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
4021
u8 power_idx;
4022
struct txpwr_idx_comp tic;
4023
u8 tx_num, i;
4024
u8 band = hal_data->current_band_type;
4025
u8 cch = hal_data->current_channel;
4026
u8 bw = hal_data->current_channel_bw;
4027
4028
if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, rfpath))
4029
return;
4030
4031
if (rs >= RATE_SECTION_NUM)
4032
return;
4033
4034
tx_num = rate_section_to_tx_num(rs);
4035
if (tx_num + 1 > hal_data->tx_nss)
4036
return;
4037
4038
if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
4039
return;
4040
4041
if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
4042
return;
4043
4044
for (i = 0; i < rates_by_sections[rs].rate_num; i++) {
4045
power_idx = rtw_hal_get_tx_power_index(adapter, rfpath, rates_by_sections[rs].rates[i], bw, cch, &tic);
4046
4047
RTW_PRINT_SEL(sel, "%4c %9s %uT %3u(0x%02x) %3u %3d (%3d %3d) %3d %5d %3d %3d\n"
4048
, rf_path_char(rfpath), MGN_RATE_STR(rates_by_sections[rs].rates[i]), tic.ntx_idx + 1
4049
, power_idx, power_idx, tic.pg, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate)
4050
, tic.by_rate, tic.limit, tic.tpt, tic.ebias, tic.btc, tic.dpd);
4051
}
4052
}
4053
4054
void dump_tx_power_idx(void *sel, _adapter *adapter)
4055
{
4056
u8 rfpath, rs;
4057
4058
dump_tx_power_idx_title(sel, adapter);
4059
for (rfpath = RF_PATH_A; rfpath < RF_PATH_MAX; rfpath++)
4060
for (rs = CCK; rs < RATE_SECTION_NUM; rs++)
4061
dump_tx_power_idx_by_path_rs(sel, adapter, rfpath, rs);
4062
}
4063
4064
bool phy_is_tx_power_limit_needed(_adapter *adapter)
4065
{
4066
#if CONFIG_TXPWR_LIMIT
4067
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
4068
struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
4069
4070
if (regsty->RegEnableTxPowerLimit == 1
4071
|| (regsty->RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory == 1))
4072
return _TRUE;
4073
#endif
4074
4075
return _FALSE;
4076
}
4077
4078
bool phy_is_tx_power_by_rate_needed(_adapter *adapter)
4079
{
4080
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
4081
struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
4082
4083
if (regsty->RegEnableTxPowerByRate == 1
4084
|| (regsty->RegEnableTxPowerByRate == 2 && hal_data->EEPROMRegulatory != 2))
4085
return _TRUE;
4086
4087
#ifdef CONFIG_USE_TSSI
4088
RTW_WARN("%s: power by rate is always needed by TSSI\n", __func__);
4089
return _TRUE;
4090
#endif
4091
4092
return _FALSE;
4093
}
4094
4095
int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file)
4096
{
4097
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
4098
int ret = _FAIL;
4099
4100
hal_data->txpwr_by_rate_loaded = 0;
4101
PHY_InitTxPowerByRate(adapter);
4102
4103
/* tx power limit is based on tx power by rate */
4104
hal_data->txpwr_limit_loaded = 0;
4105
4106
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
4107
if (chk_file
4108
&& phy_ConfigBBWithPgParaFile(adapter, PHY_FILE_PHY_REG_PG) == _SUCCESS
4109
) {
4110
hal_data->txpwr_by_rate_from_file = 1;
4111
goto post_hdl;
4112
}
4113
#endif
4114
4115
#ifdef CONFIG_EMBEDDED_FWIMG
4116
if (HAL_STATUS_SUCCESS == odm_config_bb_with_header_file(&hal_data->odmpriv, CONFIG_BB_PHY_REG_PG)) {
4117
RTW_INFO("default power by rate loaded\n");
4118
hal_data->txpwr_by_rate_from_file = 0;
4119
goto post_hdl;
4120
}
4121
#endif
4122
4123
RTW_ERR("%s():Read Tx power by rate fail\n", __func__);
4124
goto exit;
4125
4126
post_hdl:
4127
if (hal_data->odmpriv.phy_reg_pg_value_type != PHY_REG_PG_EXACT_VALUE) {
4128
rtw_warn_on(1);
4129
goto exit;
4130
}
4131
4132
PHY_TxPowerByRateConfiguration(adapter);
4133
hal_data->txpwr_by_rate_loaded = 1;
4134
4135
ret = _SUCCESS;
4136
4137
exit:
4138
return ret;
4139
}
4140
4141
#if CONFIG_TXPWR_LIMIT
4142
int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file)
4143
{
4144
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
4145
struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
4146
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
4147
int ret = _FAIL;
4148
4149
hal_data->txpwr_limit_loaded = 0;
4150
rtw_regd_exc_list_free(rfctl);
4151
rtw_txpwr_lmt_list_free(rfctl);
4152
4153
if (!hal_data->txpwr_by_rate_loaded && regsty->target_tx_pwr_valid != _TRUE) {
4154
RTW_ERR("%s():Read Tx power limit before target tx power is specify\n", __func__);
4155
goto exit;
4156
}
4157
4158
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
4159
if (chk_file
4160
&& PHY_ConfigRFWithPowerLimitTableParaFile(adapter, PHY_FILE_TXPWR_LMT) == _SUCCESS
4161
) {
4162
hal_data->txpwr_limit_from_file = 1;
4163
goto post_hdl;
4164
}
4165
#endif
4166
4167
#ifdef CONFIG_EMBEDDED_FWIMG
4168
if (odm_config_rf_with_header_file(&hal_data->odmpriv, CONFIG_RF_TXPWR_LMT, RF_PATH_A) == HAL_STATUS_SUCCESS) {
4169
RTW_INFO("default power limit loaded\n");
4170
hal_data->txpwr_limit_from_file = 0;
4171
goto post_hdl;
4172
}
4173
#endif
4174
4175
RTW_ERR("%s():Read Tx power limit fail\n", __func__);
4176
goto exit;
4177
4178
post_hdl:
4179
phy_txpwr_lmt_post_hdl(adapter);
4180
rtw_txpwr_init_regd(rfctl);
4181
hal_data->txpwr_limit_loaded = 1;
4182
ret = _SUCCESS;
4183
4184
exit:
4185
return ret;
4186
}
4187
#endif /* CONFIG_TXPWR_LIMIT */
4188
4189
void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file)
4190
{
4191
struct registry_priv *regsty = adapter_to_regsty(adapter);
4192
4193
/* check registy target tx power */
4194
regsty->target_tx_pwr_valid = rtw_regsty_chk_target_tx_power_valid(adapter);
4195
4196
/* power by rate and limit */
4197
if (phy_is_tx_power_by_rate_needed(adapter)
4198
|| (phy_is_tx_power_limit_needed(adapter) && regsty->target_tx_pwr_valid != _TRUE)
4199
)
4200
phy_load_tx_power_by_rate(adapter, chk_file);
4201
4202
#if CONFIG_TXPWR_LIMIT
4203
if (phy_is_tx_power_limit_needed(adapter))
4204
phy_load_tx_power_limit(adapter, chk_file);
4205
#endif
4206
}
4207
4208
inline void phy_reload_tx_power_ext_info(_adapter *adapter)
4209
{
4210
phy_load_tx_power_ext_info(adapter, 1);
4211
}
4212
4213
inline void phy_reload_default_tx_power_ext_info(_adapter *adapter)
4214
{
4215
phy_load_tx_power_ext_info(adapter, 0);
4216
}
4217
4218
void dump_tx_power_ext_info(void *sel, _adapter *adapter)
4219
{
4220
struct registry_priv *regsty = adapter_to_regsty(adapter);
4221
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
4222
4223
if (regsty->target_tx_pwr_valid == _TRUE)
4224
RTW_PRINT_SEL(sel, "target_tx_power: from registry\n");
4225
else if (phy_is_tx_power_by_rate_needed(adapter))
4226
RTW_PRINT_SEL(sel, "target_tx_power: from power by rate\n");
4227
else
4228
RTW_PRINT_SEL(sel, "target_tx_power: unavailable\n");
4229
4230
RTW_PRINT_SEL(sel, "tx_power_by_rate: %s, %s, %s\n"
4231
, phy_is_tx_power_by_rate_needed(adapter) ? "enabled" : "disabled"
4232
, hal_data->txpwr_by_rate_loaded ? "loaded" : "unloaded"
4233
, hal_data->txpwr_by_rate_from_file ? "file" : "default"
4234
);
4235
4236
RTW_PRINT_SEL(sel, "tx_power_limit: %s, %s, %s\n"
4237
, phy_is_tx_power_limit_needed(adapter) ? "enabled" : "disabled"
4238
, hal_data->txpwr_limit_loaded ? "loaded" : "unloaded"
4239
, hal_data->txpwr_limit_from_file ? "file" : "default"
4240
);
4241
}
4242
4243
void dump_target_tx_power(void *sel, _adapter *adapter)
4244
{
4245
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
4246
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
4247
struct registry_priv *regsty = adapter_to_regsty(adapter);
4248
int path, tx_num, band, rs;
4249
u8 target;
4250
4251
for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
4252
if (!hal_is_band_support(adapter, band))
4253
continue;
4254
4255
for (path = 0; path < RF_PATH_MAX; path++) {
4256
if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
4257
break;
4258
4259
RTW_PRINT_SEL(sel, "[%s][%c]%s\n", band_str(band), rf_path_char(path)
4260
, (regsty->target_tx_pwr_valid == _FALSE && hal_data->txpwr_by_rate_undefined_band_path[band][path]) ? "(dup)" : "");
4261
4262
for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
4263
tx_num = rate_section_to_tx_num(rs);
4264
if (tx_num + 1 > hal_data->tx_nss)
4265
continue;
4266
4267
if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
4268
continue;
4269
4270
if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
4271
continue;
4272
4273
#ifdef CONFIG_USE_TSSI
4274
target = PHY_GetTxPowerByRateOriginal(adapter, band, path, MGN_MCS7);
4275
#else
4276
target = PHY_GetTxPowerByRateBase(adapter, band, path, rs);
4277
#endif
4278
4279
if (target % hal_spec->txgi_pdbm) {
4280
_RTW_PRINT_SEL(sel, "%7s: %2d.%d\n", rate_section_str(rs)
4281
, target / hal_spec->txgi_pdbm, (target % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
4282
} else {
4283
_RTW_PRINT_SEL(sel, "%7s: %5d\n", rate_section_str(rs)
4284
, target / hal_spec->txgi_pdbm);
4285
}
4286
}
4287
}
4288
}
4289
4290
return;
4291
}
4292
4293
void dump_tx_power_by_rate(void *sel, _adapter *adapter)
4294
{
4295
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
4296
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
4297
int path, tx_num, band, n, rs;
4298
u8 rate_num, max_rate_num, base;
4299
s8 by_rate_offset;
4300
4301
for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
4302
if (!hal_is_band_support(adapter, band))
4303
continue;
4304
4305
for (path = 0; path < RF_PATH_MAX; path++) {
4306
if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
4307
break;
4308
4309
RTW_PRINT_SEL(sel, "[%s][%c]%s\n", band_str(band), rf_path_char(path)
4310
, hal_data->txpwr_by_rate_undefined_band_path[band][path] ? "(dup)" : "");
4311
4312
for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
4313
tx_num = rate_section_to_tx_num(rs);
4314
if (tx_num + 1 > hal_data->tx_nss)
4315
continue;
4316
4317
if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
4318
continue;
4319
4320
if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
4321
continue;
4322
4323
if (IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
4324
max_rate_num = 10;
4325
else
4326
max_rate_num = 8;
4327
rate_num = rate_section_rate_num(rs);
4328
#ifdef CONFIG_USE_TSSI
4329
base = 0;
4330
#else
4331
base = PHY_GetTxPowerByRateBase(adapter, band, path, rs);
4332
#endif
4333
4334
RTW_PRINT_SEL(sel, "%7s: ", rate_section_str(rs));
4335
4336
/* dump power by rate in db */
4337
for (n = rate_num - 1; n >= 0; n--) {
4338
#ifdef CONFIG_USE_TSSI
4339
by_rate_offset = PHY_GetTxPowerByRateOriginal(adapter, band, path, rates_by_sections[rs].rates[n]);
4340
#else
4341
by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, rates_by_sections[rs].rates[n]);
4342
#endif
4343
4344
if ((base + by_rate_offset) % hal_spec->txgi_pdbm) {
4345
_RTW_PRINT_SEL(sel, "%2d.%d ", (base + by_rate_offset) / hal_spec->txgi_pdbm
4346
, ((base + by_rate_offset) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
4347
} else
4348
_RTW_PRINT_SEL(sel, "%5d ", (base + by_rate_offset) / hal_spec->txgi_pdbm);
4349
}
4350
for (n = 0; n < max_rate_num - rate_num; n++)
4351
_RTW_PRINT_SEL(sel, "%5s ", "");
4352
4353
_RTW_PRINT_SEL(sel, "|");
4354
4355
/* dump power by rate in offset */
4356
for (n = rate_num - 1; n >= 0; n--) {
4357
by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, rates_by_sections[rs].rates[n]);
4358
_RTW_PRINT_SEL(sel, "%3d ", by_rate_offset);
4359
}
4360
RTW_PRINT_SEL(sel, "\n");
4361
4362
}
4363
}
4364
}
4365
}
4366
4367
/*
4368
* phy file path is stored in global char array rtw_phy_para_file_path
4369
* need to care about racing
4370
*/
4371
int rtw_get_phy_file_path(_adapter *adapter, const char *file_name)
4372
{
4373
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
4374
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
4375
int len = 0;
4376
4377
if (file_name) {
4378
len += snprintf(rtw_phy_para_file_path, PATH_LENGTH_MAX, "%s", rtw_phy_file_path);
4379
#if defined(CONFIG_MULTIDRV) || defined(REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER)
4380
len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s/", hal_spec->ic_name);
4381
#endif
4382
len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s", file_name);
4383
4384
return _TRUE;
4385
}
4386
#endif
4387
return _FALSE;
4388
}
4389
4390
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
4391
int
4392
phy_ConfigMACWithParaFile(
4393
PADAPTER Adapter,
4394
char *pFileName
4395
)
4396
{
4397
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
4398
int rlen = 0, rtStatus = _FAIL;
4399
char *szLine, *ptmp;
4400
u32 u4bRegOffset, u4bRegValue, u4bMove;
4401
4402
if (!(Adapter->registrypriv.load_phy_file & LOAD_MAC_PARA_FILE))
4403
return rtStatus;
4404
4405
_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
4406
4407
if ((pHalData->mac_reg_len == 0) && (pHalData->mac_reg == NULL)) {
4408
rtw_get_phy_file_path(Adapter, pFileName);
4409
if (rtw_readable_file_sz_chk(rtw_phy_para_file_path,
4410
MAX_PARA_FILE_BUF_LEN) == _TRUE) {
4411
rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
4412
if (rlen > 0) {
4413
rtStatus = _SUCCESS;
4414
pHalData->mac_reg = rtw_zvmalloc(rlen);
4415
if (pHalData->mac_reg) {
4416
_rtw_memcpy(pHalData->mac_reg, pHalData->para_file_buf, rlen);
4417
pHalData->mac_reg_len = rlen;
4418
} else
4419
RTW_INFO("%s mac_reg alloc fail !\n", __FUNCTION__);
4420
}
4421
}
4422
} else {
4423
if ((pHalData->mac_reg_len != 0) && (pHalData->mac_reg != NULL)) {
4424
_rtw_memcpy(pHalData->para_file_buf, pHalData->mac_reg, pHalData->mac_reg_len);
4425
rtStatus = _SUCCESS;
4426
} else
4427
RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
4428
}
4429
4430
if (rtStatus == _SUCCESS) {
4431
ptmp = pHalData->para_file_buf;
4432
for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
4433
if (!IsCommentString(szLine)) {
4434
/* Get 1st hex value as register offset */
4435
if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
4436
if (u4bRegOffset == 0xffff) {
4437
/* Ending. */
4438
break;
4439
}
4440
4441
/* Get 2nd hex value as register value. */
4442
szLine += u4bMove;
4443
if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove))
4444
rtw_write8(Adapter, u4bRegOffset, (u8)u4bRegValue);
4445
}
4446
}
4447
}
4448
} else
4449
RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
4450
4451
return rtStatus;
4452
}
4453
4454
int
4455
phy_ConfigBBWithParaFile(
4456
PADAPTER Adapter,
4457
char *pFileName,
4458
u32 ConfigType
4459
)
4460
{
4461
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
4462
int rlen = 0, rtStatus = _FAIL;
4463
char *szLine, *ptmp;
4464
u32 u4bRegOffset, u4bRegValue, u4bMove;
4465
char *pBuf = NULL;
4466
u32 *pBufLen = NULL;
4467
4468
if (!(Adapter->registrypriv.load_phy_file & LOAD_BB_PARA_FILE))
4469
return rtStatus;
4470
4471
switch (ConfigType) {
4472
case CONFIG_BB_PHY_REG:
4473
pBuf = pHalData->bb_phy_reg;
4474
pBufLen = &pHalData->bb_phy_reg_len;
4475
break;
4476
case CONFIG_BB_AGC_TAB:
4477
pBuf = pHalData->bb_agc_tab;
4478
pBufLen = &pHalData->bb_agc_tab_len;
4479
break;
4480
default:
4481
RTW_INFO("Unknown ConfigType!! %d\r\n", ConfigType);
4482
break;
4483
}
4484
4485
_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
4486
4487
if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) {
4488
rtw_get_phy_file_path(Adapter, pFileName);
4489
if (rtw_readable_file_sz_chk(rtw_phy_para_file_path,
4490
MAX_PARA_FILE_BUF_LEN) == _TRUE) {
4491
rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
4492
if (rlen > 0) {
4493
rtStatus = _SUCCESS;
4494
pBuf = rtw_zvmalloc(rlen);
4495
if (pBuf) {
4496
_rtw_memcpy(pBuf, pHalData->para_file_buf, rlen);
4497
*pBufLen = rlen;
4498
4499
switch (ConfigType) {
4500
case CONFIG_BB_PHY_REG:
4501
pHalData->bb_phy_reg = pBuf;
4502
break;
4503
case CONFIG_BB_AGC_TAB:
4504
pHalData->bb_agc_tab = pBuf;
4505
break;
4506
}
4507
} else
4508
RTW_INFO("%s(): ConfigType %d alloc fail !\n", __FUNCTION__, ConfigType);
4509
}
4510
}
4511
} else {
4512
if ((pBufLen != NULL) && (*pBufLen != 0) && (pBuf != NULL)) {
4513
_rtw_memcpy(pHalData->para_file_buf, pBuf, *pBufLen);
4514
rtStatus = _SUCCESS;
4515
} else
4516
RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
4517
}
4518
4519
if (rtStatus == _SUCCESS) {
4520
ptmp = pHalData->para_file_buf;
4521
for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
4522
if (!IsCommentString(szLine)) {
4523
/* Get 1st hex value as register offset. */
4524
if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
4525
if (u4bRegOffset == 0xffff) {
4526
/* Ending. */
4527
break;
4528
} else if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {
4529
#ifdef CONFIG_LONG_DELAY_ISSUE
4530
rtw_msleep_os(50);
4531
#else
4532
rtw_mdelay_os(50);
4533
#endif
4534
} else if (u4bRegOffset == 0xfd)
4535
rtw_mdelay_os(5);
4536
else if (u4bRegOffset == 0xfc)
4537
rtw_mdelay_os(1);
4538
else if (u4bRegOffset == 0xfb)
4539
rtw_udelay_os(50);
4540
else if (u4bRegOffset == 0xfa)
4541
rtw_udelay_os(5);
4542
else if (u4bRegOffset == 0xf9)
4543
rtw_udelay_os(1);
4544
4545
/* Get 2nd hex value as register value. */
4546
szLine += u4bMove;
4547
if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
4548
/* RTW_INFO("[BB-ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue); */
4549
phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
4550
4551
if (u4bRegOffset == 0xa24)
4552
pHalData->odmpriv.rf_calibrate_info.rega24 = u4bRegValue;
4553
4554
/* Add 1us delay between BB/RF register setting. */
4555
rtw_udelay_os(1);
4556
}
4557
}
4558
}
4559
}
4560
} else
4561
RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
4562
4563
return rtStatus;
4564
}
4565
4566
void
4567
phy_DecryptBBPgParaFile(
4568
PADAPTER Adapter,
4569
char *buffer
4570
)
4571
{
4572
u32 i = 0, j = 0;
4573
u8 map[95] = {0};
4574
u8 currentChar;
4575
char *BufOfLines, *ptmp;
4576
4577
/* RTW_INFO("=====>phy_DecryptBBPgParaFile()\n"); */
4578
/* 32 the ascii code of the first visable char, 126 the last one */
4579
for (i = 0; i < 95; ++i)
4580
map[i] = (u8)(94 - i);
4581
4582
ptmp = buffer;
4583
i = 0;
4584
for (BufOfLines = GetLineFromBuffer(ptmp); BufOfLines != NULL; BufOfLines = GetLineFromBuffer(ptmp)) {
4585
/* RTW_INFO("Encrypted Line: %s\n", BufOfLines); */
4586
4587
for (j = 0; j < strlen(BufOfLines); ++j) {
4588
currentChar = BufOfLines[j];
4589
4590
if (currentChar == '\0')
4591
break;
4592
4593
currentChar -= (u8)((((i + j) * 3) % 128));
4594
4595
BufOfLines[j] = map[currentChar - 32] + 32;
4596
}
4597
/* RTW_INFO("Decrypted Line: %s\n", BufOfLines ); */
4598
if (strlen(BufOfLines) != 0)
4599
i++;
4600
BufOfLines[strlen(BufOfLines)] = '\n';
4601
}
4602
}
4603
4604
#ifndef DBG_TXPWR_BY_RATE_FILE_PARSE
4605
#define DBG_TXPWR_BY_RATE_FILE_PARSE 0
4606
#endif
4607
4608
int
4609
phy_ParseBBPgParaFile(
4610
PADAPTER Adapter,
4611
char *buffer
4612
)
4613
{
4614
int rtStatus = _FAIL;
4615
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
4616
struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
4617
char *szLine, *ptmp;
4618
u32 u4bRegOffset, u4bRegMask;
4619
u32 u4bMove;
4620
BOOLEAN firstLine = _TRUE;
4621
u8 tx_num = 0;
4622
u8 band = 0, rf_path = 0;
4623
4624
if (Adapter->registrypriv.RegDecryptCustomFile == 1)
4625
phy_DecryptBBPgParaFile(Adapter, buffer);
4626
4627
ptmp = buffer;
4628
for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
4629
if (isAllSpaceOrTab(szLine, sizeof(*szLine)))
4630
continue;
4631
4632
if (!IsCommentString(szLine)) {
4633
/* Get header info (relative value or exact value) */
4634
if (firstLine) {
4635
if (eqNByte(szLine, (u8 *)("#[v1]"), 5)
4636
|| eqNByte(szLine, (u8 *)("#[v2]"), 5))
4637
pHalData->odmpriv.phy_reg_pg_version = szLine[3] - '0';
4638
else {
4639
RTW_ERR("The format in PHY_REG_PG are invalid %s\n", szLine);
4640
goto exit;
4641
}
4642
4643
if (eqNByte(szLine + 5, (u8 *)("[Exact]#"), 8)) {
4644
pHalData->odmpriv.phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
4645
firstLine = _FALSE;
4646
continue;
4647
} else {
4648
RTW_ERR("The values in PHY_REG_PG are invalid %s\n", szLine);
4649
goto exit;
4650
}
4651
}
4652
4653
if (pHalData->odmpriv.phy_reg_pg_version > 0) {
4654
u32 index = 0;
4655
4656
if (eqNByte(szLine, "0xffff", 6))
4657
break;
4658
4659
if (!eqNByte("#[END]#", szLine, 7)) {
4660
/* load the table label info */
4661
if (szLine[0] == '#') {
4662
index = 0;
4663
if (eqNByte(szLine, "#[2.4G]" , 7)) {
4664
band = BAND_ON_2_4G;
4665
index += 8;
4666
} else if (eqNByte(szLine, "#[5G]", 5)) {
4667
band = BAND_ON_5G;
4668
index += 6;
4669
} else {
4670
RTW_ERR("Invalid band %s in PHY_REG_PG.txt\n", szLine);
4671
goto exit;
4672
}
4673
4674
rf_path = szLine[index] - 'A';
4675
if (DBG_TXPWR_BY_RATE_FILE_PARSE)
4676
RTW_INFO(" Table label Band %d, RfPath %d\n", band, rf_path );
4677
} else { /* load rows of tables */
4678
if (szLine[1] == '1')
4679
tx_num = RF_1TX;
4680
else if (szLine[1] == '2')
4681
tx_num = RF_2TX;
4682
else if (szLine[1] == '3')
4683
tx_num = RF_3TX;
4684
else if (szLine[1] == '4')
4685
tx_num = RF_4TX;
4686
else {
4687
RTW_ERR("Invalid row in PHY_REG_PG.txt '%c'(%d)\n", szLine[1], szLine[1]);
4688
goto exit;
4689
}
4690
4691
while (szLine[index] != ']')
4692
++index;
4693
++index;/* skip ] */
4694
4695
/* Get 2nd hex value as register offset. */
4696
szLine += index;
4697
if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove))
4698
szLine += u4bMove;
4699
else
4700
goto exit;
4701
4702
/* Get 2nd hex value as register mask. */
4703
if (GetHexValueFromString(szLine, &u4bRegMask, &u4bMove))
4704
szLine += u4bMove;
4705
else
4706
goto exit;
4707
4708
if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_EXACT_VALUE) {
4709
u32 combineValue = 0;
4710
u8 integer = 0, fraction = 0;
4711
4712
if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
4713
szLine += u4bMove;
4714
else
4715
goto exit;
4716
4717
integer *= hal_spec->txgi_pdbm;
4718
integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
4719
if (pHalData->odmpriv.phy_reg_pg_version == 1)
4720
combineValue |= (((integer / 10) << 4) + (integer % 10));
4721
else
4722
combineValue |= integer;
4723
4724
if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
4725
szLine += u4bMove;
4726
else
4727
goto exit;
4728
4729
integer *= hal_spec->txgi_pdbm;
4730
integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
4731
combineValue <<= 8;
4732
if (pHalData->odmpriv.phy_reg_pg_version == 1)
4733
combineValue |= (((integer / 10) << 4) + (integer % 10));
4734
else
4735
combineValue |= integer;
4736
4737
if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
4738
szLine += u4bMove;
4739
else
4740
goto exit;
4741
4742
integer *= hal_spec->txgi_pdbm;
4743
integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
4744
combineValue <<= 8;
4745
if (pHalData->odmpriv.phy_reg_pg_version == 1)
4746
combineValue |= (((integer / 10) << 4) + (integer % 10));
4747
else
4748
combineValue |= integer;
4749
4750
if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
4751
szLine += u4bMove;
4752
else
4753
goto exit;
4754
4755
integer *= hal_spec->txgi_pdbm;
4756
integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
4757
combineValue <<= 8;
4758
if (pHalData->odmpriv.phy_reg_pg_version == 1)
4759
combineValue |= (((integer / 10) << 4) + (integer % 10));
4760
else
4761
combineValue |= integer;
4762
4763
phy_store_tx_power_by_rate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, combineValue);
4764
4765
if (DBG_TXPWR_BY_RATE_FILE_PARSE)
4766
RTW_INFO("addr:0x%3x mask:0x%08x %dTx = 0x%08x\n", u4bRegOffset, u4bRegMask, tx_num + 1, combineValue);
4767
}
4768
}
4769
}
4770
}
4771
}
4772
}
4773
4774
rtStatus = _SUCCESS;
4775
4776
exit:
4777
RTW_INFO("%s return %d\n", __func__, rtStatus);
4778
return rtStatus;
4779
}
4780
4781
int
4782
phy_ConfigBBWithPgParaFile(
4783
PADAPTER Adapter,
4784
const char *pFileName)
4785
{
4786
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
4787
int rlen = 0, rtStatus = _FAIL;
4788
4789
if (!(Adapter->registrypriv.load_phy_file & LOAD_BB_PG_PARA_FILE))
4790
return rtStatus;
4791
4792
_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
4793
4794
if (pHalData->bb_phy_reg_pg == NULL) {
4795
rtw_get_phy_file_path(Adapter, pFileName);
4796
if (rtw_readable_file_sz_chk(rtw_phy_para_file_path,
4797
MAX_PARA_FILE_BUF_LEN) == _TRUE) {
4798
rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
4799
if (rlen > 0) {
4800
rtStatus = _SUCCESS;
4801
pHalData->bb_phy_reg_pg = rtw_zvmalloc(rlen);
4802
if (pHalData->bb_phy_reg_pg) {
4803
_rtw_memcpy(pHalData->bb_phy_reg_pg, pHalData->para_file_buf, rlen);
4804
pHalData->bb_phy_reg_pg_len = rlen;
4805
} else
4806
RTW_INFO("%s bb_phy_reg_pg alloc fail !\n", __FUNCTION__);
4807
}
4808
}
4809
} else {
4810
if ((pHalData->bb_phy_reg_pg_len != 0) && (pHalData->bb_phy_reg_pg != NULL)) {
4811
_rtw_memcpy(pHalData->para_file_buf, pHalData->bb_phy_reg_pg, pHalData->bb_phy_reg_pg_len);
4812
rtStatus = _SUCCESS;
4813
} else
4814
RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
4815
}
4816
4817
if (rtStatus == _SUCCESS) {
4818
/* RTW_INFO("phy_ConfigBBWithPgParaFile(): read %s ok\n", pFileName); */
4819
rtStatus = phy_ParseBBPgParaFile(Adapter, pHalData->para_file_buf);
4820
} else
4821
RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
4822
4823
return rtStatus;
4824
}
4825
4826
#if (MP_DRIVER == 1)
4827
4828
int
4829
phy_ConfigBBWithMpParaFile(
4830
PADAPTER Adapter,
4831
char *pFileName
4832
)
4833
{
4834
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
4835
int rlen = 0, rtStatus = _FAIL;
4836
char *szLine, *ptmp;
4837
u32 u4bRegOffset, u4bRegValue, u4bMove;
4838
4839
if (!(Adapter->registrypriv.load_phy_file & LOAD_BB_MP_PARA_FILE))
4840
return rtStatus;
4841
4842
_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
4843
4844
if ((pHalData->bb_phy_reg_mp_len == 0) && (pHalData->bb_phy_reg_mp == NULL)) {
4845
rtw_get_phy_file_path(Adapter, pFileName);
4846
if (rtw_readable_file_sz_chk(rtw_phy_para_file_path,
4847
MAX_PARA_FILE_BUF_LEN) == _TRUE) {
4848
rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
4849
if (rlen > 0) {
4850
rtStatus = _SUCCESS;
4851
pHalData->bb_phy_reg_mp = rtw_zvmalloc(rlen);
4852
if (pHalData->bb_phy_reg_mp) {
4853
_rtw_memcpy(pHalData->bb_phy_reg_mp, pHalData->para_file_buf, rlen);
4854
pHalData->bb_phy_reg_mp_len = rlen;
4855
} else
4856
RTW_INFO("%s bb_phy_reg_mp alloc fail !\n", __FUNCTION__);
4857
}
4858
}
4859
} else {
4860
if ((pHalData->bb_phy_reg_mp_len != 0) && (pHalData->bb_phy_reg_mp != NULL)) {
4861
_rtw_memcpy(pHalData->para_file_buf, pHalData->bb_phy_reg_mp, pHalData->bb_phy_reg_mp_len);
4862
rtStatus = _SUCCESS;
4863
} else
4864
RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
4865
}
4866
4867
if (rtStatus == _SUCCESS) {
4868
/* RTW_INFO("phy_ConfigBBWithMpParaFile(): read %s ok\n", pFileName); */
4869
4870
ptmp = pHalData->para_file_buf;
4871
for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
4872
if (!IsCommentString(szLine)) {
4873
/* Get 1st hex value as register offset. */
4874
if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
4875
if (u4bRegOffset == 0xffff) {
4876
/* Ending. */
4877
break;
4878
} else if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {
4879
#ifdef CONFIG_LONG_DELAY_ISSUE
4880
rtw_msleep_os(50);
4881
#else
4882
rtw_mdelay_os(50);
4883
#endif
4884
} else if (u4bRegOffset == 0xfd)
4885
rtw_mdelay_os(5);
4886
else if (u4bRegOffset == 0xfc)
4887
rtw_mdelay_os(1);
4888
else if (u4bRegOffset == 0xfb)
4889
rtw_udelay_os(50);
4890
else if (u4bRegOffset == 0xfa)
4891
rtw_udelay_os(5);
4892
else if (u4bRegOffset == 0xf9)
4893
rtw_udelay_os(1);
4894
4895
/* Get 2nd hex value as register value. */
4896
szLine += u4bMove;
4897
if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
4898
/* RTW_INFO("[ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue); */
4899
phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
4900
4901
/* Add 1us delay between BB/RF register setting. */
4902
rtw_udelay_os(1);
4903
}
4904
}
4905
}
4906
}
4907
} else
4908
RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
4909
4910
return rtStatus;
4911
}
4912
4913
#endif
4914
4915
int
4916
PHY_ConfigRFWithParaFile(
4917
PADAPTER Adapter,
4918
char *pFileName,
4919
enum rf_path eRFPath
4920
)
4921
{
4922
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
4923
int rlen = 0, rtStatus = _FAIL;
4924
char *szLine, *ptmp;
4925
u32 u4bRegOffset, u4bRegValue, u4bMove;
4926
u16 i;
4927
char *pBuf = NULL;
4928
u32 *pBufLen = NULL;
4929
4930
if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_PARA_FILE))
4931
return rtStatus;
4932
4933
switch (eRFPath) {
4934
case RF_PATH_A:
4935
pBuf = pHalData->rf_radio_a;
4936
pBufLen = &pHalData->rf_radio_a_len;
4937
break;
4938
case RF_PATH_B:
4939
pBuf = pHalData->rf_radio_b;
4940
pBufLen = &pHalData->rf_radio_b_len;
4941
break;
4942
default:
4943
RTW_INFO("Unknown RF path!! %d\r\n", eRFPath);
4944
break;
4945
}
4946
4947
_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
4948
4949
if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) {
4950
rtw_get_phy_file_path(Adapter, pFileName);
4951
if (rtw_readable_file_sz_chk(rtw_phy_para_file_path,
4952
MAX_PARA_FILE_BUF_LEN) == _TRUE) {
4953
rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
4954
if (rlen > 0) {
4955
rtStatus = _SUCCESS;
4956
pBuf = rtw_zvmalloc(rlen);
4957
if (pBuf) {
4958
_rtw_memcpy(pBuf, pHalData->para_file_buf, rlen);
4959
*pBufLen = rlen;
4960
4961
switch (eRFPath) {
4962
case RF_PATH_A:
4963
pHalData->rf_radio_a = pBuf;
4964
break;
4965
case RF_PATH_B:
4966
pHalData->rf_radio_b = pBuf;
4967
break;
4968
default:
4969
RTW_INFO("Unknown RF path!! %d\r\n", eRFPath);
4970
break;
4971
}
4972
} else
4973
RTW_INFO("%s(): eRFPath=%d alloc fail !\n", __FUNCTION__, eRFPath);
4974
}
4975
}
4976
} else {
4977
if ((pBufLen != NULL) && (*pBufLen != 0) && (pBuf != NULL)) {
4978
_rtw_memcpy(pHalData->para_file_buf, pBuf, *pBufLen);
4979
rtStatus = _SUCCESS;
4980
} else
4981
RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
4982
}
4983
4984
if (rtStatus == _SUCCESS) {
4985
/* RTW_INFO("%s(): read %s successfully\n", __FUNCTION__, pFileName); */
4986
4987
ptmp = pHalData->para_file_buf;
4988
for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
4989
if (!IsCommentString(szLine)) {
4990
/* Get 1st hex value as register offset. */
4991
if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
4992
if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {
4993
/* Deay specific ms. Only RF configuration require delay. */
4994
#ifdef CONFIG_LONG_DELAY_ISSUE
4995
rtw_msleep_os(50);
4996
#else
4997
rtw_mdelay_os(50);
4998
#endif
4999
} else if (u4bRegOffset == 0xfd) {
5000
/* delay_ms(5); */
5001
for (i = 0; i < 100; i++)
5002
rtw_udelay_os(MAX_STALL_TIME);
5003
} else if (u4bRegOffset == 0xfc) {
5004
/* delay_ms(1); */
5005
for (i = 0; i < 20; i++)
5006
rtw_udelay_os(MAX_STALL_TIME);
5007
} else if (u4bRegOffset == 0xfb)
5008
rtw_udelay_os(50);
5009
else if (u4bRegOffset == 0xfa)
5010
rtw_udelay_os(5);
5011
else if (u4bRegOffset == 0xf9)
5012
rtw_udelay_os(1);
5013
else if (u4bRegOffset == 0xffff)
5014
break;
5015
5016
/* Get 2nd hex value as register value. */
5017
szLine += u4bMove;
5018
if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
5019
phy_set_rf_reg(Adapter, eRFPath, u4bRegOffset, bRFRegOffsetMask, u4bRegValue);
5020
5021
/* Temp add, for frequency lock, if no delay, that may cause */
5022
/* frequency shift, ex: 2412MHz => 2417MHz */
5023
/* If frequency shift, the following action may works. */
5024
/* Fractional-N table in radio_a.txt */
5025
/* 0x2a 0x00001 */ /* channel 1 */
5026
/* 0x2b 0x00808 frequency divider. */
5027
/* 0x2b 0x53333 */
5028
/* 0x2c 0x0000c */
5029
rtw_udelay_os(1);
5030
}
5031
}
5032
}
5033
}
5034
} else
5035
RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
5036
5037
return rtStatus;
5038
}
5039
5040
void
5041
initDeltaSwingIndexTables(
5042
PADAPTER Adapter,
5043
char *Band,
5044
char *Path,
5045
char *Sign,
5046
char *Channel,
5047
char *Rate,
5048
char *Data
5049
)
5050
{
5051
#define STR_EQUAL_5G(_band, _path, _sign, _rate, _chnl) \
5052
((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\
5053
(strcmp(Rate, _rate) == 0) && (strcmp(Channel, _chnl) == 0)\
5054
)
5055
#define STR_EQUAL_2G(_band, _path, _sign, _rate) \
5056
((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\
5057
(strcmp(Rate, _rate) == 0)\
5058
)
5059
5060
#define STORE_SWING_TABLE(_array, _iteratedIdx) \
5061
do { \
5062
for (token = strsep(&Data, delim); token != NULL; token = strsep(&Data, delim)) {\
5063
sscanf(token, "%d", &idx);\
5064
_array[_iteratedIdx++] = (u8)idx;\
5065
} } while (0)\
5066
5067
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
5068
struct dm_struct *pDM_Odm = &pHalData->odmpriv;
5069
struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
5070
u32 j = 0;
5071
char *token;
5072
char delim[] = ",";
5073
u32 idx = 0;
5074
5075
/* RTW_INFO("===>initDeltaSwingIndexTables(): Band: %s;\nPath: %s;\nSign: %s;\nChannel: %s;\nRate: %s;\n, Data: %s;\n", */
5076
/* Band, Path, Sign, Channel, Rate, Data); */
5077
5078
if (STR_EQUAL_2G("2G", "A", "+", "CCK"))
5079
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p, j);
5080
else if (STR_EQUAL_2G("2G", "A", "-", "CCK"))
5081
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n, j);
5082
else if (STR_EQUAL_2G("2G", "B", "+", "CCK"))
5083
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p, j);
5084
else if (STR_EQUAL_2G("2G", "B", "-", "CCK"))
5085
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n, j);
5086
else if (STR_EQUAL_2G("2G", "A", "+", "ALL"))
5087
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_p, j);
5088
else if (STR_EQUAL_2G("2G", "A", "-", "ALL"))
5089
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_n, j);
5090
else if (STR_EQUAL_2G("2G", "B", "+", "ALL"))
5091
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_p, j);
5092
else if (STR_EQUAL_2G("2G", "B", "-", "ALL"))
5093
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_n, j);
5094
else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "0"))
5095
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[0], j);
5096
else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "0"))
5097
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[0], j);
5098
else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "0"))
5099
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[0], j);
5100
else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "0"))
5101
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[0], j);
5102
else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "1"))
5103
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[1], j);
5104
else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "1"))
5105
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[1], j);
5106
else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "1"))
5107
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[1], j);
5108
else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "1"))
5109
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[1], j);
5110
else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "2"))
5111
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[2], j);
5112
else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "2"))
5113
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[2], j);
5114
else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "2"))
5115
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[2], j);
5116
else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "2"))
5117
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[2], j);
5118
else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "3"))
5119
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[3], j);
5120
else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "3"))
5121
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[3], j);
5122
else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "3"))
5123
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[3], j);
5124
else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "3"))
5125
STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[3], j);
5126
else
5127
RTW_INFO("===>initDeltaSwingIndexTables(): The input is invalid!!\n");
5128
}
5129
5130
int
5131
PHY_ConfigRFWithTxPwrTrackParaFile(
5132
PADAPTER Adapter,
5133
char *pFileName
5134
)
5135
{
5136
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
5137
struct dm_struct *pDM_Odm = &pHalData->odmpriv;
5138
int rlen = 0, rtStatus = _FAIL;
5139
char *szLine, *ptmp;
5140
u32 i = 0;
5141
5142
if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_TXPWR_TRACK_PARA_FILE))
5143
return rtStatus;
5144
5145
_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
5146
5147
if ((pHalData->rf_tx_pwr_track_len == 0) && (pHalData->rf_tx_pwr_track == NULL)) {
5148
rtw_get_phy_file_path(Adapter, pFileName);
5149
if (rtw_readable_file_sz_chk(rtw_phy_para_file_path,
5150
MAX_PARA_FILE_BUF_LEN) == _TRUE) {
5151
rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
5152
if (rlen > 0) {
5153
rtStatus = _SUCCESS;
5154
pHalData->rf_tx_pwr_track = rtw_zvmalloc(rlen);
5155
if (pHalData->rf_tx_pwr_track) {
5156
_rtw_memcpy(pHalData->rf_tx_pwr_track, pHalData->para_file_buf, rlen);
5157
pHalData->rf_tx_pwr_track_len = rlen;
5158
} else
5159
RTW_INFO("%s rf_tx_pwr_track alloc fail !\n", __FUNCTION__);
5160
}
5161
}
5162
} else {
5163
if ((pHalData->rf_tx_pwr_track_len != 0) && (pHalData->rf_tx_pwr_track != NULL)) {
5164
_rtw_memcpy(pHalData->para_file_buf, pHalData->rf_tx_pwr_track, pHalData->rf_tx_pwr_track_len);
5165
rtStatus = _SUCCESS;
5166
} else
5167
RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
5168
}
5169
5170
if (rtStatus == _SUCCESS) {
5171
/* RTW_INFO("%s(): read %s successfully\n", __FUNCTION__, pFileName); */
5172
5173
ptmp = pHalData->para_file_buf;
5174
for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
5175
if (!IsCommentString(szLine)) {
5176
char band[5] = "", path[5] = "", sign[5] = "";
5177
char chnl[5] = "", rate[10] = "";
5178
char data[300] = ""; /* 100 is too small */
5179
5180
if (strlen(szLine) < 10 || szLine[0] != '[')
5181
continue;
5182
5183
strncpy(band, szLine + 1, 2);
5184
strncpy(path, szLine + 5, 1);
5185
strncpy(sign, szLine + 8, 1);
5186
5187
i = 10; /* szLine+10 */
5188
if (!ParseQualifiedString(szLine, &i, rate, '[', ']')) {
5189
/* RTW_INFO("Fail to parse rate!\n"); */
5190
}
5191
if (!ParseQualifiedString(szLine, &i, chnl, '[', ']')) {
5192
/* RTW_INFO("Fail to parse channel group!\n"); */
5193
}
5194
while (szLine[i] != '{' && i < strlen(szLine))
5195
i++;
5196
if (!ParseQualifiedString(szLine, &i, data, '{', '}')) {
5197
/* RTW_INFO("Fail to parse data!\n"); */
5198
}
5199
5200
initDeltaSwingIndexTables(Adapter, band, path, sign, chnl, rate, data);
5201
}
5202
}
5203
} else
5204
RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
5205
#if 0
5206
for (i = 0; i < DELTA_SWINGIDX_SIZE; ++i) {
5207
RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2ga_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2ga_p[i]);
5208
RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2ga_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2ga_n[i]);
5209
RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2gb_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2gb_p[i]);
5210
RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2gb_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2gb_n[i]);
5211
RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p[i]);
5212
RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n[i]);
5213
RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p[i]);
5214
RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n[i]);
5215
5216
for (j = 0; j < 3; ++j) {
5217
RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5ga_p[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5ga_p[j][i]);
5218
RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5ga_n[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5ga_n[j][i]);
5219
RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5gb_p[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5gb_p[j][i]);
5220
RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5gb_n[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5gb_n[j][i]);
5221
}
5222
}
5223
#endif
5224
return rtStatus;
5225
}
5226
5227
#if CONFIG_TXPWR_LIMIT
5228
5229
#ifndef DBG_TXPWR_LMT_FILE_PARSE
5230
#define DBG_TXPWR_LMT_FILE_PARSE 0
5231
#endif
5232
5233
#define PARSE_RET_NO_HDL 0
5234
#define PARSE_RET_SUCCESS 1
5235
#define PARSE_RET_FAIL 2
5236
5237
/*
5238
* @@Ver=2.0
5239
* or
5240
* @@DomainCode=0x28, Regulation=C6
5241
* or
5242
* @@CountryCode=GB, Regulation=C7
5243
*/
5244
static u8 parse_reg_exc_config(_adapter *adapter, char *szLine)
5245
{
5246
#define VER_PREFIX "Ver="
5247
#define DOMAIN_PREFIX "DomainCode=0x"
5248
#define COUNTRY_PREFIX "CountryCode="
5249
#define REG_PREFIX "Regulation="
5250
5251
const u8 ver_prefix_len = strlen(VER_PREFIX);
5252
const u8 domain_prefix_len = strlen(DOMAIN_PREFIX);
5253
const u8 country_prefix_len = strlen(COUNTRY_PREFIX);
5254
const u8 reg_prefix_len = strlen(REG_PREFIX);
5255
u32 i, i_val_s, i_val_e;
5256
u32 j;
5257
u8 domain = 0xFF;
5258
char *country = NULL;
5259
u8 parse_reg = 0;
5260
5261
if (szLine[0] != '@' || szLine[1] != '@')
5262
return PARSE_RET_NO_HDL;
5263
5264
i = 2;
5265
if (strncmp(szLine + i, VER_PREFIX, ver_prefix_len) == 0)
5266
; /* nothing to do */
5267
else if (strncmp(szLine + i, DOMAIN_PREFIX, domain_prefix_len) == 0) {
5268
/* get string after domain prefix to ',' */
5269
i += domain_prefix_len;
5270
i_val_s = i;
5271
while (szLine[i] != ',') {
5272
if (szLine[i] == '\0')
5273
return PARSE_RET_FAIL;
5274
i++;
5275
}
5276
i_val_e = i;
5277
5278
/* check if all hex */
5279
for (j = i_val_s; j < i_val_e; j++)
5280
if (IsHexDigit(szLine[j]) == _FALSE)
5281
return PARSE_RET_FAIL;
5282
5283
/* get value from hex string */
5284
if (sscanf(szLine + i_val_s, "%hhx", &domain) != 1)
5285
return PARSE_RET_FAIL;
5286
5287
parse_reg = 1;
5288
} else if (strncmp(szLine + i, COUNTRY_PREFIX, country_prefix_len) == 0) {
5289
/* get string after country prefix to ',' */
5290
i += country_prefix_len;
5291
i_val_s = i;
5292
while (szLine[i] != ',') {
5293
if (szLine[i] == '\0')
5294
return PARSE_RET_FAIL;
5295
i++;
5296
}
5297
i_val_e = i;
5298
5299
if (i_val_e - i_val_s != 2)
5300
return PARSE_RET_FAIL;
5301
5302
/* check if all alpha */
5303
for (j = i_val_s; j < i_val_e; j++)
5304
if (is_alpha(szLine[j]) == _FALSE)
5305
return PARSE_RET_FAIL;
5306
5307
country = szLine + i_val_s;
5308
5309
parse_reg = 1;
5310
5311
} else
5312
return PARSE_RET_FAIL;
5313
5314
if (parse_reg) {
5315
/* move to 'R' */
5316
while (szLine[i] != 'R') {
5317
if (szLine[i] == '\0')
5318
return PARSE_RET_FAIL;
5319
i++;
5320
}
5321
5322
/* check if matching regulation prefix */
5323
if (strncmp(szLine + i, REG_PREFIX, reg_prefix_len) != 0)
5324
return PARSE_RET_FAIL;
5325
5326
/* get string after regulation prefix ending with space */
5327
i += reg_prefix_len;
5328
i_val_s = i;
5329
while (szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0')
5330
i++;
5331
5332
if (i == i_val_s)
5333
return PARSE_RET_FAIL;
5334
5335
rtw_regd_exc_add_with_nlen(adapter_to_rfctl(adapter), country, domain, szLine + i_val_s, i - i_val_s);
5336
}
5337
5338
return PARSE_RET_SUCCESS;
5339
}
5340
5341
static int
5342
phy_ParsePowerLimitTableFile(
5343
PADAPTER Adapter,
5344
char *buffer
5345
)
5346
{
5347
#define LD_STAGE_EXC_MAPPING 0
5348
#define LD_STAGE_TAB_DEFINE 1
5349
#define LD_STAGE_TAB_START 2
5350
#define LD_STAGE_COLUMN_DEFINE 3
5351
#define LD_STAGE_CH_ROW 4
5352
5353
int rtStatus = _FAIL;
5354
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
5355
struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
5356
struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
5357
u8 loadingStage = LD_STAGE_EXC_MAPPING;
5358
u32 i = 0, forCnt = 0;
5359
char *szLine, *ptmp;
5360
char band[10], bandwidth[10], rateSection[10], ntx[10], colNumBuf[10];
5361
char **regulation = NULL;
5362
u8 colNum = 0;
5363
5364
if (Adapter->registrypriv.RegDecryptCustomFile == 1)
5365
phy_DecryptBBPgParaFile(Adapter, buffer);
5366
5367
ptmp = buffer;
5368
for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
5369
if (isAllSpaceOrTab(szLine, sizeof(*szLine)))
5370
continue;
5371
if (IsCommentString(szLine))
5372
continue;
5373
5374
if (loadingStage == LD_STAGE_EXC_MAPPING) {
5375
if (szLine[0] == '#' || szLine[1] == '#') {
5376
loadingStage = LD_STAGE_TAB_DEFINE;
5377
if (DBG_TXPWR_LMT_FILE_PARSE)
5378
dump_regd_exc_list(RTW_DBGDUMP, adapter_to_rfctl(Adapter));
5379
} else {
5380
if (parse_reg_exc_config(Adapter, szLine) == PARSE_RET_FAIL) {
5381
RTW_ERR("Fail to parse regulation exception ruls!\n");
5382
goto exit;
5383
}
5384
continue;
5385
}
5386
}
5387
5388
if (loadingStage == LD_STAGE_TAB_DEFINE) {
5389
/* read "## 2.4G, 20M, 1T, CCK" */
5390
if (szLine[0] != '#' || szLine[1] != '#')
5391
continue;
5392
5393
/* skip the space */
5394
i = 2;
5395
while (szLine[i] == ' ' || szLine[i] == '\t')
5396
++i;
5397
5398
szLine[--i] = ' '; /* return the space in front of the regulation info */
5399
5400
/* Parse the label of the table */
5401
_rtw_memset((void *) band, 0, 10);
5402
_rtw_memset((void *) bandwidth, 0, 10);
5403
_rtw_memset((void *) ntx, 0, 10);
5404
_rtw_memset((void *) rateSection, 0, 10);
5405
if (!ParseQualifiedString(szLine, &i, band, ' ', ',')) {
5406
RTW_ERR("Fail to parse band!\n");
5407
goto exit;
5408
}
5409
if (!ParseQualifiedString(szLine, &i, bandwidth, ' ', ',')) {
5410
RTW_ERR("Fail to parse bandwidth!\n");
5411
goto exit;
5412
}
5413
if (!ParseQualifiedString(szLine, &i, ntx, ' ', ',')) {
5414
RTW_ERR("Fail to parse ntx!\n");
5415
goto exit;
5416
}
5417
if (!ParseQualifiedString(szLine, &i, rateSection, ' ', ',')) {
5418
RTW_ERR("Fail to parse rate!\n");
5419
goto exit;
5420
}
5421
5422
loadingStage = LD_STAGE_TAB_START;
5423
} else if (loadingStage == LD_STAGE_TAB_START) {
5424
/* read "## START" */
5425
if (szLine[0] != '#' || szLine[1] != '#')
5426
continue;
5427
5428
/* skip the space */
5429
i = 2;
5430
while (szLine[i] == ' ' || szLine[i] == '\t')
5431
++i;
5432
5433
if (!eqNByte((u8 *)(szLine + i), (u8 *)("START"), 5)) {
5434
RTW_ERR("Missing \"## START\" label\n");
5435
goto exit;
5436
}
5437
5438
loadingStage = LD_STAGE_COLUMN_DEFINE;
5439
} else if (loadingStage == LD_STAGE_COLUMN_DEFINE) {
5440
/* read "## #5# FCC ETSI MKK IC KCC" */
5441
if (szLine[0] != '#' || szLine[1] != '#')
5442
continue;
5443
5444
/* skip the space */
5445
i = 2;
5446
while (szLine[i] == ' ' || szLine[i] == '\t')
5447
++i;
5448
5449
_rtw_memset((void *) colNumBuf, 0, 10);
5450
if (!ParseQualifiedString(szLine, &i, colNumBuf, '#', '#')) {
5451
RTW_ERR("Fail to parse column number!\n");
5452
goto exit;
5453
}
5454
if (!GetU1ByteIntegerFromStringInDecimal(colNumBuf, &colNum)) {
5455
RTW_ERR("Column number \"%s\" is not unsigned decimal\n", colNumBuf);
5456
goto exit;
5457
}
5458
if (colNum == 0) {
5459
RTW_ERR("Column number is 0\n");
5460
goto exit;
5461
}
5462
5463
if (DBG_TXPWR_LMT_FILE_PARSE)
5464
RTW_PRINT("[%s][%s][%s][%s] column num:%d\n", band, bandwidth, rateSection, ntx, colNum);
5465
5466
regulation = (char **)rtw_zmalloc(sizeof(char *) * colNum);
5467
if (!regulation) {
5468
RTW_ERR("Regulation alloc fail\n");
5469
goto exit;
5470
}
5471
5472
for (forCnt = 0; forCnt < colNum; ++forCnt) {
5473
u32 i_ns;
5474
5475
/* skip the space */
5476
while (szLine[i] == ' ' || szLine[i] == '\t')
5477
i++;
5478
i_ns = i;
5479
5480
while (szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0')
5481
i++;
5482
5483
regulation[forCnt] = (char *)rtw_malloc(i - i_ns + 1);
5484
if (!regulation[forCnt]) {
5485
RTW_ERR("Regulation alloc fail\n");
5486
goto exit;
5487
}
5488
5489
_rtw_memcpy(regulation[forCnt], szLine + i_ns, i - i_ns);
5490
regulation[forCnt][i - i_ns] = '\0';
5491
}
5492
5493
if (DBG_TXPWR_LMT_FILE_PARSE) {
5494
RTW_PRINT("column name:");
5495
for (forCnt = 0; forCnt < colNum; ++forCnt)
5496
_RTW_PRINT(" %s", regulation[forCnt]);
5497
_RTW_PRINT("\n");
5498
}
5499
5500
loadingStage = LD_STAGE_CH_ROW;
5501
} else if (loadingStage == LD_STAGE_CH_ROW) {
5502
char channel[10] = {0}, powerLimit[10] = {0};
5503
u8 cnt = 0;
5504
5505
/* the table ends */
5506
if (szLine[0] == '#' && szLine[1] == '#') {
5507
i = 2;
5508
while (szLine[i] == ' ' || szLine[i] == '\t')
5509
++i;
5510
5511
if (eqNByte((u8 *)(szLine + i), (u8 *)("END"), 3)) {
5512
loadingStage = LD_STAGE_TAB_DEFINE;
5513
if (regulation) {
5514
for (forCnt = 0; forCnt < colNum; ++forCnt) {
5515
if (regulation[forCnt]) {
5516
rtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1);
5517
regulation[forCnt] = NULL;
5518
}
5519
}
5520
rtw_mfree((u8 *)regulation, sizeof(char *) * colNum);
5521
regulation = NULL;
5522
}
5523
colNum = 0;
5524
continue;
5525
} else {
5526
RTW_ERR("Missing \"## END\" label\n");
5527
goto exit;
5528
}
5529
}
5530
5531
if ((szLine[0] != 'c' && szLine[0] != 'C') ||
5532
(szLine[1] != 'h' && szLine[1] != 'H')
5533
) {
5534
RTW_WARN("Wrong channel prefix: '%c','%c'(%d,%d)\n", szLine[0], szLine[1], szLine[0], szLine[1]);
5535
continue;
5536
}
5537
i = 2;/* move to the location behind 'h' */
5538
5539
/* load the channel number */
5540
cnt = 0;
5541
while (szLine[i] >= '0' && szLine[i] <= '9') {
5542
channel[cnt] = szLine[i];
5543
++cnt;
5544
++i;
5545
}
5546
/* RTW_INFO("chnl %s!\n", channel); */
5547
5548
for (forCnt = 0; forCnt < colNum; ++forCnt) {
5549
/* skip the space between channel number and the power limit value */
5550
while (szLine[i] == ' ' || szLine[i] == '\t')
5551
++i;
5552
5553
/* load the power limit value */
5554
_rtw_memset((void *) powerLimit, 0, 10);
5555
5556
if (szLine[i] == 'W' && szLine[i + 1] == 'W') {
5557
/*
5558
* case "WW" assign special ww value
5559
* means to get minimal limit in other regulations at same channel
5560
*/
5561
s8 ww_value = phy_txpwr_ww_lmt_value(Adapter);
5562
5563
sprintf(powerLimit, "%d", ww_value);
5564
i += 2;
5565
5566
} else if (szLine[i] == 'N' && szLine[i + 1] == 'A') {
5567
/*
5568
* case "NA" assign max txgi value
5569
* means no limitation
5570
*/
5571
sprintf(powerLimit, "%d", hal_spec->txgi_max);
5572
i += 2;
5573
5574
} else if ((szLine[i] >= '0' && szLine[i] <= '9') || szLine[i] == '.'
5575
|| szLine[i] == '+' || szLine[i] == '-'
5576
){
5577
/* case of dBm value */
5578
u8 integer = 0, fraction = 0, negative = 0;
5579
u32 u4bMove;
5580
s8 lmt = 0;
5581
5582
if (szLine[i] == '+' || szLine[i] == '-') {
5583
if (szLine[i] == '-')
5584
negative = 1;
5585
i++;
5586
}
5587
5588
if (GetFractionValueFromString(&szLine[i], &integer, &fraction, &u4bMove))
5589
i += u4bMove;
5590
else {
5591
RTW_ERR("Limit \"%s\" is not valid decimal\n", &szLine[i]);
5592
goto exit;
5593
}
5594
5595
/* transform to string of value in unit of txgi */
5596
lmt = integer * hal_spec->txgi_pdbm + ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
5597
if (negative)
5598
lmt = -lmt;
5599
sprintf(powerLimit, "%d", lmt);
5600
5601
} else {
5602
RTW_ERR("Wrong limit expression \"%c%c\"(%d, %d)\n"
5603
, szLine[i], szLine[i + 1], szLine[i], szLine[i + 1]);
5604
goto exit;
5605
}
5606
5607
/* store the power limit value */
5608
phy_set_tx_power_limit(pDM_Odm, (u8 *)regulation[forCnt], (u8 *)band,
5609
(u8 *)bandwidth, (u8 *)rateSection, (u8 *)ntx, (u8 *)channel, (u8 *)powerLimit);
5610
5611
}
5612
}
5613
}
5614
5615
rtStatus = _SUCCESS;
5616
5617
exit:
5618
if (regulation) {
5619
for (forCnt = 0; forCnt < colNum; ++forCnt) {
5620
if (regulation[forCnt]) {
5621
rtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1);
5622
regulation[forCnt] = NULL;
5623
}
5624
}
5625
rtw_mfree((u8 *)regulation, sizeof(char *) * colNum);
5626
regulation = NULL;
5627
}
5628
5629
RTW_INFO("%s return %d\n", __func__, rtStatus);
5630
return rtStatus;
5631
}
5632
5633
int
5634
PHY_ConfigRFWithPowerLimitTableParaFile(
5635
PADAPTER Adapter,
5636
const char *pFileName
5637
)
5638
{
5639
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
5640
int rlen = 0, rtStatus = _FAIL;
5641
5642
if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_TXPWR_LMT_PARA_FILE))
5643
return rtStatus;
5644
5645
_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
5646
5647
if (pHalData->rf_tx_pwr_lmt == NULL) {
5648
rtw_get_phy_file_path(Adapter, pFileName);
5649
if (rtw_readable_file_sz_chk(rtw_phy_para_file_path,
5650
MAX_PARA_FILE_BUF_LEN) == _TRUE) {
5651
rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
5652
if (rlen > 0) {
5653
rtStatus = _SUCCESS;
5654
pHalData->rf_tx_pwr_lmt = rtw_zvmalloc(rlen);
5655
if (pHalData->rf_tx_pwr_lmt) {
5656
_rtw_memcpy(pHalData->rf_tx_pwr_lmt, pHalData->para_file_buf, rlen);
5657
pHalData->rf_tx_pwr_lmt_len = rlen;
5658
} else
5659
RTW_INFO("%s rf_tx_pwr_lmt alloc fail !\n", __FUNCTION__);
5660
}
5661
}
5662
} else {
5663
if ((pHalData->rf_tx_pwr_lmt_len != 0) && (pHalData->rf_tx_pwr_lmt != NULL)) {
5664
_rtw_memcpy(pHalData->para_file_buf, pHalData->rf_tx_pwr_lmt, pHalData->rf_tx_pwr_lmt_len);
5665
rtStatus = _SUCCESS;
5666
} else
5667
RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
5668
}
5669
5670
if (rtStatus == _SUCCESS) {
5671
/* RTW_INFO("%s(): read %s ok\n", __FUNCTION__, pFileName); */
5672
rtStatus = phy_ParsePowerLimitTableFile(Adapter, pHalData->para_file_buf);
5673
} else
5674
RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
5675
5676
return rtStatus;
5677
}
5678
#endif /* CONFIG_TXPWR_LIMIT */
5679
5680
void phy_free_filebuf_mask(_adapter *padapter, u8 mask)
5681
{
5682
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
5683
5684
if (pHalData->mac_reg && (mask & LOAD_MAC_PARA_FILE)) {
5685
rtw_vmfree(pHalData->mac_reg, pHalData->mac_reg_len);
5686
pHalData->mac_reg = NULL;
5687
}
5688
if (mask & LOAD_BB_PARA_FILE) {
5689
if (pHalData->bb_phy_reg) {
5690
rtw_vmfree(pHalData->bb_phy_reg, pHalData->bb_phy_reg_len);
5691
pHalData->bb_phy_reg = NULL;
5692
}
5693
if (pHalData->bb_agc_tab) {
5694
rtw_vmfree(pHalData->bb_agc_tab, pHalData->bb_agc_tab_len);
5695
pHalData->bb_agc_tab = NULL;
5696
}
5697
}
5698
if (pHalData->bb_phy_reg_pg && (mask & LOAD_BB_PG_PARA_FILE)) {
5699
rtw_vmfree(pHalData->bb_phy_reg_pg, pHalData->bb_phy_reg_pg_len);
5700
pHalData->bb_phy_reg_pg = NULL;
5701
}
5702
if (pHalData->bb_phy_reg_mp && (mask & LOAD_BB_MP_PARA_FILE)) {
5703
rtw_vmfree(pHalData->bb_phy_reg_mp, pHalData->bb_phy_reg_mp_len);
5704
pHalData->bb_phy_reg_mp = NULL;
5705
}
5706
if (mask & LOAD_RF_PARA_FILE) {
5707
if (pHalData->rf_radio_a) {
5708
rtw_vmfree(pHalData->rf_radio_a, pHalData->rf_radio_a_len);
5709
pHalData->rf_radio_a = NULL;
5710
}
5711
if (pHalData->rf_radio_b) {
5712
rtw_vmfree(pHalData->rf_radio_b, pHalData->rf_radio_b_len);
5713
pHalData->rf_radio_b = NULL;
5714
}
5715
}
5716
if (pHalData->rf_tx_pwr_track && (mask & LOAD_RF_TXPWR_TRACK_PARA_FILE)) {
5717
rtw_vmfree(pHalData->rf_tx_pwr_track, pHalData->rf_tx_pwr_track_len);
5718
pHalData->rf_tx_pwr_track = NULL;
5719
}
5720
if (pHalData->rf_tx_pwr_lmt && (mask & LOAD_RF_TXPWR_LMT_PARA_FILE)) {
5721
rtw_vmfree(pHalData->rf_tx_pwr_lmt, pHalData->rf_tx_pwr_lmt_len);
5722
pHalData->rf_tx_pwr_lmt = NULL;
5723
}
5724
}
5725
5726
inline void phy_free_filebuf(_adapter *padapter)
5727
{
5728
phy_free_filebuf_mask(padapter, 0xFF);
5729
}
5730
5731
#endif
5732
5733
s8
5734
phy_get_tx_power_final_absolute_value(_adapter *adapter, u8 rfpath, u8 rate,
5735
enum channel_width bw, u8 channel)
5736
{
5737
#ifdef CONFIG_USE_TSSI
5738
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
5739
u8 powerByRate = 0, powerLimit = 0;
5740
bool bIn24G = channel <= 14;
5741
s8 value = 0;
5742
u8 ntx_idx = phy_get_current_tx_num(adapter, rate);
5743
5744
if (!bIn24G && IS_CCK_RATE(rate))
5745
return 0;
5746
5747
powerByRate = PHY_GetTxPowerByRateOriginal(adapter, (u8)(!bIn24G), rfpath, rate);
5748
powerByRate /= hal_spec->txgi_pdbm;
5749
5750
#if CONFIG_TXPWR_LIMIT
5751
powerLimit = PHY_GetTxPowerLimitOriginal(adapter, NULL, (BAND_TYPE)(!bIn24G), bw, rfpath, rate, ntx_idx, channel);
5752
#else
5753
powerLimit = hal_spec->txgi_max;
5754
#endif
5755
powerLimit /= hal_spec->txgi_pdbm;
5756
5757
value = (powerByRate > powerLimit ? powerLimit : powerByRate);
5758
5759
return value;
5760
#else
5761
return 0;
5762
#endif
5763
}
5764
5765