CoCalc -- hal

GitHub Repository: nu11secur1ty/Kali-Linux
Path: blob/master/ALFA-W1F1/RTL8814AU/hal/hal_mp.c
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/******************************************************************************
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 *
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 * Copyright(c) 2007 - 2017 Realtek Corporation.
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 *
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms of version 2 of the GNU General Public License as
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 * published by the Free Software Foundation.
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 *
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 * This program is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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 * more details.
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 *
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 *****************************************************************************/
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#define _HAL_MP_C_
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#include <drv_types.h>
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#ifdef CONFIG_MP_INCLUDED
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#ifdef RTW_HALMAC
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	#include <hal_data.h>		/* struct HAL_DATA_TYPE, RF register definition and etc. */
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#else /* !RTW_HALMAC */
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	#ifdef CONFIG_RTL8188E
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		#include <rtl8188e_hal.h>
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	#endif
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	#ifdef CONFIG_RTL8723B
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		#include <rtl8723b_hal.h>
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	#endif
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	#ifdef CONFIG_RTL8192E
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		#include <rtl8192e_hal.h>
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	#endif
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	#ifdef CONFIG_RTL8814A
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		#include <rtl8814a_hal.h>
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	#endif
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	#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
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		#include <rtl8812a_hal.h>
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	#endif
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	#ifdef CONFIG_RTL8703B
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		#include <rtl8703b_hal.h>
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	#endif
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	#ifdef CONFIG_RTL8723D
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		#include <rtl8723d_hal.h>
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	#endif
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	#ifdef CONFIG_RTL8710B
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		#include <rtl8710b_hal.h>
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	#endif
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	#ifdef CONFIG_RTL8188F
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		#include <rtl8188f_hal.h>
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	#endif
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	#ifdef CONFIG_RTL8188GTV
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		#include <rtl8188gtv_hal.h>
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	#endif
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	#ifdef CONFIG_RTL8192F
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		#include <rtl8192f_hal.h>
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	#endif
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#endif /* !RTW_HALMAC */
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u8 MgntQuery_NssTxRate(u16 Rate)
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{
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	u8	NssNum = RF_TX_NUM_NONIMPLEMENT;
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	if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||
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	    (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))
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		NssNum = RF_2TX;
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	else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||
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		 (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))
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		NssNum = RF_3TX;
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	else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||
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		 (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))
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		NssNum = RF_4TX;
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	else
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		NssNum = RF_1TX;
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	return NssNum;
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}
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void hal_mpt_SwitchRfSetting(PADAPTER	pAdapter)
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{
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	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
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	u8				ChannelToSw = pMptCtx->MptChannelToSw;
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	u32				ulRateIdx = pMptCtx->mpt_rate_index;
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	u32				ulbandwidth = pMptCtx->MptBandWidth;
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	/* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
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	if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
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	    (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
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		pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
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		pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
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		if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
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			phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB);
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			phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB);
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		} else {
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			phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
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			phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
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		}
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	} else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
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		if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
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			phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
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			phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
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		} else {
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			phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
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			phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
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		}
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	} else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
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		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
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		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
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	}
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}
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s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
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{
115
	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
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	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
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119
	if (!netif_running(padapter->pnetdev)) {
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		return _FAIL;
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	}
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	if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
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		return _FAIL;
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	}
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	if (enable)
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		pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
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	else
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		pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
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131
	return _SUCCESS;
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}
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void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
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{
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	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
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	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
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139

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	*enable = pDM_Odm->rf_calibrate_info.txpowertrack_control;
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}
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void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
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{
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	u32		TempVal = 0, TempVal2 = 0, TempVal3 = 0;
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	u32		CurrCCKSwingVal = 0, CCKSwingIndex = 12;
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	u8		i;
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	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
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	PMPT_CONTEXT		pMptCtx = &(Adapter->mppriv.mpt_ctx);
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	u8				u1Channel = pHalData->current_channel;
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	u32				ulRateIdx = pMptCtx->mpt_rate_index;
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	u8				DataRate = 0xFF;
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	/* Do not modify CCK TX filter parameters for 8822B*/
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	if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) ||
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		IS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8192F(Adapter) || IS_HARDWARE_TYPE_8822C(Adapter))
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		return;
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160
	DataRate = mpt_to_mgnt_rate(ulRateIdx);
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	if (u1Channel == 14 && IS_CCK_RATE(DataRate))
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		pHalData->bCCKinCH14 = TRUE;
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	else
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		pHalData->bCCKinCH14 = FALSE;
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	if (IS_HARDWARE_TYPE_8703B(Adapter)) {
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		if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
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			/* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
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			phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
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			phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
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173
		} else {
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			/* Normal setting for 8703B, just recover to the default setting. */
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			/* This hardcore values reference from the parameter which BB team gave. */
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			for (i = 0 ; i < 2 ; ++i)
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				phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
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		}
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	} else if (IS_HARDWARE_TYPE_8723D(Adapter)) {
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		/* 2.4G CCK TX DFIR */
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		/* 2016.01.20 Suggest from RS BB mingzhi*/
183
		if ((u1Channel == 14)) {
184
			phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
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			phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
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			phy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
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		} else {
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			for (i = 0 ; i < 3 ; ++i) {
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				phy_set_bb_reg(Adapter,
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					     pHalData->RegForRecover[i].offset,
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					     bMaskDWord,
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					     pHalData->RegForRecover[i].value);
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			}
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		}
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	} else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
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		/* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
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		CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
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		CCKSwingIndex = 20; /* default index */
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		if (!pHalData->bCCKinCH14) {
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			/* Readback the current bb cck swing value and compare with the table to */
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			/* get the current swing index */
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			for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
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				if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) &&
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				    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) {
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					CCKSwingIndex = i;
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					break;
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				}
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			}
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			write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]);
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			write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]);
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			write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]);
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			write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]);
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			write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]);
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			write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]);
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			write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]);
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			write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]);
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			write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]);
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			write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]);
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			write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]);
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			write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]);
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			write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]);
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			write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]);
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			write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]);
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			write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]);
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			RTW_INFO("%s , cck_swing_table_ch1_ch13_88f[%d]\n", __func__, CCKSwingIndex);
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		}  else {
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			for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
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				if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) &&
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				    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) {
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					CCKSwingIndex = i;
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					break;
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				}
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			}
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			write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]);
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			write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]);
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			write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]);
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			write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]);
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			write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]);
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			write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]);
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			write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]);
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			write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]);
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			write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]);
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			write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]);
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			write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]);
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			write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]);
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			write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]);
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			write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]);
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			write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]);
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			write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]);
251
			RTW_INFO("%s , cck_swing_table_ch14_88f[%d]\n", __func__, CCKSwingIndex);
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		}
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	} else {
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		/* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
256
		CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
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258
		if (!pHalData->bCCKinCH14) {
259
			/* Readback the current bb cck swing value and compare with the table to */
260
			/* get the current swing index */
261
			for (i = 0; i < CCK_TABLE_SIZE; i++) {
262
				if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13[i][0]) &&
263
				    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13[i][1])) {
264
					CCKSwingIndex = i;
265
					break;
266
				}
267
			}
268

269
			/*Write 0xa22 0xa23*/
270
			TempVal = cck_swing_table_ch1_ch13[CCKSwingIndex][0] +
271
				(cck_swing_table_ch1_ch13[CCKSwingIndex][1] << 8);
272

273

274
			/*Write 0xa24 ~ 0xa27*/
275
			TempVal2 = 0;
276
			TempVal2 = cck_swing_table_ch1_ch13[CCKSwingIndex][2] +
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				(cck_swing_table_ch1_ch13[CCKSwingIndex][3] << 8) +
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				(cck_swing_table_ch1_ch13[CCKSwingIndex][4] << 16) +
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				(cck_swing_table_ch1_ch13[CCKSwingIndex][5] << 24);
280

281
			/*Write 0xa28  0xa29*/
282
			TempVal3 = 0;
283
			TempVal3 = cck_swing_table_ch1_ch13[CCKSwingIndex][6] +
284
				(cck_swing_table_ch1_ch13[CCKSwingIndex][7] << 8);
285
		}  else {
286
			for (i = 0; i < CCK_TABLE_SIZE; i++) {
287
				if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14[i][0]) &&
288
				    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14[i][1])) {
289
					CCKSwingIndex = i;
290
					break;
291
				}
292
			}
293

294
			/*Write 0xa22 0xa23*/
295
			TempVal = cck_swing_table_ch14[CCKSwingIndex][0] +
296
				  (cck_swing_table_ch14[CCKSwingIndex][1] << 8);
297

298
			/*Write 0xa24 ~ 0xa27*/
299
			TempVal2 = 0;
300
			TempVal2 = cck_swing_table_ch14[CCKSwingIndex][2] +
301
				   (cck_swing_table_ch14[CCKSwingIndex][3] << 8) +
302
				(cck_swing_table_ch14[CCKSwingIndex][4] << 16) +
303
				   (cck_swing_table_ch14[CCKSwingIndex][5] << 24);
304

305
			/*Write 0xa28  0xa29*/
306
			TempVal3 = 0;
307
			TempVal3 = cck_swing_table_ch14[CCKSwingIndex][6] +
308
				   (cck_swing_table_ch14[CCKSwingIndex][7] << 8);
309
		}
310

311
		write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
312
		write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
313
		write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
314
	}
315

316
}
317

318
void hal_mpt_SetChannel(PADAPTER pAdapter)
319
{
320
	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
321
	struct mp_priv	*pmp = &pAdapter->mppriv;
322
	u8		channel = pmp->channel;
323
	u8		bandwidth = pmp->bandwidth;
324

325
	hal_mpt_SwitchRfSetting(pAdapter);
326

327
	pHalData->bSwChnl = _TRUE;
328
	pHalData->bSetChnlBW = _TRUE;
329

330
	if (bandwidth == 2) {
331
		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
332
	} else if (bandwidth == 1) {
333
		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
334
	} else
335
		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
336

337
	hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
338
	rtw_btcoex_wifionly_scan_notify(pAdapter);
339

340
}
341

342
/*
343
 * Notice
344
 *	Switch bandwitdth may change center frequency(channel)
345
 */
346
void hal_mpt_SetBandwidth(PADAPTER pAdapter)
347
{
348
	struct mp_priv *pmp = &pAdapter->mppriv;
349
	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
350

351
	u8		channel = pmp->channel;
352
	u8		bandwidth = pmp->bandwidth;
353

354
	pHalData->bSwChnl = _TRUE;
355
	pHalData->bSetChnlBW = _TRUE;
356

357
	if (bandwidth == 2) {
358
		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
359
	} else if (bandwidth == 1) {
360
		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
361
	} else
362
		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
363

364
	hal_mpt_SwitchRfSetting(pAdapter);
365
	rtw_btcoex_wifionly_scan_notify(pAdapter);
366

367
}
368

369
void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
370
{
371
	switch (Rate) {
372
	case MPT_CCK: {
373
		u32	TxAGC = 0, pwr = 0;
374

375
		pwr = pTxPower[RF_PATH_A];
376
		if (pwr < 0x3f) {
377
			TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
378
			phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[RF_PATH_A]);
379
			phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
380
		}
381
		pwr = pTxPower[RF_PATH_B];
382
		if (pwr < 0x3f) {
383
			TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
384
			phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[RF_PATH_B]);
385
			phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
386
		}
387
	}
388
	break;
389

390
	case MPT_OFDM_AND_HT: {
391
		u32	TxAGC = 0;
392
		u8	pwr = 0;
393

394
		pwr = pTxPower[0];
395
		if (pwr < 0x3f) {
396
			TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
397
			RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
398
			phy_set_bb_reg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
399
			phy_set_bb_reg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
400
			phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
401
			phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
402
			phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
403
			phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
404
		}
405
		TxAGC = 0;
406
		pwr = pTxPower[1];
407
		if (pwr < 0x3f) {
408
			TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
409
			RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
410
			phy_set_bb_reg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
411
			phy_set_bb_reg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
412
			phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
413
			phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
414
			phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
415
			phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
416
		}
417
	}
418
	break;
419

420
	default:
421
		break;
422
	}
423
	RTW_INFO("<===mpt_SetTxPower_Old()\n");
424
}
425

426
void
427
mpt_SetTxPower(
428
	PADAPTER		pAdapter,
429
	MPT_TXPWR_DEF	Rate,
430
	u8 *pTxPower
431
)
432
{
433
	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
434

435
	u8 path = 0 , i = 0, MaxRate = MGN_6M;
436
	u8 StartPath = RF_PATH_A, EndPath = RF_PATH_B;
437

438
	if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8814B(pAdapter))
439
		EndPath = RF_PATH_D;
440
	else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)
441
		|| IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
442
		EndPath = RF_PATH_A;
443

444
	switch (Rate) {
445
	case MPT_CCK: {
446
		u8 rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
447

448
		for (path = StartPath; path <= EndPath; path++)
449
			for (i = 0; i < sizeof(rate); ++i)
450
				PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
451
	}
452
	break;
453
	case MPT_OFDM: {
454
		u8 rate[] = {
455
			MGN_6M, MGN_9M, MGN_12M, MGN_18M,
456
			MGN_24M, MGN_36M, MGN_48M, MGN_54M,
457
		};
458

459
		for (path = StartPath; path <= EndPath; path++)
460
			for (i = 0; i < sizeof(rate); ++i)
461
				PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
462
	}
463
	break;
464
	case MPT_HT: {
465
		u8 rate[] = {
466
			MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
467
			MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
468
			MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
469
			MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,
470
			MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,
471
			MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,
472
			MGN_MCS30, MGN_MCS31,
473
		};
474
		if (pHalData->rf_type == RF_3T3R)
475
			MaxRate = MGN_MCS23;
476
		else if (pHalData->rf_type == RF_2T2R)
477
			MaxRate = MGN_MCS15;
478
		else
479
			MaxRate = MGN_MCS7;
480
		for (path = StartPath; path <= EndPath; path++) {
481
			for (i = 0; i < sizeof(rate); ++i) {
482
				if (rate[i] > MaxRate)
483
					break;
484
				PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
485
			}
486
		}
487
	}
488
	break;
489
	case MPT_VHT: {
490
		u8 rate[] = {
491
			MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
492
			MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
493
			MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
494
			MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,
495
			MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
496
			MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,
497
			MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
498
			MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,
499
		};
500
		if (pHalData->rf_type == RF_3T3R)
501
			MaxRate = MGN_VHT3SS_MCS9;
502
		else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
503
			MaxRate = MGN_VHT2SS_MCS9;
504
		else
505
			MaxRate = MGN_VHT1SS_MCS9;
506

507
		for (path = StartPath; path <= EndPath; path++) {
508
			for (i = 0; i < sizeof(rate); ++i) {
509
				if (rate[i] > MaxRate)
510
					break;
511
				PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
512
			}
513
		}
514
	}
515
	break;
516
	default:
517
		RTW_INFO("<===mpt_SetTxPower: Illegal channel!!\n");
518
		break;
519
	}
520
}
521

522
void hal_mpt_SetTxPower(PADAPTER pAdapter)
523
{
524
	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
525
	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
526
	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
527

528
	if (pHalData->rf_chip < RF_CHIP_MAX) {
529
		if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
530
		    IS_HARDWARE_TYPE_8723B(pAdapter) ||
531
		    IS_HARDWARE_TYPE_8192E(pAdapter) ||
532
		    IS_HARDWARE_TYPE_8703B(pAdapter) ||
533
		    IS_HARDWARE_TYPE_8188F(pAdapter) ||
534
		    IS_HARDWARE_TYPE_8188GTV(pAdapter)
535
		) {
536

537
			RTW_INFO("===> MPT_ProSetTxPower: Old\n");
538

539
			mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
540
			mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
541

542
		} else {
543

544
			mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
545
			mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
546
			mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
547
			if(IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
548
				RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
549
				mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
550
			}
551
		}
552

553
		rtw_hal_set_txpwr_done(pAdapter);
554
	} else
555
		RTW_INFO("RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
556

557
	odm_clear_txpowertracking_state(pDM_Odm);
558
}
559

560
void hal_mpt_SetDataRate(PADAPTER pAdapter)
561
{
562
	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
563
	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
564
	u32 DataRate;
565

566
	DataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
567

568
	hal_mpt_SwitchRfSetting(pAdapter);
569

570
	hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
571
#ifdef CONFIG_RTL8723B
572
	if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
573
		if (IS_CCK_RATE(DataRate)) {
574
			if (pMptCtx->mpt_rf_path == RF_PATH_A)
575
				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0x6);
576
			else
577
				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0x6);
578
		} else {
579
			if (pMptCtx->mpt_rf_path == RF_PATH_A)
580
				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
581
			else
582
				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
583
		}
584
	}
585

586
	if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
587
	     ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
588
		if (pMptCtx->mpt_rf_path == RF_PATH_A)
589
			phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
590
		else
591
			phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
592
	}
593
#endif
594
}
595

596
#define RF_PATH_AB	22
597

598
#ifdef CONFIG_RTL8814A
599
void mpt_ToggleIG_8814A(PADAPTER	pAdapter)
600
{
601
	u8 Path;
602
	u32 IGReg = rA_IGI_Jaguar, IGvalue = 0;
603

604
	for (Path = 0; Path <= RF_PATH_D; Path++) {
605
		switch (Path) {
606
		case RF_PATH_B:
607
			IGReg = rB_IGI_Jaguar;
608
			break;
609
		case RF_PATH_C:
610
			IGReg = rC_IGI_Jaguar2;
611
			break;
612
		case RF_PATH_D:
613
			IGReg = rD_IGI_Jaguar2;
614
			break;
615
		default:
616
			IGReg = rA_IGI_Jaguar;
617
			break;
618
		}
619

620
		IGvalue = phy_query_bb_reg(pAdapter, IGReg, bMaskByte0);
621
		phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);
622
		phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue);
623
	}
624
}
625

626
void mpt_SetRFPath_8814A(PADAPTER	pAdapter)
627
{
628

629
	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
630
	PMPT_CONTEXT	pMptCtx = &pAdapter->mppriv.mpt_ctx;
631
	R_ANTENNA_SELECT_OFDM	*p_ofdm_tx;	/* OFDM Tx register */
632
	R_ANTENNA_SELECT_CCK	*p_cck_txrx;
633
	u8	ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
634
	/*/PRT_HIGH_THROUGHPUT		pHTInfo = GET_HT_INFO(pMgntInfo);*/
635
	/*/PRT_VERY_HIGH_THROUGHPUT	pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
636

637
	u32	ulAntennaTx = pHalData->antenna_tx_path;
638
	u32	ulAntennaRx = pHalData->AntennaRxPath;
639
	u8	NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
640

641
	if (NssforRate == RF_3TX) {
642
		RTW_INFO("===> SetAntenna 3T Rate ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
643

644
		switch (ulAntennaTx) {
645
		case ANTENNA_BCD:
646
			pMptCtx->mpt_rf_path = RF_PATH_BCD;
647
			/*pHalData->ValidTxPath = 0x0e;*/
648
			phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e);	/*/ 0x940[27:16]=12'b0010_0100_0111*/
649
			break;
650

651
		case ANTENNA_ABC:
652
		default:
653
			pMptCtx->mpt_rf_path = RF_PATH_ABC;
654
			/*pHalData->ValidTxPath = 0x0d;*/
655
			phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247);	/*/ 0x940[27:16]=12'b0010_0100_0111*/
656
			break;
657
		}
658

659
	} else { /*/if(NssforRate == RF_1TX)*/
660
		RTW_INFO("===> SetAntenna for 1T/2T Rate, ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
661
		switch (ulAntennaTx) {
662
		case ANTENNA_BCD:
663
			pMptCtx->mpt_rf_path = RF_PATH_BCD;
664
			/*pHalData->ValidTxPath = 0x0e;*/
665
			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
666
			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
667
			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
668
			break;
669

670
		case ANTENNA_BC:
671
			pMptCtx->mpt_rf_path = RF_PATH_BC;
672
			/*pHalData->ValidTxPath = 0x06;*/
673
			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
674
			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
675
			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
676
			break;
677
		case ANTENNA_B:
678
			pMptCtx->mpt_rf_path = RF_PATH_B;
679
			/*pHalData->ValidTxPath = 0x02;*/
680
			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4);			/*/ 0xa07[7:4] = 4'b0100*/
681
			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002);	/*/ 0x93C[31:20]=12'b0000_0000_0010*/
682
			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2);					/* 0x80C[7:4] = 4'b0010*/
683
			break;
684

685
		case ANTENNA_C:
686
			pMptCtx->mpt_rf_path = RF_PATH_C;
687
			/*pHalData->ValidTxPath = 0x04;*/
688
			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2);			/*/ 0xa07[7:4] = 4'b0010*/
689
			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004);	/*/ 0x93C[31:20]=12'b0000_0000_0100*/
690
			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4);					/*/ 0x80C[7:4] = 4'b0100*/
691
			break;
692

693
		case ANTENNA_D:
694
			pMptCtx->mpt_rf_path = RF_PATH_D;
695
			/*pHalData->ValidTxPath = 0x08;*/
696
			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1);			/*/ 0xa07[7:4] = 4'b0001*/
697
			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008);	/*/ 0x93C[31:20]=12'b0000_0000_1000*/
698
			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8);					/*/ 0x80C[7:4] = 4'b1000*/
699
			break;
700

701
		case ANTENNA_A:
702
		default:
703
			pMptCtx->mpt_rf_path = RF_PATH_A;
704
			/*pHalData->ValidTxPath = 0x01;*/
705
			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8);			/*/ 0xa07[7:4] = 4'b1000*/
706
			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001);	/*/ 0x93C[31:20]=12'b0000_0000_0001*/
707
			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1);					/*/ 0x80C[7:4] = 4'b0001*/
708
			break;
709
		}
710
	}
711

712
	switch (ulAntennaRx) {
713
	case ANTENNA_A:
714
		/*pHalData->ValidRxPath = 0x01;*/
715
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
716
		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
717
		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
718
		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
719
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
720
		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
721
		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
722
		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
723
		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
724
		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
725
		/*/ CCA related PD_delay_th*/
726
		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
727
		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
728
		break;
729

730
	case ANTENNA_B:
731
		/*pHalData->ValidRxPath = 0x02;*/
732
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
733
		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
734
		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
735
		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
736
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
737
		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
738
		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
739
		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
740
		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
741
		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
742
		/*/ CCA related PD_delay_th*/
743
		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
744
		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
745
		break;
746

747
	case ANTENNA_C:
748
		/*pHalData->ValidRxPath = 0x04;*/
749
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
750
		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
751
		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
752
		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
753
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
754
		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
755
		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
756
		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
757
		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
758
		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
759
		/*/ CCA related PD_delay_th*/
760
		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
761
		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
762
		break;
763

764
	case ANTENNA_D:
765
		/*pHalData->ValidRxPath = 0x08;*/
766
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
767
		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
768
		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
769
		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
770
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
771
		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
772
		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
773
		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
774
		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
775
		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
776
		/*/ CCA related PD_delay_th*/
777
		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
778
		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
779
		break;
780

781
	case ANTENNA_BC:
782
		/*pHalData->ValidRxPath = 0x06;*/
783
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
784
		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
785
		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
786
		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
787
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
788
		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
789
		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
790
		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
791
		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
792
		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
793
		/*/ CCA related PD_delay_th*/
794
		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
795
		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
796
		break;
797

798
	case ANTENNA_CD:
799
		/*pHalData->ValidRxPath = 0x0C;*/
800
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
801
		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
802
		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
803
		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
804
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
805
		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
806
		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
807
		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
808
		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
809
		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
810
		/*/ CCA related PD_delay_th*/
811
		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
812
		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
813
		break;
814

815
	case ANTENNA_BCD:
816
		/*pHalData->ValidRxPath = 0x0e;*/
817
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
818
		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
819
		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
820
		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
821
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
822
		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
823
		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
824
		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
825
		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
826
		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
827
		/*/ CCA related PD_delay_th*/
828
		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
829
		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
830
		break;
831

832
	case ANTENNA_ABCD:
833
		/*pHalData->ValidRxPath = 0x0f;*/
834
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
835
		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
836
		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
837
		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
838
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
839
		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
840
		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
841
		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
842
		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
843
		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
844
		/*/ CCA related PD_delay_th*/
845
		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
846
		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
847
		break;
848

849
	default:
850
		break;
851
	}
852

853
	PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
854

855
	mpt_ToggleIG_8814A(pAdapter);
856
}
857
#endif /* CONFIG_RTL8814A */
858
#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)  || defined(CONFIG_RTL8822C)
859
void
860
mpt_SetSingleTone_8814A(
861
		PADAPTER	pAdapter,
862
		BOOLEAN	bSingleTone,
863
		BOOLEAN	bEnPMacTx)
864
{
865

866
	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
867
	u8 StartPath = RF_PATH_A,  EndPath = RF_PATH_A, path;
868
	static u32		regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
869

870
	if (bSingleTone) {
871
		regIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord);		/*/ 0xC1C[31:21]*/
872
		regIG1 = phy_query_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord);		/*/ 0xE1C[31:21]*/
873
		regIG2 = phy_query_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord);	/*/ 0x181C[31:21]*/
874
		regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord);	/*/ 0x1A1C[31:21]*/
875

876
		switch (pMptCtx->mpt_rf_path) {
877
		case RF_PATH_A:
878
		case RF_PATH_B:
879
		case RF_PATH_C:
880
		case RF_PATH_D:
881
			StartPath = pMptCtx->mpt_rf_path;
882
			EndPath = pMptCtx->mpt_rf_path;
883
			break;
884
		case RF_PATH_AB:
885
			EndPath = RF_PATH_B;
886
			break;
887
		case RF_PATH_BC:
888
			StartPath = RF_PATH_B;
889
			EndPath = RF_PATH_C;
890
			break;
891
		case RF_PATH_ABC:
892
			EndPath = RF_PATH_C;
893
			break;
894
		case RF_PATH_BCD:
895
			StartPath = RF_PATH_B;
896
			EndPath = RF_PATH_D;
897
			break;
898
		case RF_PATH_ABCD:
899
			EndPath = RF_PATH_D;
900
			break;
901
		}
902

903
		if (bEnPMacTx == FALSE) {
904
			hal_mpt_SetContinuousTx(pAdapter, _TRUE);
905
			issue_nulldata(pAdapter, NULL, 1, 3, 500);
906
		}
907

908
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
909

910
		for (path = StartPath; path <= EndPath; path++) {
911
			phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
912
			phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
913

914
			phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
915
		}
916

917
		phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
918
		phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
919
		phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
920
		phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
921
	} else {
922
		switch (pMptCtx->mpt_rf_path) {
923
		case RF_PATH_A:
924
		case RF_PATH_B:
925
		case RF_PATH_C:
926
		case RF_PATH_D:
927
			StartPath = pMptCtx->mpt_rf_path;
928
			EndPath = pMptCtx->mpt_rf_path;
929
			break;
930
		case RF_PATH_AB:
931
			EndPath = RF_PATH_B;
932
			break;
933
		case RF_PATH_BC:
934
			StartPath = RF_PATH_B;
935
			EndPath = RF_PATH_C;
936
			break;
937
		case RF_PATH_ABC:
938
			EndPath = RF_PATH_C;
939
			break;
940
		case RF_PATH_BCD:
941
			StartPath = RF_PATH_B;
942
			EndPath = RF_PATH_D;
943
			break;
944
		case RF_PATH_ABCD:
945
			EndPath = RF_PATH_D;
946
			break;
947
		}
948
		for (path = StartPath; path <= EndPath; path++)
949
			phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */
950

951
		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
952

953
		if (bEnPMacTx == FALSE)
954
			hal_mpt_SetContinuousTx(pAdapter, _FALSE);
955

956
		phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
957
		phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
958
		phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
959
		phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
960
	}
961
}
962

963
#endif
964

965
#if	defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
966
void mpt_SetRFPath_8812A(PADAPTER pAdapter)
967
{
968
	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
969
	PMPT_CONTEXT	pMptCtx = &pAdapter->mppriv.mpt_ctx;
970
	struct mp_priv *pmp = &pAdapter->mppriv;
971
	u8		channel = pmp->channel;
972
	u8		bandwidth = pmp->bandwidth;
973
	u8		eLNA_2g = pHalData->ExternalLNA_2G;
974
	u32		ulAntennaTx, ulAntennaRx;
975
	u32 reg0xC50 = 0;
976

977
	ulAntennaTx = pHalData->antenna_tx_path;
978
	ulAntennaRx = pHalData->AntennaRxPath;
979

980
	switch (ulAntennaTx) {
981
	case ANTENNA_A:
982
		pMptCtx->mpt_rf_path = RF_PATH_A;
983
		phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
984
		if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
985
			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
986
		break;
987
	case ANTENNA_B:
988
		pMptCtx->mpt_rf_path = RF_PATH_B;
989
		phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
990
		if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
991
			phy_set_bb_reg(pAdapter,	r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
992
		break;
993
	case ANTENNA_AB:
994
		pMptCtx->mpt_rf_path = RF_PATH_AB;
995
		phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
996
		if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
997
			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
998
		break;
999
	default:
1000
		pMptCtx->mpt_rf_path = RF_PATH_AB;
1001
		RTW_INFO("Unknown Tx antenna.\n");
1002
		break;
1003
	}
1004

1005
	switch (ulAntennaRx) {
1006
	case ANTENNA_A:
1007
		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
1008
		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
1009
		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1010
		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1011

1012
		/*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1013
		reg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
1014
		phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1015
		phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
1016

1017
		/* set PWED_TH for BB Yn user guide R29 */
1018
		if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1019
			if (channel <= 14) { /* 2.4G */
1020
				if (bandwidth == CHANNEL_WIDTH_20
1021
				    && eLNA_2g == 0) {
1022
					/* 0x830[3:1]=3'b010 */
1023
					phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1024
				} else
1025
					/* 0x830[3:1]=3'b100 */
1026
					phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1027
			} else
1028
				/* 0x830[3:1]=3'b100 for 5G */
1029
				phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1030
		}
1031
		break;
1032
	case ANTENNA_B:
1033
		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
1034
		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
1035
		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
1036
		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1037

1038
		/*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1039
		reg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
1040
		phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1041
		phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
1042

1043
		/* set PWED_TH for BB Yn user guide R29 */
1044
		if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1045
			if (channel <= 14) {
1046
				if (bandwidth == CHANNEL_WIDTH_20
1047
				    && eLNA_2g == 0) {
1048
					/* 0x830[3:1]=3'b010 */
1049
					phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1050
				} else
1051
					/* 0x830[3:1]=3'b100 */
1052
					phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1053
			} else
1054
				/* 0x830[3:1]=3'b100 for 5G */
1055
				phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1056
		}
1057
		break;
1058
	case ANTENNA_AB:
1059
		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
1060
		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
1061
		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1062
		/* set PWED_TH for BB Yn user guide R29 */
1063
		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1064
		break;
1065
	default:
1066
		RTW_INFO("Unknown Rx antenna.\n");
1067
		break;
1068
	}
1069

1070
	if (pHalData->rfe_type == 5 || pHalData->rfe_type == 1) {
1071
		if (ulAntennaTx == ANTENNA_A || ulAntennaTx == ANTENNA_AB) {
1072
			/* WiFi */
1073
			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x2);
1074
			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1075
		} else {
1076
			/* BT */
1077
			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x1);
1078
			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1079
		}
1080
	}
1081
}
1082
#endif
1083

1084
#ifdef CONFIG_RTL8723B
1085
void mpt_SetRFPath_8723B(PADAPTER pAdapter)
1086
{
1087
	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
1088
	u32		ulAntennaTx, ulAntennaRx;
1089
	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1090
	struct dm_struct	*pDM_Odm = &pHalData->odmpriv;
1091
	struct dm_rf_calibration_struct	*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1092
	u8 i;
1093

1094
	ulAntennaTx = pHalData->antenna_tx_path;
1095
	ulAntennaRx = pHalData->AntennaRxPath;
1096

1097
	if (pHalData->rf_chip >= RF_CHIP_MAX) {
1098
		RTW_INFO("This RF chip ID is not supported\n");
1099
		return;
1100
	}
1101

1102
	switch (pAdapter->mppriv.antenna_tx) {
1103
	case ANTENNA_A: { /*/ Actually path S1  (Wi-Fi)*/
1104
		pMptCtx->mpt_rf_path = RF_PATH_A;
1105
		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1106
		phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1107

1108
		for (i = 0; i < 3; ++i) {
1109
			u32 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1110
			u32 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1];
1111

1112
			if (offset != 0) {
1113
				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1114
				RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1115
			}
1116
		}
1117
		for (i = 0; i < 2; ++i) {
1118
			u32 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1119
			u32 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1];
1120

1121
			if (offset != 0) {
1122
				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1123
				RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1124
			}
1125
		}
1126
	}
1127
	break;
1128
	case ANTENNA_B: { /*/ Actually path S0 (BT)*/
1129
		u32 offset;
1130
		u32 data;
1131

1132
		pMptCtx->mpt_rf_path = RF_PATH_B;
1133
		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1134
		phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
1135

1136
		for (i = 0; i < 3; ++i) {
1137
			/*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC  to S1 instead of S0.*/
1138
			offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1139
			data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][1];
1140
			if (pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1141
				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1142
				RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1143
			}
1144
		}
1145
		/*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1146
		for (i = 0; i < 2; ++i) {
1147
			offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1148
			data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][1];
1149
			if (pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1150
				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1151
				RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1152
			}
1153
		}
1154
	}
1155
	break;
1156
	default:
1157
		pMptCtx->mpt_rf_path = RF_PATH_AB;
1158
		break;
1159
	}
1160
}
1161
#endif
1162

1163
#ifdef CONFIG_RTL8703B
1164
void mpt_SetRFPath_8703B(PADAPTER pAdapter)
1165
{
1166
	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
1167
	u32					ulAntennaTx, ulAntennaRx;
1168
	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1169
	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
1170
	struct dm_rf_calibration_struct			*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1171
	u8 i;
1172

1173
	ulAntennaTx = pHalData->antenna_tx_path;
1174
	ulAntennaRx = pHalData->AntennaRxPath;
1175

1176
	if (pHalData->rf_chip >= RF_CHIP_MAX) {
1177
		RTW_INFO("This RF chip ID is not supported\n");
1178
		return;
1179
	}
1180

1181
	switch (pAdapter->mppriv.antenna_tx) {
1182
	case ANTENNA_A: { /* Actually path S1  (Wi-Fi) */
1183
		pMptCtx->mpt_rf_path = RF_PATH_A;
1184
		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1185
		phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1186

1187
		for (i = 0; i < 3; ++i) {
1188
			u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1189
			u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1190

1191
			if (offset != 0) {
1192
				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1193
				RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1194
			}
1195

1196
		}
1197
		for (i = 0; i < 2; ++i) {
1198
			u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1199
			u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1200

1201
			if (offset != 0) {
1202
				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1203
				RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1204
			}
1205
		}
1206
	}
1207
	break;
1208
	case ANTENNA_B: { /* Actually path S0 (BT)*/
1209
		pMptCtx->mpt_rf_path = RF_PATH_B;
1210
		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1211
		phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
1212

1213
		for (i = 0; i < 3; ++i) {
1214
			u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1215
			u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1216

1217
			if (pRFCalibrateInfo->tx_iqc_8703b[i][0] != 0) {
1218
				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1219
				RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1220
			}
1221
		}
1222
		for (i = 0; i < 2; ++i) {
1223
			u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1224
			u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1225

1226
			if (pRFCalibrateInfo->rx_iqc_8703b[i][0] != 0) {
1227
				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1228
				RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1229
			}
1230
		}
1231
	}
1232
	break;
1233
	default:
1234
		pMptCtx->mpt_rf_path = RF_PATH_AB;
1235
		break;
1236
	}
1237

1238
}
1239
#endif
1240

1241
#ifdef CONFIG_RTL8723D
1242
void mpt_SetRFPath_8723D(PADAPTER pAdapter)
1243
{
1244
	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
1245
	u8	p = 0, i = 0;
1246
	u32	ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
1247
	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1248
	struct dm_struct	*pDM_Odm = &pHalData->odmpriv;
1249
	struct dm_rf_calibration_struct	*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1250

1251
	ulAntennaTx = pHalData->antenna_tx_path;
1252
	ulAntennaRx = pHalData->AntennaRxPath;
1253

1254
	if (pHalData->rf_chip >= RF_CHIP_MAX) {
1255
		RTW_INFO("This RF chip ID is not supported\n");
1256
		return;
1257
	}
1258

1259
	switch (pAdapter->mppriv.antenna_tx) {
1260
	/* Actually path S1  (Wi-Fi) */
1261
	case ANTENNA_A: {
1262
		pMptCtx->mpt_rf_path = RF_PATH_A;
1263
		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0);
1264
	}
1265
	break;
1266
	/* Actually path S0 (BT) */
1267
	case ANTENNA_B: {
1268
		pMptCtx->mpt_rf_path = RF_PATH_B;
1269
		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA);
1270

1271
	}
1272
	break;
1273
	default:
1274
		pMptCtx->mpt_rf_path = RF_PATH_AB;
1275
		break;
1276
	}
1277
}
1278
#endif
1279

1280
void mpt_SetRFPath_819X(PADAPTER	pAdapter)
1281
{
1282
	HAL_DATA_TYPE			*pHalData	= GET_HAL_DATA(pAdapter);
1283
	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1284
	u32			ulAntennaTx, ulAntennaRx;
1285
	R_ANTENNA_SELECT_OFDM	*p_ofdm_tx;	/* OFDM Tx register */
1286
	R_ANTENNA_SELECT_CCK	*p_cck_txrx;
1287
	u8		r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
1288
	u8		chgTx = 0, chgRx = 0;
1289
	u32		r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
1290

1291
	ulAntennaTx = pHalData->antenna_tx_path;
1292
	ulAntennaRx = pHalData->AntennaRxPath;
1293

1294
	p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
1295
	p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
1296

1297
	p_ofdm_tx->r_ant_ht1			= 0x1;
1298
	p_ofdm_tx->r_ant_ht2			= 0x2;/*Second TX RF path is A*/
1299
	p_ofdm_tx->r_ant_non_ht			= 0x3;/*/ 0x1+0x2=0x3 */
1300

1301
	switch (ulAntennaTx) {
1302
	case ANTENNA_A:
1303
		p_ofdm_tx->r_tx_antenna		= 0x1;
1304
		r_ofdm_tx_en_val		= 0x1;
1305
		p_ofdm_tx->r_ant_l		= 0x1;
1306
		p_ofdm_tx->r_ant_ht_s1		= 0x1;
1307
		p_ofdm_tx->r_ant_non_ht_s1	= 0x1;
1308
		p_cck_txrx->r_ccktx_enable	= 0x8;
1309
		chgTx = 1;
1310
		/*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
1311
		/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1312
		{
1313
			phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1314
			phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
1315
			r_ofdm_tx_en_val			= 0x3;
1316
			/*/ Power save*/
1317
			/*/cosa r_ant_select_ofdm_val = 0x11111111;*/
1318
			/*/ We need to close RFB by SW control*/
1319
			if (pHalData->rf_type == RF_2T2R) {
1320
				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1321
				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
1322
				phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
1323
				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1324
				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
1325
			}
1326
		}
1327
		pMptCtx->mpt_rf_path = RF_PATH_A;
1328
		break;
1329
	case ANTENNA_B:
1330
		p_ofdm_tx->r_tx_antenna		= 0x2;
1331
		r_ofdm_tx_en_val		= 0x2;
1332
		p_ofdm_tx->r_ant_l		= 0x2;
1333
		p_ofdm_tx->r_ant_ht_s1		= 0x2;
1334
		p_ofdm_tx->r_ant_non_ht_s1	= 0x2;
1335
		p_cck_txrx->r_ccktx_enable	= 0x4;
1336
		chgTx = 1;
1337
		/*/ From SD3 Willis suggestion !!! Set RF A as standby*/
1338
		/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1339
		{
1340
			phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
1341
			phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1342

1343
			/*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
1344
			/*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
1345
			if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
1346
				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
1347
				phy_set_bb_reg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
1348
				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1349
				/*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1350
				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
1351
				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1352
			}
1353
		}
1354
		pMptCtx->mpt_rf_path = RF_PATH_B;
1355
		break;
1356
	case ANTENNA_AB:/*/ For 8192S*/
1357
		p_ofdm_tx->r_tx_antenna		= 0x3;
1358
		r_ofdm_tx_en_val		= 0x3;
1359
		p_ofdm_tx->r_ant_l		= 0x3;
1360
		p_ofdm_tx->r_ant_ht_s1		= 0x3;
1361
		p_ofdm_tx->r_ant_non_ht_s1	= 0x3;
1362
		p_cck_txrx->r_ccktx_enable	= 0xC;
1363
		chgTx = 1;
1364
		/*/ From SD3Willis suggestion !!! Set RF B as standby*/
1365
		/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1366
		{
1367
			phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1368
			phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1369
			/* Disable Power save*/
1370
			/*cosa r_ant_select_ofdm_val = 0x3321333;*/
1371
			/* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
1372
			if (pHalData->rf_type == RF_2T2R) {
1373
				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1374

1375
				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1376
				/*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1377
				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1378
				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1379
			}
1380
		}
1381
		pMptCtx->mpt_rf_path = RF_PATH_AB;
1382
		break;
1383
	default:
1384
		break;
1385
	}
1386
#if 0
1387
	/*  r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
1388
	/*  r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
1389
	/* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D	 */
1390
#endif
1391
	switch (ulAntennaRx) {
1392
	case ANTENNA_A:
1393
		r_rx_antenna_ofdm		= 0x1;	/* A*/
1394
		p_cck_txrx->r_cckrx_enable	= 0x0;	/* default: A*/
1395
		p_cck_txrx->r_cckrx_enable_2	= 0x0;	/* option: A*/
1396
		chgRx = 1;
1397
		break;
1398
	case ANTENNA_B:
1399
		r_rx_antenna_ofdm			= 0x2;	/*/ B*/
1400
		p_cck_txrx->r_cckrx_enable	= 0x1;	/*/ default: B*/
1401
		p_cck_txrx->r_cckrx_enable_2	= 0x1;	/*/ option: B*/
1402
		chgRx = 1;
1403
		break;
1404
	case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/
1405
		r_rx_antenna_ofdm		= 0x3;/*/ AB*/
1406
		p_cck_txrx->r_cckrx_enable	= 0x0;/*/ default:A*/
1407
		p_cck_txrx->r_cckrx_enable_2	= 0x1;/*/ option:B*/
1408
		chgRx = 1;
1409
		break;
1410
	default:
1411
		break;
1412
	}
1413

1414

1415
	if (chgTx && chgRx) {
1416
		switch (pHalData->rf_chip) {
1417
		case RF_8225:
1418
		case RF_8256:
1419
		case RF_6052:
1420
			/*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
1421
			phy_set_bb_reg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val);		/*/OFDM Tx*/
1422
			phy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val);		/*/OFDM Tx*/
1423
			phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);	/*/OFDM Rx*/
1424
			phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);	/*/OFDM Rx*/
1425
			if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1426
				phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm);	/*/OFDM Rx*/
1427
				phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm);	/*/OFDM Rx*/
1428
			}
1429
			phy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
1430
			break;
1431

1432
		default:
1433
			RTW_INFO("Unsupported RFChipID for switching antenna.\n");
1434
			break;
1435
		}
1436
	}
1437
}	/* MPT_ProSetRFPath */
1438

1439
#ifdef CONFIG_RTL8192F
1440

1441
void mpt_set_rfpath_8192f(PADAPTER	pAdapter)
1442
{
1443
	HAL_DATA_TYPE			*pHalData	= GET_HAL_DATA(pAdapter);
1444
	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1445

1446
	u16		ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
1447
	u8				NssforRate, odmNssforRate;
1448
	u32				ulAntennaTx, ulAntennaRx;
1449
	enum bb_path	RxAntToPhyDm;
1450
	enum bb_path	TxAntToPhyDm;
1451

1452
	ulAntennaTx = pHalData->antenna_tx_path;
1453
	ulAntennaRx = pHalData->AntennaRxPath;
1454
	NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
1455

1456
	if (pHalData->rf_chip >= RF_TYPE_MAX)
1457
		RTW_INFO("This RF chip ID is not supported\n");
1458

1459
	switch (ulAntennaTx) {
1460
	case ANTENNA_A:
1461
			pMptCtx->mpt_rf_path = RF_PATH_A;
1462
			TxAntToPhyDm = BB_PATH_A;
1463
			break;
1464
	case ANTENNA_B:
1465
			pMptCtx->mpt_rf_path = RF_PATH_B;
1466
			TxAntToPhyDm = BB_PATH_B;
1467
			break;
1468
	case ANTENNA_AB:
1469
			pMptCtx->mpt_rf_path = RF_PATH_AB;
1470
			TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1471
			break;
1472
	default:
1473
			pMptCtx->mpt_rf_path = RF_PATH_AB;
1474
			TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1475
			break;
1476
	}
1477

1478
	switch (ulAntennaRx) {
1479
	case ANTENNA_A:
1480
			RxAntToPhyDm = BB_PATH_A;
1481
			break;
1482
	case ANTENNA_B:
1483
			RxAntToPhyDm = BB_PATH_B;
1484
			break;
1485
	case ANTENNA_AB:
1486
			RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1487
			break;
1488
	default:
1489
			RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1490
			break;
1491
	}
1492

1493
	phydm_api_trx_mode(GET_PDM_ODM(pAdapter), TxAntToPhyDm, RxAntToPhyDm, TxAntToPhyDm);
1494

1495
}
1496

1497
#endif
1498

1499
void hal_mpt_SetAntenna(PADAPTER	pAdapter)
1500

1501
{
1502
	RTW_INFO("Do %s\n", __func__);
1503
#ifdef CONFIG_RTL8822C
1504
	if (IS_HARDWARE_TYPE_8822C(pAdapter)) {
1505
		rtl8822c_mp_config_rfpath(pAdapter);
1506
		return;
1507
	}
1508
#endif
1509
#ifdef CONFIG_RTL8814A
1510
	if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
1511
		mpt_SetRFPath_8814A(pAdapter);
1512
		return;
1513
	}
1514
#endif
1515
#ifdef CONFIG_RTL8822B
1516
	if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1517
		rtl8822b_mp_config_rfpath(pAdapter);
1518
		return;
1519
	}
1520
#endif
1521
#ifdef CONFIG_RTL8821C
1522
	if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1523
		rtl8821c_mp_config_rfpath(pAdapter);
1524
		return;
1525
	}
1526
#endif
1527
#if	defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1528
	if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1529
		mpt_SetRFPath_8812A(pAdapter);
1530
		return;
1531
	}
1532
#endif
1533
#ifdef CONFIG_RTL8723B
1534
	if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1535
		mpt_SetRFPath_8723B(pAdapter);
1536
		return;
1537
	}
1538
#endif
1539

1540
#ifdef CONFIG_RTL8703B
1541
	if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1542
		mpt_SetRFPath_8703B(pAdapter);
1543
		return;
1544
	}
1545
#endif
1546

1547
#ifdef CONFIG_RTL8723D
1548
	if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1549
		mpt_SetRFPath_8723D(pAdapter);
1550
		return;
1551
	}
1552
#endif
1553

1554
#ifdef CONFIG_RTL8192F
1555
		if (IS_HARDWARE_TYPE_8192F(pAdapter)) {
1556
			mpt_set_rfpath_8192f(pAdapter);
1557
			return;
1558
		}
1559
#endif
1560

1561
#ifdef CONFIG_RTL8814B
1562
	if (IS_HARDWARE_TYPE_8814B(pAdapter)) {
1563
		rtl8814b_mp_config_rfpath(pAdapter);
1564
		return;
1565
	}
1566
#endif
1567

1568
	/*	else if (IS_HARDWARE_TYPE_8821B(pAdapter))
1569
			mpt_SetRFPath_8821B(pAdapter);
1570
		Prepare for 8822B
1571
		else if (IS_HARDWARE_TYPE_8822B(Context))
1572
			mpt_SetRFPath_8822B(Context);
1573
	*/
1574
	mpt_SetRFPath_819X(pAdapter);
1575
	RTW_INFO("mpt_SetRFPath_819X Do %s\n", __func__);
1576
}
1577

1578
s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1579
{
1580
	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1581

1582
	if (!netif_running(pAdapter->pnetdev)) {
1583
		return _FAIL;
1584
	}
1585

1586

1587
	if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
1588
		return _FAIL;
1589
	}
1590

1591

1592
	target_ther &= 0xff;
1593
	if (target_ther < 0x07)
1594
		target_ther = 0x07;
1595
	else if (target_ther > 0x1d)
1596
		target_ther = 0x1d;
1597

1598
	pHalData->eeprom_thermal_meter = target_ther;
1599

1600
	return _SUCCESS;
1601
}
1602

1603

1604
void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
1605
{
1606
	if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
1607
		phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
1608
		phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x0);
1609
		phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
1610
	} else
1611
		phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
1612

1613
}
1614

1615

1616
u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path)
1617

1618
{
1619
	struct dm_struct *p_dm_odm = adapter_to_phydm(pAdapter);
1620

1621
	u32 ThermalValue = 0;
1622
	s32 thermal_value_temp = 0;
1623
	s8 thermal_offset = 0;
1624
	u32 thermal_reg_mask = 0;
1625

1626
	if (IS_8822C_SERIES(GET_HAL_DATA(pAdapter)->version_id))
1627
			thermal_reg_mask = 0x007e; 	/*0x42: RF Reg[6:1], 35332(themal K  & bias k & power trim) & 35325(tssi )*/
1628
	else
1629
			thermal_reg_mask = 0xfc00;	/*0x42: RF Reg[15:10]*/
1630

1631
	ThermalValue = (u8)phy_query_rf_reg(pAdapter, rf_path, 0x42, thermal_reg_mask);
1632

1633
	thermal_offset = phydm_get_thermal_offset(p_dm_odm);
1634

1635
	thermal_value_temp = ThermalValue + thermal_offset;
1636

1637
	if (thermal_value_temp > 63)
1638
		ThermalValue = 63;
1639
	else if (thermal_value_temp < 0)
1640
		ThermalValue = 0;
1641
	else
1642
		ThermalValue = thermal_value_temp;
1643

1644
	return (u8)ThermalValue;
1645
}
1646

1647

1648
void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value)
1649
{
1650
#if 0
1651
	fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
1652
	rtw_msleep_os(1000);
1653
	fw_cmd_data(pAdapter, value, 1);
1654
	*value &= 0xFF;
1655
#else
1656
	hal_mpt_TriggerRFThermalMeter(pAdapter);
1657
	rtw_msleep_os(1000);
1658
	*value = hal_mpt_ReadRFThermalMeter(pAdapter, rfpath);
1659
#endif
1660

1661
}
1662

1663

1664
void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1665
{
1666
	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1667

1668
	pAdapter->mppriv.mpt_ctx.bSingleCarrier = bStart;
1669

1670
	if (bStart) {/*/ Start Single Carrier.*/
1671
		/*/ Start Single Carrier.*/
1672
		/*/ 1. if OFDM block on?*/
1673
		if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1674
			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
1675

1676
		/*/ 2. set CCK test mode off, set to CCK normal mode*/
1677
		phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1678

1679
		/*/ 3. turn on scramble setting*/
1680
		phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
1681

1682
		/*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1683
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1684
		if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
1685
			phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
1686
		else
1687
#endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1688
			phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);
1689

1690
	} else {
1691
		/*/ Stop Single Carrier.*/
1692
		/*/ Stop Single Carrier.*/
1693
		/*/ Turn off all test modes.*/
1694
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1695
		if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
1696
			phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1697
		else
1698
#endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1699
			phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1700

1701
		rtw_msleep_os(10);
1702
		/*/BB Reset*/
1703
		phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1704
		phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1705
	}
1706
}
1707

1708

1709
void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1710
{
1711
	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
1712
	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1713
	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
1714
	u32			ulAntennaTx = pHalData->antenna_tx_path;
1715
	static u32		regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
1716
	u8 rfPath;
1717

1718
	if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
1719
#ifdef	PHYDM_MP_SUPPORT
1720
		phydm_mp_set_single_tone(pDM_Odm, bStart, pMptCtx->mpt_rf_path);
1721
#endif
1722
		return;
1723
	}
1724

1725
	switch (ulAntennaTx) {
1726
	case ANTENNA_B:
1727
		rfPath = RF_PATH_B;
1728
		break;
1729
	case ANTENNA_C:
1730
		rfPath = RF_PATH_C;
1731
		break;
1732
	case ANTENNA_D:
1733
		rfPath = RF_PATH_D;
1734
		break;
1735
	case ANTENNA_A:
1736
	default:
1737
		rfPath = RF_PATH_A;
1738
		break;
1739
	}
1740

1741
	pAdapter->mppriv.mpt_ctx.is_single_tone = bStart;
1742
	if (bStart) {
1743
		/*/ Start Single Tone.*/
1744
		/*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
1745
		if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1746
			regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask);
1747
			phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1748
			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
1749
			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
1750
		} else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1751
			/*/Set MAC REG 88C: Prevent SingleTone Fail*/
1752
			phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1753
			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/
1754
			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1755
		}	else if (IS_HARDWARE_TYPE_8192F(pAdapter)) { /* USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1756
 #ifdef CONFIG_RTL8192F
1757
			phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x1);
1758
			phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x1);
1759
			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x1);
1760
			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x1);
1761
			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x1);
1762
			phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x1);
1763
			phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1764
			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x1); /* RF LO disabled*/
1765
			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /* Tx mode*/
1766
#endif
1767
		} else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1768
			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1769
				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1770
				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
1771
			} else {
1772
				/*/ S0/S1 both use PATH A to configure*/
1773
				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1774
				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
1775
			}
1776
		} else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1777
			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1778
				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
1779
				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
1780
			}
1781
		} else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
1782
			/*Set BB REG 88C: Prevent SingleTone Fail*/
1783
			phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
1784
			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1);
1785
			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2);
1786

1787
		} else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1788
			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1789
				phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1790
				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1791
				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x1);
1792
			} else {/* S0/S1 both use PATH A to configure */
1793
				phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1794
				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1795
				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x1);
1796
			}
1797
		} else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
1798
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1799
			u8 p = RF_PATH_A;
1800

1801
			regRF = phy_query_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
1802
			regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
1803
			regBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
1804
			regBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1805
			regBB3 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1806

1807
			phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/
1808

1809
			if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
1810
				for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
1811
					phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1812
					phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1813
					phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1814
				}
1815
			} else {
1816
				phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1817
				phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1818
#ifdef CONFIG_RTL8821C
1819
				if (IS_HARDWARE_TYPE_8821C(pAdapter) && pDM_Odm->current_rf_set_8821c == SWITCH_TO_BTG)
1820
					phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x75, BIT16, 0x1); /* RF LO (for BTG) enabled */
1821
				else
1822
#endif
1823
					phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1824
			}
1825
			if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1826
					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777);  /* 0xCB0=0x77777777*/
1827
					phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777);  /* 0xEB0=0x77777777*/
1828
					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777);  /* 0xCB4[15:0] = 0x7777*/
1829
					phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777);  /* 0xEB4[15:0] = 0x7777*/
1830
					phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xFFF, 0xb); /* 0xCBC[23:16] = 0x12*/
1831
					phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xFFF, 0x830); /* 0xEBC[23:16] = 0x12*/
1832
			} else if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1833
				phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xF0F0, 0x707);  /* 0xCB0[[15:12, 7:4] = 0x707*/
1834

1835
				if (pHalData->external_pa_5g)
1836
				{
1837
					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
1838
				}
1839
				else if (pHalData->ExternalPA_2G)
1840
				{
1841
					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
1842
				}
1843
			} else {
1844
				phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1845
				phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1846

1847
				if (pHalData->external_pa_5g) {
1848
					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
1849
					phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
1850
				} else if (pHalData->ExternalPA_2G) {
1851
					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
1852
					phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
1853
				}
1854
			}
1855
#endif
1856
		}
1857
#if defined(CONFIG_RTL8814A)
1858
				else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1859
						mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
1860
#endif
1861
		else	/*/ Turn On SingleTone and turn off the other test modes.*/
1862
			phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
1863

1864
		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1865
		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1866

1867
	} else {/*/ Stop Single Ton e.*/
1868

1869
		if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1870
			phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF);
1871
			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1872
			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1873
		} else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1874
			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
1875
			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */
1876
			/*/ RESTORE MAC REG 88C: Enable RF Functions*/
1877
			phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0);
1878
		} else if (IS_HARDWARE_TYPE_8192F(pAdapter)){
1879
#ifdef CONFIG_RTL8192F
1880
			phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x0);
1881
			phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x0);
1882
			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x0);
1883
			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x0);
1884
			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x0);
1885
			phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x0);
1886
			phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0x0);
1887
			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x0); /* RF LO disabled*/
1888
			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /* Rx mode*/
1889
#endif
1890
		} else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1891
			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1892
				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1893
				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
1894
			} else {
1895
				/*/ S0/S1 both use PATH A to configure*/
1896
				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1897
				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
1898
			}
1899
		} else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1900
			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1901
				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
1902
				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
1903
			}
1904
		} else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
1905
			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/
1906
			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/
1907
			/*Set BB REG 88C: Prevent SingleTone Fail*/
1908
			phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
1909
		} else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1910
			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1911
				phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1912
				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
1913
				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x0);
1914
			} else {	/* S0/S1 both use PATH A to configure */
1915
				phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1916
				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
1917
				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x0);
1918
			}
1919
		} else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
1920
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1921
			u8 p = RF_PATH_A;
1922

1923
			phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
1924

1925
			if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
1926
				for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
1927
					phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1928
					phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1929
				}
1930
			} else {
1931
				p = pMptCtx->mpt_rf_path;
1932
				phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1933

1934
				if (IS_HARDWARE_TYPE_8821C(pAdapter))
1935
					phy_set_rf_reg(pAdapter, p, 0x75, BIT16, 0x0); /* RF LO (for BTG) disabled */
1936

1937
				phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1938
			}
1939

1940
			phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
1941
			phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
1942
			phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);
1943
			phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);
1944

1945
			if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1946
				RTW_INFO("Restore RFE control Pin cbc\n");
1947
				phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xfff, 0x0);
1948
				phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xfff, 0x0);
1949
			}
1950
#endif
1951
		}
1952
#if defined(CONFIG_RTL8814A)
1953
		else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1954
			mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
1955

1956
		else/*/ Turn off all test modes.*/
1957
			phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1958
#endif
1959
		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1960
		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1961

1962
	}
1963
}
1964

1965
void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
1966
{
1967
	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
1968
	struct dm_struct		*pdm_odm = &pHalData->odmpriv;
1969
	u8 Rate;
1970

1971
	pAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart;
1972

1973
	if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
1974
#ifdef PHYDM_MP_SUPPORT
1975
		phydm_mp_set_carrier_supp(pdm_odm, bStart, pAdapter->mppriv.rateidx);
1976
#endif
1977
		return;
1978
	}
1979

1980
	Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
1981
	if (bStart) {/* Start Carrier Suppression.*/
1982
		if (Rate <= MPT_RATE_11M) {
1983
			/*/ 1. if CCK block on?*/
1984
			if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
1985
				write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
1986

1987
			/*/Turn Off All Test Mode*/
1988
			if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
1989
				phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
1990
			else
1991
				phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1992

1993
			write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);    /*/transmit mode*/
1994
			write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0);  /*/turn off scramble setting*/
1995

1996
			/*/Set CCK Tx Test Rate*/
1997
			write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);    /*/Set FTxRate to 1Mbps*/
1998
		}
1999

2000
		/*Set for dynamic set Power index*/
2001
		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2002
		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2003

2004
	} else {/* Stop Carrier Suppression.*/
2005

2006
		if (Rate <= MPT_RATE_11M) {
2007
			write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);    /*normal mode*/
2008
			write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1);  /*turn on scramble setting*/
2009

2010
			/*BB Reset*/
2011
			write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2012
			write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2013
		}
2014
		/*Stop for dynamic set Power index*/
2015
		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2016
		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2017
	}
2018
	RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n");
2019
}
2020

2021
u32 hal_mpt_query_phytxok(PADAPTER	pAdapter)
2022
{
2023
	PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2024
	RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
2025
	HAL_DATA_TYPE			*pHalData	= GET_HAL_DATA(pAdapter);
2026
	u16 count = 0;
2027

2028
#ifdef PHYDM_MP_SUPPORT
2029
	struct dm_struct *dm = (struct dm_struct *)&pHalData->odmpriv;
2030
	struct phydm_mp *mp = &dm->dm_mp_table;
2031

2032
	if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
2033
		phydm_mp_get_tx_ok(&pHalData->odmpriv, pAdapter->mppriv.rateidx);
2034
		count = mp->tx_phy_ok_cnt;
2035

2036
	} else
2037
#endif
2038
	{
2039

2040
	if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2041
		count = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
2042
	else
2043
		count = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
2044
	}
2045

2046
	if (count > 50000) {
2047
		rtw_reset_phy_trx_ok_counters(pAdapter);
2048
		pAdapter->mppriv.tx.sended += count;
2049
		count = 0;
2050
	}
2051

2052
	return pAdapter->mppriv.tx.sended + count;
2053

2054
}
2055

2056
static	void mpt_StopCckContTx(
2057
	PADAPTER	pAdapter
2058
)
2059
{
2060
	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
2061
	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2062
	u8			u1bReg;
2063

2064
	pMptCtx->bCckContTx = FALSE;
2065
	pMptCtx->bOfdmContTx = FALSE;
2066

2067
	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);	/*normal mode*/
2068
	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1);	/*turn on scramble setting*/
2069

2070
	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2071
		phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0);			/* 0xa15[1:0] = 2b00*/
2072
		phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);		/* 0xc08[16] = 0*/
2073

2074
		phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
2075
		phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0);
2076
		phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0);
2077
	}
2078

2079
	/*BB Reset*/
2080
	phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2081
	phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2082

2083
	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2084
	phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2085
	phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2086
	}
2087

2088
	if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) || 
2089
		IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || 
2090
		IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) || 
2091
		IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2092
		phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);/* patch Count CCK adjust Rate*/
2093
	}
2094

2095
}	/* mpt_StopCckContTx */
2096

2097

2098
static	void mpt_StopOfdmContTx(
2099
	PADAPTER	pAdapter
2100
)
2101
{
2102
	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
2103
	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2104
	u8			u1bReg;
2105
	u32			data;
2106

2107
	pMptCtx->bCckContTx = FALSE;
2108
	pMptCtx->bOfdmContTx = FALSE;
2109

2110
	if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2111
		phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2112
	else
2113
		phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2114

2115
	rtw_mdelay_os(10);
2116

2117
	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)){
2118
		phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0);			/* 0xa15[1:0] = 0*/
2119
		phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);		/* 0xc08[16] = 0*/
2120
	}
2121

2122
	/*BB Reset*/
2123
	phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2124
	phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2125

2126
	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2127
	phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2128
	phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2129
	}
2130
}	/* mpt_StopOfdmContTx */
2131

2132

2133
static	void mpt_StartCckContTx(
2134
	PADAPTER		pAdapter
2135
)
2136
{
2137
	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
2138
	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2139
	u32			cckrate;
2140

2141
	/* 1. if CCK block on */
2142
	if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn))
2143
		phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
2144

2145
	/*Turn Off All Test Mode*/
2146
	if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2147
		phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2148
	else
2149
		phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2150

2151
	cckrate  = pAdapter->mppriv.rateidx;
2152

2153
	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
2154

2155
	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);	/*transmit mode*/
2156
	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1);	/*turn on scramble setting*/
2157

2158
	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2159
		phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3);			/* 0xa15[1:0] = 11 force cck rxiq = 0*/
2160
		phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1);		/* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
2161
		phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
2162
		phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1);
2163
		phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1);
2164
	}
2165

2166
	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2167
		phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2168
		phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2169
	}
2170

2171
	if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) || 
2172
		IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || 
2173
		IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) || 
2174
		IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2175
		if (pAdapter->mppriv.rateidx == MPT_RATE_1M) /* patch Count CCK adjust Rate*/
2176
			phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);
2177
		else
2178
			phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bEnable);
2179
	}
2180

2181
	pMptCtx->bCckContTx = TRUE;
2182
	pMptCtx->bOfdmContTx = FALSE;
2183

2184
}	/* mpt_StartCckContTx */
2185

2186

2187
static	void mpt_StartOfdmContTx(
2188
	PADAPTER		pAdapter
2189
)
2190
{
2191
	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
2192
	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2193

2194
	/* 1. if OFDM block on?*/
2195
	if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
2196
		phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
2197

2198
	/* 2. set CCK test mode off, set to CCK normal mode*/
2199
	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
2200

2201
	/* 3. turn on scramble setting*/
2202
	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
2203

2204
	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2205
		phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3);			/* 0xa15[1:0] = 2b'11*/
2206
		phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1);		/* 0xc08[16] = 1*/
2207
	}
2208

2209
	/* 4. Turn On Continue Tx and turn off the other test modes.*/
2210
	if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2211
		phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
2212
	else
2213
		phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
2214

2215
	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2216
	phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2217
	phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2218
	}
2219

2220
	pMptCtx->bCckContTx = FALSE;
2221
	pMptCtx->bOfdmContTx = TRUE;
2222
}	/* mpt_StartOfdmContTx */
2223

2224
#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)  || defined(CONFIG_RTL8822C)
2225
#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
2226
static void mpt_convert_phydm_txinfo_for_jaguar3(
2227
	RT_PMAC_TX_INFO	pMacTxInfo, struct phydm_pmac_info *phydmtxinfo)
2228
{
2229
	phydmtxinfo->en_pmac_tx = pMacTxInfo.bEnPMacTx;
2230
	phydmtxinfo->mode = pMacTxInfo.Mode;
2231
	phydmtxinfo->tx_rate = MRateToHwRate(mpt_to_mgnt_rate(pMacTxInfo.TX_RATE));
2232
	phydmtxinfo->tx_sc = pMacTxInfo.TX_SC;
2233
	phydmtxinfo->is_short_preamble = pMacTxInfo.bSPreamble;
2234
	phydmtxinfo->ndp_sound = pMacTxInfo.NDP_sound;
2235
	phydmtxinfo->bw = pMacTxInfo.BandWidth;
2236
	phydmtxinfo->m_stbc = pMacTxInfo.m_STBC;
2237
	phydmtxinfo->packet_period = pMacTxInfo.PacketPeriod;
2238
	phydmtxinfo->packet_count = pMacTxInfo.PacketCount;
2239
	phydmtxinfo->packet_pattern = pMacTxInfo.PacketPattern;
2240
	phydmtxinfo->sfd = pMacTxInfo.SFD;
2241
	phydmtxinfo->signal_field = pMacTxInfo.SignalField;
2242
	phydmtxinfo->service_field = pMacTxInfo.ServiceField;
2243
	phydmtxinfo->length = pMacTxInfo.LENGTH;
2244
	_rtw_memcpy(&phydmtxinfo->crc16,pMacTxInfo.CRC16, 2);
2245
	_rtw_memcpy(&phydmtxinfo->lsig , pMacTxInfo.LSIG,3);
2246
	_rtw_memcpy(&phydmtxinfo->ht_sig , pMacTxInfo.HT_SIG,6);
2247
	_rtw_memcpy(&phydmtxinfo->vht_sig_a , pMacTxInfo.VHT_SIG_A,6);
2248
	_rtw_memcpy(&phydmtxinfo->vht_sig_b , pMacTxInfo.VHT_SIG_B,4);
2249
	phydmtxinfo->vht_sig_b_crc = pMacTxInfo.VHT_SIG_B_CRC;
2250
	_rtw_memcpy(&phydmtxinfo->vht_delimiter,pMacTxInfo.VHT_Delimiter,4);
2251
}
2252
#endif
2253

2254
/* for HW TX mode */
2255
void mpt_ProSetPMacTx(PADAPTER	Adapter)
2256
{
2257
	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
2258
	PMPT_CONTEXT	pMptCtx		=	&(Adapter->mppriv.mpt_ctx);
2259
	struct mp_priv *pmppriv = &Adapter->mppriv;
2260
	RT_PMAC_TX_INFO	PMacTxInfo	=	pMptCtx->PMacTxInfo;
2261
	u32			u4bTmp;
2262
	struct dm_struct *p_dm_odm;
2263

2264
	p_dm_odm = &pHalData->odmpriv;
2265

2266
#if 0
2267
	PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
2268
	PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);
2269
	PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);
2270
	PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);
2271
	dbg_print("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
2272
	PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
2273

2274
	PRINT_DATA("Src Address", Adapter->mac_addr, ETH_ALEN);
2275
	PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, ETH_ALEN);
2276
#endif
2277
	if (pmppriv->pktInterval != 0)
2278
		PMacTxInfo.PacketPeriod = pmppriv->pktInterval;
2279

2280
    	if (pmppriv->tx.count != 0)
2281
        	PMacTxInfo.PacketCount = pmppriv->tx.count;
2282

2283
	RTW_INFO("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
2284
	RTW_INFO("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
2285
		 PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
2286

2287
	if (IS_HARDWARE_TYPE_JAGUAR3(Adapter)) {
2288
#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
2289
		struct phydm_pmac_info phydm_mactxinfo;
2290

2291
		mpt_convert_phydm_txinfo_for_jaguar3(PMacTxInfo, &phydm_mactxinfo);
2292
		phydm_set_pmac_tx(p_dm_odm, &phydm_mactxinfo, pMptCtx->mpt_rf_path);
2293
#endif
2294
		return;
2295
	}
2296

2297
	if (PMacTxInfo.bEnPMacTx == FALSE) {
2298
		if (pMptCtx->HWTxmode == CONTINUOUS_TX) {
2299
			phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);			/*	TX Stop*/
2300
			if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
2301
				mpt_StopCckContTx(Adapter);
2302
			else
2303
				mpt_StopOfdmContTx(Adapter);
2304
		} else if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index)) {
2305
			u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord);
2306
			phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
2307
			phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);		/*TX Stop*/
2308
		} else
2309
			phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);		/*	TX Stop*/
2310

2311
		if (pMptCtx->HWTxmode == OFDM_Single_Tone_TX) {
2312
			/* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
2313
			if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
2314
				mpt_StopCckContTx(Adapter);
2315
			else
2316
				mpt_StopOfdmContTx(Adapter);
2317

2318
			mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);
2319
		}
2320
		pMptCtx->HWTxmode = TEST_NONE;
2321
		return;
2322
	}
2323

2324
    	pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
2325

2326
	if (PMacTxInfo.Mode == CONTINUOUS_TX) {
2327
		pMptCtx->HWTxmode = CONTINUOUS_TX;
2328
		PMacTxInfo.PacketCount = 1;
2329

2330
        	hal_mpt_SetTxPower(Adapter);
2331

2332
		if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2333
			mpt_StartCckContTx(Adapter);
2334
		else
2335
			mpt_StartOfdmContTx(Adapter);
2336
	} else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2337
		/* Continuous TX -> HW TX -> RF Setting */
2338
		pMptCtx->HWTxmode = OFDM_Single_Tone_TX;
2339
		PMacTxInfo.PacketCount = 1;
2340

2341
		if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2342
			mpt_StartCckContTx(Adapter);
2343
		else
2344
			mpt_StartOfdmContTx(Adapter);
2345
	} else if (PMacTxInfo.Mode == PACKETS_TX) {
2346
		pMptCtx->HWTxmode = PACKETS_TX;
2347
		if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
2348
			PMacTxInfo.PacketCount = 0xffff;
2349
	}
2350

2351
	if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2352
		/* 0xb1c[0:15] TX packet count 0xb1C[31:16]	SFD*/
2353
		u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16);
2354
		phy_set_bb_reg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
2355
		/* 0xb40 7:0 SIGNAL	15:8 SERVICE	31:16 LENGTH*/
2356
		u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16);
2357
		phy_set_bb_reg(Adapter, 0xb40, bMaskDWord, u4bTmp);
2358
		u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);
2359
		phy_set_bb_reg(Adapter, 0xb44, bMaskLWord, u4bTmp);
2360

2361
		if (PMacTxInfo.bSPreamble)
2362
			phy_set_bb_reg(Adapter, 0xb0c, BIT27, 0);
2363
		else
2364
			phy_set_bb_reg(Adapter, 0xb0c, BIT27, 1);
2365
	} else {
2366
		phy_set_bb_reg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
2367

2368
		u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24);
2369
		phy_set_bb_reg(Adapter, 0xb08, bMaskDWord, u4bTmp);	/*	Set 0xb08[23:0] = LSIG, 0xb08[31:24] =  Data init octet*/
2370

2371
		if (PMacTxInfo.PacketPattern == 0x12)
2372
			u4bTmp = 0x3000000;
2373
		else
2374
			u4bTmp = 0;
2375
	}
2376

2377
	if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {
2378
		u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16);
2379
		phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2380
		u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16);
2381
		phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2382
	} else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2383
		u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16);
2384
		phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2385
		u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16);
2386
		phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2387

2388
		_rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);
2389
		phy_set_bb_reg(Adapter, 0xb14, bMaskDWord, u4bTmp);
2390
	}
2391

2392
	if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2393
		u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod;	/* for TX interval */
2394
		phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, u4bTmp);
2395

2396
		_rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);
2397
		phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, u4bTmp);
2398

2399
		/* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/
2400
		/*& Duration & Frame control*/
2401
		phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, 0x00000040);
2402

2403
		/* Address1 [0:3]*/
2404
		u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2405
		phy_set_bb_reg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
2406

2407
		/* Address3 [3:0]*/
2408
		phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2409

2410
		/* Address2[0:1] & Address1 [5:4]*/
2411
		u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2412
		phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2413

2414
		/* Address2 [5:2]*/
2415
		u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2416
		phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2417

2418
		/* Sequence Control & Address3 [5:4]*/
2419
		/*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/
2420
		/*phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
2421
	} else {
2422
		phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod);	/* for TX interval*/
2423
		/* & Duration & Frame control */
2424
		phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, 0x00000040);
2425

2426
		/* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/
2427
		/* Address1 [0:3]*/
2428
		u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2429
		phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, u4bTmp);
2430

2431
		/* Address3 [3:0]*/
2432
		phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2433

2434
		/* Address2[0:1] & Address1 [5:4]*/
2435
		u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2436
		phy_set_bb_reg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
2437

2438
		/* Address2 [5:2] */
2439
		u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2440
		phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2441

2442
		/* Sequence Control & Address3 [5:4]*/
2443
		u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);
2444
		phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2445
	}
2446

2447
	phy_set_bb_reg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
2448

2449
	/* 0xb4c 3:0 TXSC	5:4	BW	7:6 m_STBC	8 NDP_Sound*/
2450
	u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8);
2451
	phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp);
2452

2453
	if (IS_HARDWARE_TYPE_JAGUAR2(Adapter)) {
2454
		u32 offset = 0xb44;
2455

2456
		if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2457
			phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2458
		else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2459
			phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2460
		else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2461
			phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2462

2463
	} else if(IS_HARDWARE_TYPE_JAGUAR(Adapter)) {
2464
		u32 offset = 0xb4c;
2465

2466
		if(IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2467
			phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2468
		else if(IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2469
			phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2470
		else if(IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2471
			phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2472
	}
2473

2474
	phy_set_bb_reg(Adapter, 0xb00, BIT8, 1);		/*	Turn on PMAC*/
2475
	/* phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);				 */ /* TX Stop */
2476
	if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2477
		phy_set_bb_reg(Adapter, 0xb04, 0xf, 8);		/*TX CCK ON*/
2478
		phy_set_bb_reg(Adapter, 0xA84, BIT31, 0);
2479
	} else
2480
		phy_set_bb_reg(Adapter, 0xb04, 0xf, 4);		/*	TX Ofdm ON	*/
2481

2482
	if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)
2483
		mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);
2484

2485
}
2486

2487
#endif
2488

2489
void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
2490
{
2491
	u8 Rate;
2492

2493
	RTW_INFO("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx);
2494
	Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
2495
	pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart;
2496

2497
	if (Rate <= MPT_RATE_11M) {
2498
		if (bStart)
2499
			mpt_StartCckContTx(pAdapter);
2500
		else
2501
			mpt_StopCckContTx(pAdapter);
2502

2503
	} else if (Rate >= MPT_RATE_6M) {
2504
		if (bStart)
2505
			mpt_StartOfdmContTx(pAdapter);
2506
		else
2507
			mpt_StopOfdmContTx(pAdapter);
2508
	}
2509
}
2510

2511
#endif /* CONFIG_MP_INCLUDE*/
2512

2513
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