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nu11secur1ty
GitHub Repository: nu11secur1ty/Kali-Linux
Path: blob/master/ALFA-W1F1/RTL8814AU/hal/phydm/halrf/rtl8814a/halrf_8814a_ce.c
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#include "mp_precomp.h"
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#include "../../phydm_precomp.h"
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#if (RTL8814A_SUPPORT == 1)
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/*---------------------------Define Local Constant---------------------------*/
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/* 2010/04/25 MH Define the max tx power tracking tx agc power. */
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#define ODM_TXPWRTRACK_MAX_IDX_8814A 6
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25
/*---------------------------Define Local Constant---------------------------*/
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27
/*3============================================================*/
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/* 3 Tx Power Tracking
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*3============================================================*/
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#define REG_A_TX_AGC 0xC94
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#define REG_B_TX_AGC 0xE94
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#define REG_C_TX_AGC 0x1894
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#define REG_D_TX_AGC 0x1A94
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#define TXAGC_BITMASK (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25))
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#define REG_A_BBSWING 0xC1C
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#define REG_B_BBSWING 0xE1C
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#define REG_C_BBSWING 0x181C
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#define REG_D_BBSWING 0x1A1C
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#define BBSWING_BITMASK 0xFFE00000
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#if 0
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u8 check_rf_gain_offset(
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struct dm_struct *dm,
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enum pwrtrack_method method,
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u8 rf_path
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)
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{
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s8 upper_bound = 10, lower_bound = -5; /*4'b1010 = 10*/
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s8 final_rf_index = 0;
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boolean is_positive = false;
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u32 bit_mask = 0;
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u8 final_ofdm_swing_index = 0, tx_scaling_upper_bound = 28, tx_scaling_lower_bound = 4; /*upper bound +2dB, lower bound -10dB*/
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struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
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if (method == MIX_MODE) { /*normal Tx power tracking*/
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "is 8814 MP chip\n");
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bit_mask = BIT(19);
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cali_info->absolute_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path] + cali_info->kfree_offset[rf_path];
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if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0) /*check if RF_Index is positive or not*/
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is_positive = true;
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else
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is_positive = false;
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odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, bit_mask, is_positive);
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bit_mask = BIT(18) | BIT(17) | BIT(16) | BIT(15);
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final_rf_index = cali_info->absolute_ofdm_swing_idx[rf_path] / 2; /*TxBB 1 step equal 1dB, BB swing 1step equal 0.5dB*/
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}
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if (final_rf_index > upper_bound) { /*Upper bound = 10dB, if more htan upper bound, then move to bb swing max = +2dB*/
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odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, bit_mask, upper_bound); /*set RF Reg0x55 per path*/
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final_ofdm_swing_index = cali_info->default_ofdm_index + (cali_info->absolute_ofdm_swing_idx[rf_path] - (upper_bound << 1));
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if (final_ofdm_swing_index > tx_scaling_upper_bound) /*bb swing upper bound = +2dB*/
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final_ofdm_swing_index = tx_scaling_upper_bound;
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"******path-%d Compensate with TXBB = %d\n", rf_path,
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upper_bound);
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return final_ofdm_swing_index;
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} else if (final_rf_index < lower_bound) { /*lower bound = -5dB*/
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odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, bit_mask, (-1) * (lower_bound)); /*set RF Reg0x55 per path*/
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final_ofdm_swing_index = cali_info->default_ofdm_index - ((lower_bound << 1) - cali_info->absolute_ofdm_swing_idx[rf_path]);
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if (final_ofdm_swing_index < tx_scaling_lower_bound) /*bb swing lower bound = -10dB*/
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final_ofdm_swing_index = tx_scaling_lower_bound;
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return final_ofdm_swing_index;
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} else { /*normal case*/
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if (is_positive == true)
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odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, bit_mask, final_rf_index); /*set RF Reg0x55 per path*/
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else
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odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, bit_mask, (-1) * final_rf_index); /*set RF Reg0x55 per path*/
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final_ofdm_swing_index = cali_info->default_ofdm_index + (cali_info->absolute_ofdm_swing_idx[rf_path]) % 2;
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return final_ofdm_swing_index;
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}
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return false;
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}
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#endif
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u8 get_tssivalue(struct dm_struct *dm, enum pwrtrack_method method, u8 rf_path)
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{
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struct _ADAPTER *adapter = dm->adapter;
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struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
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struct _hal_rf_ *rf = &(dm->rf_table);
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HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
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s8 power_by_rate_value = 0;
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u8 tx_num, tssi_value = 0;
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u8 channel = *dm->channel;
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u8 band_width = hal_data->current_channel_bw;
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u8 tx_rate = 0xFF;
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u8 tx_limit = 0;
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u8 reg_pwr_tbl_sel = 0;
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#ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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PMGNT_INFO mgnt_info = &(adapter->MgntInfo);
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reg_pwr_tbl_sel = mgnt_info->reg_pwr_tbl_sel;
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#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
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reg_pwr_tbl_sel = adapter->registrypriv.reg_pwr_tbl_sel;
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#endif
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#endif
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if (*dm->mp_mode == true) {
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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#if (MP_DRIVER == 1)
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PMPT_CONTEXT p_mpt_ctx = &(adapter->mpt_ctx);
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tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
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#endif
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#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
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#ifdef CONFIG_MP_INCLUDED
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PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
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tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
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#endif
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#endif
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#endif
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} else {
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u16 rate = *(dm->forced_data_rate);
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if (!rate) { /*auto rate*/
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
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#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
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if (dm->number_linked_client != 0)
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tx_rate = hw_rate_to_m_rate(dm->tx_rate);
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else
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tx_rate = rf->p_rate_index;
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#endif
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} else /*force rate*/
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tx_rate = (u8)rate;
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}
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__,
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tx_rate);
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tx_num = mgnt_query_nss_tx_rate(tx_rate);
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if (channel >= 1 && channel <= 14) {
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power_by_rate_value = phy_get_tx_power_by_rate_original(adapter, BAND_ON_2_4G, (enum rf_path)rf_path, tx_num, tx_rate);
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tx_limit = phy_get_tx_power_limit_original(adapter, reg_pwr_tbl_sel, BAND_ON_2_4G, band_width, RF_PATH_A, tx_rate, channel);
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"Call:%s power_by_rate_value=%d tx_rate=0x%X rf_path=%d tx_num=%d\n",
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__func__, power_by_rate_value, tx_rate, rf_path, tx_num);
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"Call:%s tx_limit=%d reg_pwr_tbl_sel=0x%X band_width=%d channel=%d\n",
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__func__, tx_limit, reg_pwr_tbl_sel, band_width,
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channel);
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power_by_rate_value = power_by_rate_value > tx_limit ? tx_limit : power_by_rate_value;
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if (IS_CCK_RATE(tx_rate)) {
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switch (rf_path) {
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case RF_PATH_A:
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tssi_value = cali_info->delta_swing_tssi_table_2g_cck_a[power_by_rate_value];
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break;
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case RF_PATH_B:
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tssi_value = cali_info->delta_swing_tssi_table_2g_cck_b[power_by_rate_value];
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break;
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case RF_PATH_C:
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tssi_value = cali_info->delta_swing_tssi_table_2g_cck_c[power_by_rate_value];
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break;
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case RF_PATH_D:
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tssi_value = cali_info->delta_swing_tssi_table_2g_cck_d[power_by_rate_value];
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break;
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default:
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"Call:%s Wrong path name!!!\n",
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__func__);
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break;
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}
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} else {
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switch (rf_path) {
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case RF_PATH_A:
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tssi_value = cali_info->delta_swing_tssi_table_2ga[power_by_rate_value];
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break;
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case RF_PATH_B:
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tssi_value = cali_info->delta_swing_tssi_table_2gb[power_by_rate_value];
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break;
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case RF_PATH_C:
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tssi_value = cali_info->delta_swing_tssi_table_2gc[power_by_rate_value];
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break;
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case RF_PATH_D:
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tssi_value = cali_info->delta_swing_tssi_table_2gd[power_by_rate_value];
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break;
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default:
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"Call:%s Wrong path name!!!!\n",
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__func__);
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break;
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}
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}
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} else if (channel >= 36 && channel <= 64) {
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power_by_rate_value = phy_get_tx_power_by_rate_original(adapter, BAND_ON_5G, (enum rf_path)rf_path, tx_num, tx_rate);
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tx_limit = phy_get_tx_power_limit_original(adapter, reg_pwr_tbl_sel, BAND_ON_5G, band_width, RF_PATH_A, tx_rate, channel);
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"Call:%s power_by_rate_value=%d tx_rate=0x%X rf_path=%d tx_num=%d\n",
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__func__, power_by_rate_value, tx_rate, rf_path, tx_num);
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"Call:%s tx_limit=%d reg_pwr_tbl_sel=0x%X band_width=%d channel=%d\n",
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__func__, tx_limit, reg_pwr_tbl_sel, band_width,
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channel);
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power_by_rate_value = power_by_rate_value > tx_limit ? tx_limit : power_by_rate_value;
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switch (rf_path) {
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case RF_PATH_A:
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tssi_value = cali_info->delta_swing_tssi_table_5ga[0][power_by_rate_value];
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break;
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case RF_PATH_B:
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tssi_value = cali_info->delta_swing_tssi_table_5gb[0][power_by_rate_value];
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break;
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case RF_PATH_C:
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tssi_value = cali_info->delta_swing_tssi_table_5gc[0][power_by_rate_value];
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break;
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case RF_PATH_D:
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tssi_value = cali_info->delta_swing_tssi_table_5gd[0][power_by_rate_value];
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break;
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default:
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"Call:%s Wrong path name!!!!\n", __func__);
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break;
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}
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} else if (channel >= 100 && channel <= 144) {
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power_by_rate_value = phy_get_tx_power_by_rate_original(adapter, BAND_ON_5G, (enum rf_path)rf_path, tx_num, tx_rate);
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tx_limit = phy_get_tx_power_limit_original(adapter, reg_pwr_tbl_sel, BAND_ON_5G, band_width, RF_PATH_A, tx_rate, channel);
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"Call:%s power_by_rate_value=%d tx_rate=0x%X rf_path=%d tx_num=%d\n",
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__func__, power_by_rate_value, tx_rate, rf_path, tx_num);
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"Call:%s tx_limit=%d reg_pwr_tbl_sel=0x%X band_width=%d channel=%d\n",
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__func__, tx_limit, reg_pwr_tbl_sel, band_width,
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channel);
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power_by_rate_value = power_by_rate_value > tx_limit ? tx_limit : power_by_rate_value;
288
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switch (rf_path) {
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case RF_PATH_A:
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tssi_value = cali_info->delta_swing_tssi_table_5ga[1][power_by_rate_value];
292
break;
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case RF_PATH_B:
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tssi_value = cali_info->delta_swing_tssi_table_5gb[1][power_by_rate_value];
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break;
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case RF_PATH_C:
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tssi_value = cali_info->delta_swing_tssi_table_5gc[1][power_by_rate_value];
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break;
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case RF_PATH_D:
303
tssi_value = cali_info->delta_swing_tssi_table_5gd[1][power_by_rate_value];
304
break;
305
306
default:
307
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
308
"Call:%s Wrong path name!!!!\n", __func__);
309
break;
310
}
311
} else if (channel >= 149 && channel <= 173) {
312
power_by_rate_value = phy_get_tx_power_by_rate_original(adapter, BAND_ON_5G, (enum rf_path)rf_path, tx_num, tx_rate);
313
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tx_limit = phy_get_tx_power_limit_original(adapter, reg_pwr_tbl_sel, BAND_ON_5G, band_width, RF_PATH_A, tx_rate, channel);
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
317
"Call:%s power_by_rate_value=%d tx_rate=0x%X rf_path=%d tx_num=%d\n",
318
__func__, power_by_rate_value, tx_rate, rf_path, tx_num);
319
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
320
"Call:%s tx_limit=%d reg_pwr_tbl_sel=0x%X band_width=%d channel=%d\n",
321
__func__, tx_limit, reg_pwr_tbl_sel, band_width,
322
channel);
323
324
power_by_rate_value = power_by_rate_value > tx_limit ? tx_limit : power_by_rate_value;
325
326
switch (rf_path) {
327
case RF_PATH_A:
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tssi_value = cali_info->delta_swing_tssi_table_5ga[2][power_by_rate_value];
329
break;
330
331
case RF_PATH_B:
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tssi_value = cali_info->delta_swing_tssi_table_5gb[2][power_by_rate_value];
333
break;
334
335
case RF_PATH_C:
336
tssi_value = cali_info->delta_swing_tssi_table_5gc[2][power_by_rate_value];
337
break;
338
339
case RF_PATH_D:
340
tssi_value = cali_info->delta_swing_tssi_table_5gd[2][power_by_rate_value];
341
break;
342
343
default:
344
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
345
"Call:%s Wrong path name!!!!\n", __func__);
346
break;
347
}
348
}
349
350
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s index=%d tssi_value=%d\n",
351
__func__, power_by_rate_value, tssi_value);
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353
#endif /*CONFIG_PHYDM_POWERTRACK_BY_TSSI*/
354
355
return tssi_value;
356
}
357
358
boolean get_tssi_mode_tx_agc_bb_swing_offset(struct dm_struct *dm,
359
enum pwrtrack_method method,
360
u8 rf_path, u32 offset_vaule,
361
u8 tx_power_index_offest)
362
{
363
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
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365
u8 bb_swing_upper_bound = cali_info->default_ofdm_index + 10;
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u8 bb_swing_lower_bound = 0;
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u8 tx_agc_index = (u8)cali_info->absolute_ofdm_swing_idx[rf_path];
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u8 tx_bb_swing_index = (u8)cali_info->bb_swing_idx_ofdm[rf_path];
369
370
if (tx_power_index_offest > 0XF)
371
tx_power_index_offest = 0XF;
372
373
if (tx_agc_index == 0 && tx_bb_swing_index == cali_info->default_ofdm_index) {
374
if ((offset_vaule & 0X20) >> 5 == 0) {
375
offset_vaule = offset_vaule & 0X1F;
376
377
if (offset_vaule > tx_power_index_offest) {
378
tx_agc_index = tx_power_index_offest;
379
tx_bb_swing_index = tx_bb_swing_index + (u8)offset_vaule - tx_power_index_offest;
380
381
if (tx_bb_swing_index > bb_swing_upper_bound)
382
tx_bb_swing_index = bb_swing_upper_bound;
383
384
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
385
"tx_agc_index(0) tx_bb_swing_index(18) +++ ( offset_vaule > 0XF) offset_vaule = 0X%X TXAGCIndex = 0X%X tx_bb_swing_index = %d\n",
386
offset_vaule, tx_agc_index,
387
tx_bb_swing_index);
388
} else {
389
tx_agc_index = (u8)offset_vaule;
390
tx_bb_swing_index = cali_info->default_ofdm_index;
391
392
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"tx_agc_index(0) tx_bb_swing_index(18) +++ ( offset_vaule <= 0XF) offset_vaule = 0X%X TXAGCIndex = 0X%X tx_bb_swing_index = %d\n",
394
offset_vaule, tx_agc_index,
395
tx_bb_swing_index);
396
}
397
} else {
398
tx_agc_index = 0;
399
offset_vaule = ((~offset_vaule) + 1) & 0X1F;
400
401
if (tx_bb_swing_index >= (u8)offset_vaule)
402
tx_bb_swing_index = tx_bb_swing_index - (u8)offset_vaule;
403
else
404
tx_bb_swing_index = bb_swing_lower_bound;
405
406
if (tx_bb_swing_index <= bb_swing_lower_bound)
407
tx_bb_swing_index = bb_swing_lower_bound;
408
409
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
410
"tx_agc_index(0) tx_bb_swing_index(18) --- offset_vaule = 0X%X TXAGCIndex = 0X%X tx_bb_swing_index = %d\n",
411
offset_vaule, tx_agc_index, tx_bb_swing_index);
412
}
413
414
} else if (tx_agc_index > 0 && tx_bb_swing_index == cali_info->default_ofdm_index) {
415
if ((offset_vaule & 0X20) >> 5 == 0) {
416
if (offset_vaule > tx_power_index_offest) {
417
tx_agc_index = tx_power_index_offest;
418
tx_bb_swing_index = tx_bb_swing_index + (u8)offset_vaule - tx_power_index_offest;
419
420
if (tx_bb_swing_index > bb_swing_upper_bound)
421
tx_bb_swing_index = bb_swing_upper_bound;
422
} else
423
tx_agc_index = (u8)offset_vaule;
424
425
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
426
"tx_agc_index > 0 tx_bb_swing_index(18) +++ offset_vaule = 0X%X TXAGCIndex = 0X%X tx_bb_swing_index = %d\n",
427
offset_vaule, tx_agc_index, tx_bb_swing_index);
428
} else {
429
tx_agc_index = 0;
430
offset_vaule = ((~offset_vaule) + 1) & 0X1F;
431
432
if (tx_bb_swing_index >= (u8)offset_vaule)
433
tx_bb_swing_index = tx_bb_swing_index - (u8)offset_vaule;
434
else
435
tx_bb_swing_index = bb_swing_lower_bound;
436
437
if (tx_bb_swing_index <= bb_swing_lower_bound)
438
tx_bb_swing_index = bb_swing_lower_bound;
439
440
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
441
"tx_agc_index > 0 tx_bb_swing_index(18) --- offset_vaule = 0X%X TXAGCIndex = 0X%X tx_bb_swing_index = %d\n",
442
offset_vaule, tx_agc_index, tx_bb_swing_index);
443
}
444
445
} else if (tx_agc_index > 0 && tx_bb_swing_index > cali_info->default_ofdm_index) {
446
if ((offset_vaule & 0X20) >> 5 == 0) {
447
tx_agc_index = tx_power_index_offest;
448
tx_bb_swing_index = tx_bb_swing_index + (u8)offset_vaule - tx_power_index_offest;
449
450
if (tx_bb_swing_index > bb_swing_upper_bound)
451
tx_bb_swing_index = bb_swing_upper_bound;
452
453
if (tx_bb_swing_index < cali_info->default_ofdm_index) {
454
tx_agc_index = tx_power_index_offest - (cali_info->default_ofdm_index - tx_bb_swing_index);
455
tx_bb_swing_index = cali_info->default_ofdm_index;
456
}
457
} else {
458
tx_agc_index = 0;
459
offset_vaule = ((~offset_vaule) + 1) & 0X1F;
460
461
if (tx_bb_swing_index >= (u8)offset_vaule)
462
tx_bb_swing_index = cali_info->default_ofdm_index - (u8)offset_vaule;
463
else
464
tx_bb_swing_index = bb_swing_lower_bound;
465
466
if (tx_bb_swing_index <= bb_swing_lower_bound)
467
tx_bb_swing_index = bb_swing_lower_bound;
468
}
469
470
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
471
"tx_agc_index>0 tx_bb_swing_index>18 --- offset_vaule = 0X%X TXAGCIndex = 0X%X tx_bb_swing_index = %d offset_vaule=%d\n",
472
offset_vaule, tx_agc_index, tx_bb_swing_index,
473
offset_vaule - tx_power_index_offest);
474
475
} else if (tx_agc_index == 0 && tx_bb_swing_index < cali_info->default_ofdm_index) {
476
if ((offset_vaule & 0X20) >> 5 == 1) {
477
offset_vaule = ((~offset_vaule) + 1) & 0X1F;
478
479
if (tx_bb_swing_index >= (u8)offset_vaule)
480
tx_bb_swing_index = tx_bb_swing_index - (u8)offset_vaule;
481
else
482
tx_bb_swing_index = bb_swing_lower_bound;
483
} else {
484
offset_vaule = (offset_vaule & 0x1F);
485
tx_bb_swing_index = tx_bb_swing_index + (u8)offset_vaule;
486
487
if (tx_bb_swing_index > cali_info->default_ofdm_index) {
488
tx_agc_index = tx_bb_swing_index - cali_info->default_ofdm_index;
489
tx_bb_swing_index = cali_info->default_ofdm_index;
490
491
if (tx_agc_index > tx_power_index_offest) {
492
tx_bb_swing_index = cali_info->default_ofdm_index + (u8)(tx_agc_index)-tx_power_index_offest;
493
tx_agc_index = tx_power_index_offest;
494
495
if (tx_bb_swing_index > bb_swing_upper_bound)
496
tx_bb_swing_index = bb_swing_upper_bound;
497
}
498
}
499
}
500
501
if (tx_bb_swing_index <= bb_swing_lower_bound) {
502
tx_bb_swing_index = bb_swing_lower_bound;
503
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
504
"Call %s Path_%d BBSwing Lower Bound\n",
505
__func__, rf_path);
506
}
507
508
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
509
"tx_agc_index(0) tx_bb_swing_index < 18 offset_vaule = 0X%X TXAGCIndex = 0X%X tx_bb_swing_index = %d\n",
510
offset_vaule, tx_agc_index, tx_bb_swing_index);
511
}
512
513
if ((tx_agc_index == cali_info->absolute_ofdm_swing_idx[rf_path]) && (tx_bb_swing_index == cali_info->bb_swing_idx_ofdm[rf_path]))
514
return false;
515
516
else {
517
cali_info->absolute_ofdm_swing_idx[rf_path] = tx_agc_index;
518
cali_info->bb_swing_idx_ofdm[rf_path] = tx_bb_swing_index;
519
return true;
520
}
521
}
522
523
void set_tx_agc_bb_swing_offset(struct dm_struct *dm,
524
enum pwrtrack_method method, u8 rf_path)
525
{
526
struct _ADAPTER *adapter = dm->adapter;
527
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
528
529
u8 tx_rate = 0xFF;
530
u8 channel = *dm->channel;
531
u8 band_width = hal_data->current_channel_bw;
532
u32 tx_path = hal_data->antenna_tx_path;
533
534
u8 tssi_value = 0;
535
u8 tx_power_index = 0;
536
u8 tx_power_index_offest = 0;
537
u32 offset_vaule = 0;
538
u32 tssi_function = 0;
539
u32 txbb_swing = 0;
540
u8 tx_bb_swing_index = 0;
541
u32 tx_agc_index = 0;
542
u32 wait_tx_agc_offset_timer = 0;
543
u8 i = 0;
544
boolean rtn = false;
545
546
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
547
struct _hal_rf_ *rf = &(dm->rf_table);
548
549
if (*dm->mp_mode == true) {
550
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
551
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
552
#if (MP_DRIVER == 1)
553
PMPT_CONTEXT p_mpt_ctx = &(adapter->mpt_ctx);
554
555
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
556
#endif
557
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
558
#ifdef CONFIG_MP_INCLUDED
559
PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
560
561
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
562
#endif
563
#endif
564
#endif
565
} else {
566
u16 rate = *(dm->forced_data_rate);
567
568
if (!rate) { /*auto rate*/
569
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
570
tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
571
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
572
if (dm->number_linked_client != 0)
573
tx_rate = hw_rate_to_m_rate(dm->tx_rate);
574
else
575
tx_rate = rf->p_rate_index;
576
#endif
577
} else /*force rate*/
578
tx_rate = (u8)rate;
579
}
580
581
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__,
582
tx_rate);
583
584
if (method == TSSI_MODE) {
585
switch (rf_path) {
586
case RF_PATH_A:
587
/*Disable path B TSSI Circuit*/
588
odm_set_rf_reg(dm, RF_PATH_B, RF_0x65, BIT(10), 0);
589
/*Enable path A TSSI Circuit*/
590
odm_set_rf_reg(dm, RF_PATH_A, RF_0x65, BIT(10), 1);
591
592
/*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/
593
tssi_value = get_tssivalue(dm, TSSI_MODE, (enum rf_path)rf_path);
594
595
odm_set_rf_reg(dm, (enum rf_path)rf_path, RF_0x65, BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15), tssi_value);
596
597
/*Write BB 0xC8C for setting Max. packet (30) of tracking power and the initial value of TXAGC*/
598
odm_set_bb_reg(dm, R_0xc8c, BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14), 30);
599
600
odm_set_bb_reg(dm, R_0xc8c, BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8), 0);
601
602
/*Write BB TXAGC Initial Power index for EEPROM*/
603
tx_power_index = phy_get_tx_power_index_8814a(adapter, (enum rf_path)rf_path, tx_rate, band_width, channel);
604
odm_set_bb_reg(dm, R_0xc8c, BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), tx_power_index);
605
606
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
607
"Call %s tx_power_index=%d rf_path=%d tx_rate=%d band_width=%d channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n",
608
__func__,
609
odm_get_bb_reg(dm, R_0xc8c,
610
BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) |
611
BIT(1) | BIT(0)), rf_path, tx_rate, band_width,
612
channel,
613
odm_get_rf_reg(dm, (enum rf_path)rf_path,
614
RF_0x65,
615
BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15)),
616
odm_get_rf_reg(dm, (enum rf_path)rf_path,
617
RF_0x65, BIT(11) | BIT(10)));
618
619
/*Disable BB TSSI Power Tracking*/
620
odm_set_bb_reg(dm, R_0xc8c, BIT(7), 0);
621
/*Enable path A TSSI Circuit*/
622
odm_set_rf_reg(dm, RF_PATH_A, RF_0x65, BIT(10), 1);
623
/*Enable BB TSSI Power Tracking*/
624
odm_set_bb_reg(dm, R_0xc8c, BIT(7), 1);
625
626
/* delay_us(500);*/
627
wait_tx_agc_offset_timer = 0;
628
629
while ((odm_get_bb_reg(dm, R_0xd2c, BIT(30)) != 1) && ((tx_path & 8) == 8)) {
630
wait_tx_agc_offset_timer++;
631
632
if (wait_tx_agc_offset_timer >= 1000)
633
break;
634
}
635
636
/*Read the offset value at BB Reg.*/
637
offset_vaule = odm_get_bb_reg(dm, R_0xd2c, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24));
638
639
tssi_function = odm_get_bb_reg(dm, R_0xd2c, BIT(30));
640
641
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
642
"Call %s 0XD2C tssi_function[30]=0X%X offset_vaule[29:24]=0X%X rf_path=%d\n",
643
__func__, tssi_function, offset_vaule, rf_path);
644
645
/*Disable BB TSSI Power Tracking*/
646
odm_set_bb_reg(dm, R_0xc8c, BIT(7), 0);
647
/*Disable path A TSSI Circuit*/
648
odm_set_rf_reg(dm, RF_PATH_A, RF_0x65, BIT(10), 0);
649
650
if (tssi_function == 1) {
651
txbb_swing = odm_get_bb_reg(dm, REG_A_BBSWING, BBSWING_BITMASK);
652
653
for (i = 0; i <= 36; i++) {
654
if (txbb_swing == tx_scaling_table_jaguar[i]) {
655
cali_info->bb_swing_idx_ofdm[rf_path] = i;
656
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, " PathA txbb_swing = %d txbb_swing=0X%X\n", tx_bb_swing_index, txbb_swing);
657
break;
658
659
} else
660
cali_info->bb_swing_idx_ofdm[rf_path] = cali_info->default_ofdm_index;
661
}
662
663
cali_info->absolute_ofdm_swing_idx[rf_path] = (u8)odm_get_bb_reg(dm, REG_A_TX_AGC, TXAGC_BITMASK);
664
665
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
666
"TXAGCIndex = 0X%X tx_bb_swing_index = %d\n",
667
cali_info->absolute_ofdm_swing_idx[
668
rf_path],
669
cali_info->bb_swing_idx_ofdm[rf_path]);
670
671
tx_power_index_offest = 63 - tx_power_index;
672
673
rtn = get_tssi_mode_tx_agc_bb_swing_offset(dm, method, (enum rf_path)rf_path, offset_vaule, tx_power_index_offest);
674
675
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
676
" tx_agc_index = %d tx_bb_swing_index = %d rtn=%d\n",
677
cali_info->absolute_ofdm_swing_idx[
678
rf_path],
679
cali_info->bb_swing_idx_ofdm[rf_path],
680
rtn);
681
682
if (rtn == true) {
683
odm_set_bb_reg(dm, REG_A_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
684
odm_set_bb_reg(dm, REG_A_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); /*set BBswing*/
685
} else
686
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "TXAGC And BB Swing are the same path=%d\n", rf_path);
687
688
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
689
" ========================================================\n");
690
691
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
692
" OffsetValue(0XD2C)=0X%X TXAGC(REG_A_TX_AGC)=0X%X 0XC1C(PathC BBSwing)(%d)=0X%X\n",
693
odm_get_bb_reg(dm, R_0xd2c,
694
BIT(29) | BIT(28) | BIT(27) | BIT(26) |
695
BIT(25) | BIT(24)),
696
odm_get_bb_reg(dm, REG_A_TX_AGC,
697
TXAGC_BITMASK),
698
cali_info->bb_swing_idx_ofdm[rf_path],
699
odm_get_bb_reg(dm, REG_A_BBSWING,
700
BBSWING_BITMASK));
701
702
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
703
" 0X55[13:9]=0X%X 0X56=0X%X\n",
704
odm_get_rf_reg(dm, (enum rf_path)rf_path,
705
0X55,
706
BIT(13) | BIT(12) | BIT(11) | BIT(10) |
707
BIT(9)),
708
odm_get_rf_reg(dm, (enum rf_path)rf_path,
709
0X56, 0XFFFFFFFF));
710
711
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
712
" ========================================================\n");
713
714
} else
715
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
716
" TSSI does not Calculate Finish\n");
717
718
break;
719
720
case RF_PATH_B:
721
/*Disable path A TSSI Circuit*/
722
odm_set_rf_reg(dm, RF_PATH_A, RF_0x65, BIT(10), 0);
723
/*Enable path B TSSI Circuit*/
724
odm_set_rf_reg(dm, RF_PATH_B, RF_0x65, BIT(10), 1);
725
726
/*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/
727
tssi_value = get_tssivalue(dm, TSSI_MODE, (enum rf_path)rf_path);
728
729
odm_set_rf_reg(dm, (enum rf_path)rf_path, RF_0x65, BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15), tssi_value);
730
731
/*Write BB 0xE8C for setting Max. packet (30) of tracking power and the initial value of TXAGC*/
732
odm_set_bb_reg(dm, R_0xe8c, BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14), 30);
733
734
odm_set_bb_reg(dm, R_0xe8c, BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8), 0);
735
736
/*Write BB TXAGC Initial Power index for EEPROM*/
737
tx_power_index = phy_get_tx_power_index_8814a(adapter, (enum rf_path)rf_path, tx_rate, band_width, channel);
738
odm_set_bb_reg(dm, R_0xe8c, BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), tx_power_index);
739
740
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
741
"Call %s tx_power_index=%d rf_path=%d tx_rate=%d band_width=%d channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n",
742
__func__,
743
odm_get_bb_reg(dm, R_0xe8c,
744
BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) |
745
BIT(1) | BIT(0)), rf_path, tx_rate, band_width,
746
channel,
747
odm_get_rf_reg(dm, (enum rf_path)rf_path,
748
RF_0x65,
749
BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15)),
750
odm_get_rf_reg(dm, (enum rf_path)rf_path,
751
RF_0x65, BIT(11) | BIT(10)));
752
753
/*Disable BB TSSI Power Tracking*/
754
odm_set_bb_reg(dm, R_0xe8c, BIT(7), 0);
755
/*Enable path B TSSI Circuit*/
756
odm_set_rf_reg(dm, RF_PATH_B, RF_0x65, BIT(10), 1);
757
/*Enable BB TSSI Power Tracking*/
758
odm_set_bb_reg(dm, R_0xe8c, BIT(7), 1);
759
760
/* delay_us(500);*/
761
wait_tx_agc_offset_timer = 0;
762
763
while ((odm_get_bb_reg(dm, R_0xd6c, BIT(30)) != 1) && ((tx_path & 4) == 4)) {
764
wait_tx_agc_offset_timer++;
765
766
if (wait_tx_agc_offset_timer >= 1000)
767
break;
768
}
769
770
/*Read the offset value at BB Reg.*/
771
offset_vaule = odm_get_bb_reg(dm, R_0xd6c, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24));
772
773
tssi_function = odm_get_bb_reg(dm, R_0xd6c, BIT(30));
774
775
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
776
"Call %s 0XD6C tssi_function[30]=0X%X offset_vaule[29:24]=0X%X rf_path=%d\n",
777
__func__, tssi_function, offset_vaule, rf_path);
778
779
/*Disable BB TSSI Power Tracking*/
780
odm_set_bb_reg(dm, R_0xe8c, BIT(7), 0);
781
/*Disable path B TSSI Circuit*/
782
odm_set_rf_reg(dm, RF_PATH_B, RF_0x65, BIT(10), 0);
783
784
if (tssi_function == 1) {
785
txbb_swing = odm_get_bb_reg(dm, REG_B_BBSWING, BBSWING_BITMASK);
786
787
for (i = 0; i <= 36; i++) {
788
if (txbb_swing == tx_scaling_table_jaguar[i]) {
789
cali_info->bb_swing_idx_ofdm[rf_path] = i;
790
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, " PathB txbb_swing = %d txbb_swing=0X%X\n", tx_bb_swing_index, txbb_swing);
791
break;
792
793
} else
794
cali_info->bb_swing_idx_ofdm[rf_path] = cali_info->default_ofdm_index;
795
}
796
797
cali_info->absolute_ofdm_swing_idx[rf_path] = (u8)odm_get_bb_reg(dm, REG_B_TX_AGC, TXAGC_BITMASK);
798
799
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
800
"TXAGCIndex = 0X%X tx_bb_swing_index = %d\n",
801
cali_info->absolute_ofdm_swing_idx[
802
rf_path],
803
cali_info->bb_swing_idx_ofdm[rf_path]);
804
805
tx_power_index_offest = 63 - tx_power_index;
806
807
rtn = get_tssi_mode_tx_agc_bb_swing_offset(dm, method, (enum rf_path)rf_path, offset_vaule, tx_power_index_offest);
808
809
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
810
" tx_agc_index = %d tx_bb_swing_index = %d rtn=%d\n",
811
cali_info->absolute_ofdm_swing_idx[
812
rf_path],
813
cali_info->bb_swing_idx_ofdm[rf_path],
814
rtn);
815
816
if (rtn == true) {
817
odm_set_bb_reg(dm, REG_B_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
818
odm_set_bb_reg(dm, REG_B_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); /*set BBswing*/
819
} else
820
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "TXAGC And BB Swing are the same path=%d\n", rf_path);
821
822
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
823
" ========================================================\n");
824
825
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
826
" OffsetValue(0XD6C)=0X%X TXAGC(REG_B_TX_AGC)=0X%X 0XE1C(PathB BBSwing)(%d)=0X%X\n",
827
odm_get_bb_reg(dm, R_0xd6c,
828
BIT(29) | BIT(28) | BIT(27) | BIT(26) |
829
BIT(25) | BIT(24)),
830
odm_get_bb_reg(dm, REG_B_TX_AGC,
831
TXAGC_BITMASK),
832
cali_info->bb_swing_idx_ofdm[rf_path],
833
odm_get_bb_reg(dm, REG_B_BBSWING,
834
BBSWING_BITMASK));
835
836
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
837
" 0X55[13:9]=0X%X 0X56=0X%X\n",
838
odm_get_rf_reg(dm, (enum rf_path)rf_path,
839
0X55,
840
BIT(13) | BIT(12) | BIT(11) | BIT(10) |
841
BIT(9)),
842
odm_get_rf_reg(dm, (enum rf_path)rf_path,
843
0X56, 0XFFFFFFFF));
844
845
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
846
" ========================================================\n");
847
848
} else
849
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
850
" TSSI does not Calculate Finish\n");
851
852
break;
853
854
case RF_PATH_C:
855
/*Disable path D TSSI Circuit*/
856
odm_set_rf_reg(dm, RF_PATH_D, RF_0x65, BIT(10), 0);
857
/*Enable path C TSSI Circuit*/
858
odm_set_rf_reg(dm, RF_PATH_C, RF_0x65, BIT(10), 1);
859
860
/*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/
861
tssi_value = get_tssivalue(dm, TSSI_MODE, (enum rf_path)rf_path);
862
863
odm_set_rf_reg(dm, (enum rf_path)rf_path, RF_0x65, BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15), tssi_value);
864
865
/*Write BB 0x188C for setting Max. packet (30) of tracking power and the initial value of TXAGC*/
866
odm_set_bb_reg(dm, R_0x188c, BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14), 30);
867
868
odm_set_bb_reg(dm, R_0x188c, BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8), 0);
869
870
/*Write BB TXAGC Initial Power index for EEPROM*/
871
tx_power_index = phy_get_tx_power_index_8814a(adapter, (enum rf_path)rf_path, tx_rate, band_width, channel);
872
odm_set_bb_reg(dm, R_0x188c, BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), tx_power_index);
873
874
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
875
"Call %s tx_power_index=%d rf_path=%d tx_rate=%d band_width=%d channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n",
876
__func__,
877
odm_get_bb_reg(dm, R_0x188c,
878
BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) |
879
BIT(1) | BIT(0)), rf_path, tx_rate, band_width,
880
channel,
881
odm_get_rf_reg(dm, (enum rf_path)rf_path,
882
RF_0x65,
883
BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15)),
884
odm_get_rf_reg(dm, (enum rf_path)rf_path,
885
RF_0x65, BIT(11) | BIT(10)));
886
887
/*Disable BB TSSI Power Tracking*/
888
odm_set_bb_reg(dm, R_0x188c, BIT(7), 0);
889
/*Enable path C TSSI Circuit*/
890
odm_set_rf_reg(dm, RF_PATH_C, RF_0x65, BIT(10), 1);
891
/*Enable BB TSSI Power Tracking*/
892
odm_set_bb_reg(dm, R_0x188c, BIT(7), 1);
893
894
/* delay_us(500);*/
895
wait_tx_agc_offset_timer = 0;
896
897
while ((odm_get_bb_reg(dm, R_0xdac, BIT(30)) != 1) && ((tx_path & 2) == 2)) {
898
wait_tx_agc_offset_timer++;
899
900
if (wait_tx_agc_offset_timer >= 1000)
901
break;
902
}
903
904
/*Read the offset value at BB Reg.*/
905
offset_vaule = odm_get_bb_reg(dm, R_0xdac, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24));
906
907
tssi_function = odm_get_bb_reg(dm, R_0xdac, BIT(30));
908
909
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
910
"Call %s 0XDAC tssi_function[30]=0X%X offset_vaule[29:24]=0X%X rf_path=%d\n",
911
__func__, tssi_function, offset_vaule, rf_path);
912
913
/*Disable BB TSSI Power Tracking*/
914
odm_set_bb_reg(dm, R_0x188c, BIT(7), 0);
915
/*Disable path C TSSI Circuit*/
916
odm_set_rf_reg(dm, RF_PATH_C, RF_0x65, BIT(10), 0);
917
918
if (tssi_function == 1) {
919
txbb_swing = odm_get_bb_reg(dm, REG_C_BBSWING, BBSWING_BITMASK);
920
921
for (i = 0; i <= 36; i++) {
922
if (txbb_swing == tx_scaling_table_jaguar[i]) {
923
cali_info->bb_swing_idx_ofdm[rf_path] = i;
924
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, " PathC txbb_swing = %d txbb_swing=0X%X\n", tx_bb_swing_index, txbb_swing);
925
break;
926
927
} else
928
cali_info->bb_swing_idx_ofdm[rf_path] = cali_info->default_ofdm_index;
929
}
930
931
cali_info->absolute_ofdm_swing_idx[rf_path] = (u8)odm_get_bb_reg(dm, REG_C_TX_AGC, TXAGC_BITMASK);
932
933
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
934
"TXAGCIndex = 0X%X tx_bb_swing_index = %d\n",
935
cali_info->absolute_ofdm_swing_idx[
936
rf_path],
937
cali_info->bb_swing_idx_ofdm[rf_path]);
938
939
tx_power_index_offest = 63 - tx_power_index;
940
941
rtn = get_tssi_mode_tx_agc_bb_swing_offset(dm, method, (enum rf_path)rf_path, offset_vaule, tx_power_index_offest);
942
943
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
944
" tx_agc_index = %d tx_bb_swing_index = %d rtn=%d\n",
945
cali_info->absolute_ofdm_swing_idx[
946
rf_path],
947
cali_info->bb_swing_idx_ofdm[rf_path],
948
rtn);
949
950
if (rtn == true) {
951
odm_set_bb_reg(dm, REG_C_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
952
odm_set_bb_reg(dm, REG_C_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); /*set BBswing*/
953
} else
954
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "TXAGC And BB Swing are the same path=%d\n", rf_path);
955
956
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
957
" ========================================================\n");
958
959
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
960
" OffsetValue(0XDAC)=0X%X TXAGC(REG_C_TX_AGC)=0X%X 0X181C(PathC BBSwing)(%d)=0X%X\n",
961
odm_get_bb_reg(dm, R_0xdac,
962
BIT(29) | BIT(28) | BIT(27) | BIT(26) |
963
BIT(25) | BIT(24)),
964
odm_get_bb_reg(dm, REG_C_TX_AGC,
965
TXAGC_BITMASK),
966
cali_info->bb_swing_idx_ofdm[rf_path],
967
odm_get_bb_reg(dm, REG_C_BBSWING,
968
BBSWING_BITMASK));
969
970
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
971
" 0X55[13:9]=0X%X 0X56=0X%X\n",
972
odm_get_rf_reg(dm, (enum rf_path)rf_path,
973
0X55,
974
BIT(13) | BIT(12) | BIT(11) | BIT(10) |
975
BIT(9)),
976
odm_get_rf_reg(dm, (enum rf_path)rf_path,
977
0X56, 0XFFFFFFFF));
978
979
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
980
" ========================================================\n");
981
982
} else
983
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
984
" TSSI does not Calculate Finish\n");
985
986
break;
987
988
case RF_PATH_D:
989
/*Disable path C TSSI Circuit*/
990
odm_set_rf_reg(dm, RF_PATH_C, RF_0x65, BIT(10), 0);
991
/*Enable path D TSSI Circuit*/
992
odm_set_rf_reg(dm, RF_PATH_D, RF_0x65, BIT(10), 1);
993
994
/*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/
995
tssi_value = get_tssivalue(dm, TSSI_MODE, (enum rf_path)rf_path);
996
997
odm_set_rf_reg(dm, (enum rf_path)rf_path, RF_0x65, BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15), tssi_value);
998
999
/*Write BB 0x1A8C for setting Max. packet (30) of tracking power and the initial value of TXAGC*/
1000
odm_set_bb_reg(dm, R_0x1a8c, BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14), 30);
1001
1002
odm_set_bb_reg(dm, R_0x1a8c, BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8), 0);
1003
1004
/*Write BB TXAGC Initial Power index for EEPROM*/
1005
tx_power_index = phy_get_tx_power_index_8814a(adapter, (enum rf_path)rf_path, tx_rate, band_width, channel);
1006
odm_set_bb_reg(dm, R_0x1a8c, BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), tx_power_index);
1007
1008
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1009
"Call %s tx_power_index=%d rf_path=%d tx_rate=%d band_width=%d channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n",
1010
__func__,
1011
odm_get_bb_reg(dm, R_0x1a8c,
1012
BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) |
1013
BIT(1) | BIT(0)), rf_path, tx_rate, band_width,
1014
channel,
1015
odm_get_rf_reg(dm, (enum rf_path)rf_path,
1016
RF_0x65,
1017
BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15)),
1018
odm_get_rf_reg(dm, (enum rf_path)rf_path,
1019
RF_0x65, BIT(11) | BIT(10)));
1020
1021
/*Disable BB TSSI Power Tracking*/
1022
odm_set_bb_reg(dm, R_0x1a8c, BIT(7), 0);
1023
/*Enable path D TSSI Circuit*/
1024
odm_set_rf_reg(dm, RF_PATH_D, RF_0x65, BIT(10), 1);
1025
/*Enable BB TSSI Power Tracking*/
1026
odm_set_bb_reg(dm, R_0x1a8c, BIT(7), 1);
1027
1028
/* delay_us(500);*/
1029
wait_tx_agc_offset_timer = 0;
1030
1031
while ((odm_get_bb_reg(dm, R_0xdec, BIT(30)) != 1) && ((tx_path & 1) == 1)) {
1032
wait_tx_agc_offset_timer++;
1033
1034
if (wait_tx_agc_offset_timer >= 1000)
1035
break;
1036
}
1037
1038
/*Read the offset value at BB Reg.*/
1039
offset_vaule = odm_get_bb_reg(dm, R_0xdec, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24));
1040
1041
tssi_function = odm_get_bb_reg(dm, R_0xdec, BIT(30));
1042
1043
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1044
"Call %s 0XDEC tssi_function[30]=0X%X offset_vaule[29:24]=0X%X rf_path=%d\n",
1045
__func__, tssi_function, offset_vaule, rf_path);
1046
1047
/*Disable BB TSSI Power Tracking*/
1048
odm_set_bb_reg(dm, R_0x1a8c, BIT(7), 0);
1049
/*Disable path D TSSI Circuit*/
1050
odm_set_rf_reg(dm, RF_PATH_D, RF_0x65, BIT(10), 0);
1051
1052
if (tssi_function == 1) {
1053
txbb_swing = odm_get_bb_reg(dm, REG_D_BBSWING, BBSWING_BITMASK);
1054
1055
for (i = 0; i <= 36; i++) {
1056
if (txbb_swing == tx_scaling_table_jaguar[i]) {
1057
cali_info->bb_swing_idx_ofdm[rf_path] = i;
1058
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, " PathD txbb_swing = %d txbb_swing=0X%X\n", tx_bb_swing_index, txbb_swing);
1059
break;
1060
1061
} else
1062
cali_info->bb_swing_idx_ofdm[rf_path] = cali_info->default_ofdm_index;
1063
}
1064
1065
cali_info->absolute_ofdm_swing_idx[rf_path] = (u8)odm_get_bb_reg(dm, REG_D_TX_AGC, TXAGC_BITMASK);
1066
1067
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1068
"TXAGCIndex = 0X%X tx_bb_swing_index = %d\n",
1069
cali_info->absolute_ofdm_swing_idx[
1070
rf_path],
1071
cali_info->bb_swing_idx_ofdm[rf_path]);
1072
1073
tx_power_index_offest = 63 - tx_power_index;
1074
1075
rtn = get_tssi_mode_tx_agc_bb_swing_offset(dm, method, (enum rf_path)rf_path, offset_vaule, tx_power_index_offest);
1076
1077
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1078
" tx_agc_index = %d tx_bb_swing_index = %d rtn=%d\n",
1079
cali_info->absolute_ofdm_swing_idx[
1080
rf_path],
1081
cali_info->bb_swing_idx_ofdm[rf_path],
1082
rtn);
1083
1084
if (rtn == true) {
1085
odm_set_bb_reg(dm, REG_D_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
1086
odm_set_bb_reg(dm, REG_D_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); /*set BBswing*/
1087
} else
1088
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "TXAGC And BB Swing are the same path=%d\n", rf_path);
1089
1090
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1091
" ========================================================\n");
1092
1093
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1094
" OffsetValue(0XDEC)=0X%X TXAGC(REG_D_TX_AGC)=0X%X 0X1A1C(PathD BBSwing)(%d)=0X%X\n",
1095
odm_get_bb_reg(dm, R_0xdec,
1096
BIT(29) | BIT(28) | BIT(27) | BIT(26) |
1097
BIT(25) | BIT(24)),
1098
odm_get_bb_reg(dm, REG_D_TX_AGC,
1099
TXAGC_BITMASK),
1100
cali_info->bb_swing_idx_ofdm[rf_path],
1101
odm_get_bb_reg(dm, REG_D_BBSWING,
1102
BBSWING_BITMASK));
1103
1104
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1105
" 0X55[13:9]=0X%X 0X56=0X%X\n",
1106
odm_get_rf_reg(dm, (enum rf_path)rf_path,
1107
0X55,
1108
BIT(13) | BIT(12) | BIT(11) | BIT(10) |
1109
BIT(9)),
1110
odm_get_rf_reg(dm, (enum rf_path)rf_path,
1111
0X56, 0XFFFFFFFF));
1112
1113
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1114
" ========================================================\n");
1115
1116
} else
1117
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1118
" TSSI does not Calculate Finish\n");
1119
1120
break;
1121
1122
default:
1123
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1124
"Wrong path name!!!!\n");
1125
1126
break;
1127
}
1128
}
1129
}
1130
1131
boolean get_mix_mode_tx_agc_bb_swing_offset(struct dm_struct *dm,
1132
enum pwrtrack_method method,
1133
u8 rf_path,
1134
u8 tx_power_index_offest)
1135
{
1136
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
1137
1138
u8 bb_swing_upper_bound = cali_info->default_ofdm_index + 10;
1139
u8 bb_swing_lower_bound = 0;
1140
1141
s8 tx_agc_index = 0;
1142
u8 tx_bb_swing_index = cali_info->default_ofdm_index;
1143
1144
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1145
"Path_%d cali_info->absolute_ofdm_swing_idx[rf_path]=%d, tx_power_index_offest=%d\n",
1146
rf_path, cali_info->absolute_ofdm_swing_idx[rf_path],
1147
tx_power_index_offest);
1148
1149
if (tx_power_index_offest > 0XF)
1150
tx_power_index_offest = 0XF;
1151
1152
if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0 && cali_info->absolute_ofdm_swing_idx[rf_path] <= tx_power_index_offest) {
1153
tx_agc_index = cali_info->absolute_ofdm_swing_idx[rf_path];
1154
tx_bb_swing_index = cali_info->default_ofdm_index;
1155
} else if (cali_info->absolute_ofdm_swing_idx[rf_path] > tx_power_index_offest) {
1156
tx_agc_index = tx_power_index_offest;
1157
cali_info->remnant_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest;
1158
tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->remnant_ofdm_swing_idx[rf_path];
1159
1160
if (tx_bb_swing_index > bb_swing_upper_bound)
1161
tx_bb_swing_index = bb_swing_upper_bound;
1162
} else {
1163
tx_agc_index = 0;
1164
1165
if (cali_info->default_ofdm_index > (cali_info->absolute_ofdm_swing_idx[rf_path] * (-1)))
1166
tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->absolute_ofdm_swing_idx[rf_path];
1167
else
1168
tx_bb_swing_index = bb_swing_lower_bound;
1169
1170
if (tx_bb_swing_index < bb_swing_lower_bound)
1171
tx_bb_swing_index = bb_swing_lower_bound;
1172
}
1173
1174
cali_info->absolute_ofdm_swing_idx[rf_path] = tx_agc_index;
1175
cali_info->bb_swing_idx_ofdm[rf_path] = tx_bb_swing_index;
1176
1177
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1178
"MixMode Offset Path_%d cali_info->absolute_ofdm_swing_idx[rf_path]=%d cali_info->bb_swing_idx_ofdm[rf_path]=%d tx_power_index_offest=%d\n",
1179
rf_path, cali_info->absolute_ofdm_swing_idx[rf_path],
1180
cali_info->bb_swing_idx_ofdm[rf_path], tx_power_index_offest);
1181
1182
return true;
1183
}
1184
1185
void power_tracking_by_mix_mode(struct dm_struct *dm,
1186
enum pwrtrack_method method, u8 rf_path)
1187
{
1188
struct _ADAPTER *adapter = dm->adapter;
1189
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1190
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
1191
struct _hal_rf_ *rf = &(dm->rf_table);
1192
1193
u8 tx_rate = 0xFF;
1194
u8 channel = *dm->channel;
1195
u8 band_width = hal_data->current_channel_bw;
1196
u8 tx_power_index_offest = 0;
1197
u8 tx_power_index = 0;
1198
1199
if (*dm->mp_mode == true) {
1200
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1201
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1202
#if (MP_DRIVER == 1)
1203
PMPT_CONTEXT p_mpt_ctx = &(adapter->mpt_ctx);
1204
1205
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
1206
#endif
1207
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1208
#ifdef CONFIG_MP_INCLUDED
1209
PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
1210
1211
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
1212
#endif
1213
#endif
1214
#endif
1215
} else {
1216
u16 rate = *(dm->forced_data_rate);
1217
1218
if (!rate) { /*auto rate*/
1219
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1220
tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
1221
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1222
if (dm->number_linked_client != 0)
1223
tx_rate = hw_rate_to_m_rate(dm->tx_rate);
1224
else
1225
tx_rate = rf->p_rate_index;
1226
#endif
1227
} else /*force rate*/
1228
tx_rate = (u8)rate;
1229
}
1230
1231
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__,
1232
tx_rate);
1233
1234
if ((cali_info->power_index_offset[RF_PATH_A] != 0 ||
1235
cali_info->power_index_offset[RF_PATH_B] != 0 ||
1236
cali_info->power_index_offset[RF_PATH_C] != 0 ||
1237
cali_info->power_index_offset[RF_PATH_D] != 0) &&
1238
cali_info->txpowertrack_control && hal_data->eeprom_thermal_meter != 0xff) {
1239
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1240
"****************Path_%d POWER Tracking MIX MODE**********\n",
1241
rf_path);
1242
1243
tx_power_index = phy_get_tx_power_index_8814a(adapter, (enum rf_path)rf_path, tx_rate, band_width, channel);
1244
tx_power_index_offest = 63 - tx_power_index;
1245
1246
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1247
"cali_info->absolute_ofdm_swing_idx[%d] =%d tx_power_index=%d\n",
1248
rf_path, cali_info->absolute_ofdm_swing_idx[rf_path],
1249
tx_power_index);
1250
1251
switch (rf_path) {
1252
case RF_PATH_A:
1253
get_mix_mode_tx_agc_bb_swing_offset(dm, method, (enum rf_path)rf_path, tx_power_index_offest);
1254
odm_set_bb_reg(dm, REG_A_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
1255
odm_set_bb_reg(dm, REG_A_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); /*set BBswing*/
1256
break;
1257
1258
case RF_PATH_B:
1259
get_mix_mode_tx_agc_bb_swing_offset(dm, method, (enum rf_path)rf_path, tx_power_index_offest);
1260
odm_set_bb_reg(dm, REG_B_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
1261
odm_set_bb_reg(dm, REG_B_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); /*set BBswing*/
1262
break;
1263
1264
case RF_PATH_C:
1265
get_mix_mode_tx_agc_bb_swing_offset(dm, method, (enum rf_path)rf_path, tx_power_index_offest);
1266
odm_set_bb_reg(dm, REG_C_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
1267
odm_set_bb_reg(dm, REG_C_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); /*set BBswing*/
1268
break;
1269
1270
case RF_PATH_D:
1271
get_mix_mode_tx_agc_bb_swing_offset(dm, method, (enum rf_path)rf_path, tx_power_index_offest);
1272
odm_set_bb_reg(dm, REG_D_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
1273
odm_set_bb_reg(dm, REG_D_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); /*set BBswing*/
1274
break;
1275
1276
default:
1277
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1278
"Wrong path name!!!!\n");
1279
break;
1280
}
1281
} else
1282
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1283
"Power index is the same, eeprom_thermal_meter = 0XFF or txpowertrack_control is Disable !!!!\n");
1284
}
1285
1286
void power_tracking_by_tssi_mode(struct dm_struct *dm,
1287
enum pwrtrack_method method, u8 rf_path)
1288
{
1289
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1290
"****************Path_%d POWER Tracking TSSI_MODE**********\n",
1291
rf_path);
1292
1293
set_tx_agc_bb_swing_offset(dm, TSSI_MODE, (enum rf_path)rf_path);
1294
1295
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1296
"****************Path_%d End POWER Tracking TSSI_MODE**********\n",
1297
rf_path);
1298
1299
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n");
1300
}
1301
1302
void odm_tx_pwr_track_set_pwr8814a(void *dm_void, enum pwrtrack_method method,
1303
u8 rf_path, u8 channel_mapped_index)
1304
{
1305
struct dm_struct *dm = (struct dm_struct *)dm_void;
1306
void *adapter = dm->adapter;
1307
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1308
1309
u8 final_ofdm_swing_index = 0;
1310
u8 channel = *dm->channel;
1311
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
1312
1313
/*K-Free*/
1314
#if 0
1315
s8 txbb_index = 0;
1316
s8 txbb_upper_bound = 10, txbb_lower_bound = -5;
1317
1318
txbb_index = cali_info->kfree_offset[rf_path] / 2;
1319
1320
if (txbb_index > txbb_upper_bound)
1321
txbb_index = txbb_upper_bound;
1322
else if (txbb_index < txbb_lower_bound)
1323
txbb_index = txbb_lower_bound;
1324
1325
if (txbb_index >= 0) {
1326
odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 1);
1327
odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, (BIT(18) | BIT17 | BIT16 | BIT15), txbb_index); /*set RF Reg0x55 per path*/
1328
} else {
1329
odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 0);
1330
odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, (BIT(18) | BIT(17) | BIT(16) | BIT(15)), (-1) * txbb_index);
1331
}
1332
1333
#endif
1334
1335
if (method == TXAGC) {
1336
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1337
"****************Path_%d POWER Tracking No TXAGC MODE**********\n",
1338
rf_path);
1339
1340
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1341
"cali_info->absolute_ofdm_swing_idx[%d] =%d\n", rf_path,
1342
cali_info->absolute_ofdm_swing_idx[rf_path]);
1343
} else if (method == TSSI_MODE)
1344
power_tracking_by_tssi_mode(dm, TSSI_MODE, (enum rf_path)rf_path);
1345
else if (method == BBSWING) { /*use for mp driver clean power tracking status*/
1346
switch (rf_path) {
1347
case RF_PATH_A:
1348
odm_set_bb_reg(dm, REG_A_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
1349
odm_set_bb_reg(dm, REG_A_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); /*set BBswing*/
1350
break;
1351
1352
case RF_PATH_B:
1353
odm_set_bb_reg(dm, REG_B_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
1354
odm_set_bb_reg(dm, REG_B_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); /*set BBswing*/
1355
break;
1356
1357
case RF_PATH_C:
1358
odm_set_bb_reg(dm, REG_C_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
1359
odm_set_bb_reg(dm, REG_C_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); /*set BBswing*/
1360
break;
1361
1362
case RF_PATH_D:
1363
odm_set_bb_reg(dm, REG_D_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
1364
odm_set_bb_reg(dm, REG_D_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); /*set BBswing*/
1365
break;
1366
1367
default:
1368
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1369
"Wrong path name!!!!\n");
1370
1371
break;
1372
}
1373
1374
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1375
"rf_path=%d Clear 8814 Power tracking TXAGC=%d BBSwing=%d\n",
1376
rf_path, cali_info->absolute_ofdm_swing_idx[rf_path],
1377
cali_info->bb_swing_idx_ofdm[rf_path]);
1378
1379
} else if (method == MIX_MODE)
1380
power_tracking_by_mix_mode(dm, MIX_MODE, (enum rf_path)rf_path);
1381
else if (method == MIX_2G_TSSI_5G_MODE) {
1382
if (channel <= 14)
1383
power_tracking_by_mix_mode(dm, MIX_MODE, (enum rf_path)rf_path);
1384
else
1385
power_tracking_by_tssi_mode(dm, TSSI_MODE, (enum rf_path)rf_path);
1386
} else if (method == MIX_5G_TSSI_2G_MODE) {
1387
if (channel <= 14)
1388
power_tracking_by_tssi_mode(dm, TSSI_MODE, (enum rf_path)rf_path);
1389
else
1390
power_tracking_by_mix_mode(dm, MIX_MODE, (enum rf_path)rf_path);
1391
}
1392
} /*odm_tx_pwr_track_set_pwr8814a*/
1393
1394
void get_delta_swing_table_8814a(void *dm_void, u8 **temperature_up_a,
1395
u8 **temperature_down_a, u8 **temperature_up_b,
1396
u8 **temperature_down_b)
1397
{
1398
struct dm_struct *dm = (struct dm_struct *)dm_void;
1399
struct _ADAPTER *adapter = dm->adapter;
1400
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
1401
struct _hal_rf_ *rf = &(dm->rf_table);
1402
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1403
u8 tx_rate = 0xFF;
1404
u8 channel = *dm->channel;
1405
1406
if (*dm->mp_mode == true) {
1407
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1408
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1409
#if (MP_DRIVER == 1)
1410
PMPT_CONTEXT p_mpt_ctx = &(adapter->mpt_ctx);
1411
1412
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
1413
#endif
1414
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1415
#ifdef CONFIG_MP_INCLUDED
1416
PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
1417
1418
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
1419
#endif
1420
#endif
1421
#endif
1422
} else {
1423
u16 rate = *(dm->forced_data_rate);
1424
1425
if (!rate) { /*auto rate*/
1426
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1427
tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
1428
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1429
if (dm->number_linked_client != 0)
1430
tx_rate = hw_rate_to_m_rate(dm->tx_rate);
1431
else
1432
tx_rate = rf->p_rate_index;
1433
#endif
1434
} else /*force rate*/
1435
tx_rate = (u8)rate;
1436
}
1437
1438
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__,
1439
tx_rate);
1440
1441
if (1 <= channel && channel <= 14) {
1442
if (IS_CCK_RATE(tx_rate)) {
1443
*temperature_up_a = cali_info->delta_swing_table_idx_2g_cck_a_p;
1444
*temperature_down_a = cali_info->delta_swing_table_idx_2g_cck_a_n;
1445
*temperature_up_b = cali_info->delta_swing_table_idx_2g_cck_b_p;
1446
*temperature_down_b = cali_info->delta_swing_table_idx_2g_cck_b_n;
1447
} else {
1448
*temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;
1449
*temperature_down_a = cali_info->delta_swing_table_idx_2ga_n;
1450
*temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;
1451
*temperature_down_b = cali_info->delta_swing_table_idx_2gb_n;
1452
}
1453
} else if (36 <= channel && channel <= 64) {
1454
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[0];
1455
*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[0];
1456
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[0];
1457
*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[0];
1458
} else if (100 <= channel && channel <= 144) {
1459
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[1];
1460
*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[1];
1461
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[1];
1462
*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[1];
1463
} else if (149 <= channel && channel <= 177) {
1464
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[2];
1465
*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[2];
1466
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[2];
1467
*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[2];
1468
} else {
1469
*temperature_up_a = (u8 *)delta_swing_table_idx_2ga_p_8188e;
1470
*temperature_down_a = (u8 *)delta_swing_table_idx_2ga_n_8188e;
1471
*temperature_up_b = (u8 *)delta_swing_table_idx_2ga_p_8188e;
1472
*temperature_down_b = (u8 *)delta_swing_table_idx_2ga_n_8188e;
1473
}
1474
1475
return;
1476
}
1477
1478
void get_delta_swing_table_8814a_path_cd(void *dm_void, u8 **temperature_up_c,
1479
u8 **temperature_down_c,
1480
u8 **temperature_up_d,
1481
u8 **temperature_down_d)
1482
{
1483
struct dm_struct *dm = (struct dm_struct *)dm_void;
1484
struct _ADAPTER *adapter = dm->adapter;
1485
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
1486
struct _hal_rf_ *rf = &(dm->rf_table);
1487
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1488
u8 tx_rate = 0xFF;
1489
u8 channel = *dm->channel;
1490
1491
if (*dm->mp_mode == true) {
1492
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1493
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1494
#if (MP_DRIVER == 1)
1495
PMPT_CONTEXT p_mpt_ctx = &(adapter->mpt_ctx);
1496
1497
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
1498
#endif
1499
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1500
#ifdef CONFIG_MP_INCLUDED
1501
PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
1502
1503
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
1504
#endif
1505
#endif
1506
#endif
1507
} else {
1508
u16 rate = *(dm->forced_data_rate);
1509
1510
if (!rate) { /*auto rate*/
1511
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1512
tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
1513
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1514
if (dm->number_linked_client != 0)
1515
tx_rate = hw_rate_to_m_rate(dm->tx_rate);
1516
else
1517
tx_rate = rf->p_rate_index;
1518
#endif
1519
} else /*force rate*/
1520
tx_rate = (u8)rate;
1521
}
1522
1523
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__,
1524
tx_rate);
1525
1526
if (1 <= channel && channel <= 14) {
1527
if (IS_CCK_RATE(tx_rate)) {
1528
*temperature_up_c = cali_info->delta_swing_table_idx_2g_cck_c_p;
1529
*temperature_down_c = cali_info->delta_swing_table_idx_2g_cck_c_n;
1530
*temperature_up_d = cali_info->delta_swing_table_idx_2g_cck_d_p;
1531
*temperature_down_d = cali_info->delta_swing_table_idx_2g_cck_d_n;
1532
} else {
1533
*temperature_up_c = cali_info->delta_swing_table_idx_2gc_p;
1534
*temperature_down_c = cali_info->delta_swing_table_idx_2gc_n;
1535
*temperature_up_d = cali_info->delta_swing_table_idx_2gd_p;
1536
*temperature_down_d = cali_info->delta_swing_table_idx_2gd_n;
1537
}
1538
} else if (36 <= channel && channel <= 64) {
1539
*temperature_up_c = cali_info->delta_swing_table_idx_5gc_p[0];
1540
*temperature_down_c = cali_info->delta_swing_table_idx_5gc_n[0];
1541
*temperature_up_d = cali_info->delta_swing_table_idx_5gd_p[0];
1542
*temperature_down_d = cali_info->delta_swing_table_idx_5gd_n[0];
1543
} else if (100 <= channel && channel <= 144) {
1544
*temperature_up_c = cali_info->delta_swing_table_idx_5gc_p[1];
1545
*temperature_down_c = cali_info->delta_swing_table_idx_5gc_n[1];
1546
*temperature_up_d = cali_info->delta_swing_table_idx_5gd_p[1];
1547
*temperature_down_d = cali_info->delta_swing_table_idx_5gd_n[1];
1548
} else if (149 <= channel && channel <= 177) {
1549
*temperature_up_c = cali_info->delta_swing_table_idx_5gc_p[2];
1550
*temperature_down_c = cali_info->delta_swing_table_idx_5gc_n[2];
1551
*temperature_up_d = cali_info->delta_swing_table_idx_5gd_p[2];
1552
*temperature_down_d = cali_info->delta_swing_table_idx_5gd_n[2];
1553
} else {
1554
*temperature_up_c = (u8 *)delta_swing_table_idx_2ga_p_8188e;
1555
*temperature_down_c = (u8 *)delta_swing_table_idx_2ga_n_8188e;
1556
*temperature_up_d = (u8 *)delta_swing_table_idx_2ga_p_8188e;
1557
*temperature_down_d = (u8 *)delta_swing_table_idx_2ga_n_8188e;
1558
}
1559
1560
return;
1561
}
1562
1563
void configure_txpower_track_8814a(struct txpwrtrack_cfg *config)
1564
{
1565
config->swing_table_size_cck = CCK_TABLE_SIZE;
1566
config->swing_table_size_ofdm = OFDM_TABLE_SIZE;
1567
config->threshold_iqk = 8;
1568
config->average_thermal_num = AVG_THERMAL_NUM_8814A;
1569
config->rf_path_count = MAX_PATH_NUM_8814A;
1570
config->thermal_reg_addr = RF_T_METER_88E;
1571
1572
config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr8814a;
1573
config->do_iqk = do_iqk_8814a;
1574
config->phy_lc_calibrate = halrf_lck_trigger;
1575
config->get_delta_swing_table = get_delta_swing_table_8814a;
1576
config->get_delta_swing_table8814only = get_delta_swing_table_8814a_path_cd;
1577
}
1578
1579
void _phy_lc_calibrate_8814a(struct dm_struct *dm, boolean is2T)
1580
{
1581
u32 /*rf_amode=0, rf_bmode=0,*/ lc_cal = 0, tmp = 0, cnt;
1582
1583
/* Check continuous TX and Packet TX */
1584
u32 reg0x914 = odm_read_4byte(dm, REG_SINGLE_TONE_CONT_TX_JAGUAR);
1585
;
1586
1587
/* Backup RF reg18. */
1588
1589
if ((reg0x914 & 0x70000) == 0)
1590
odm_write_1byte(dm, REG_TXPAUSE, 0xFF);
1591
1592
/* 3 3. Read RF reg18 */
1593
lc_cal = odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK);
1594
1595
/* 3 4. Set LC calibration begin bit15 */
1596
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, 0x1b126);
1597
1598
ODM_delay_ms(100);
1599
1600
for (cnt = 0; cnt < 100; cnt++) {
1601
if (odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
1602
break;
1603
ODM_delay_ms(10);
1604
}
1605
RF_DBG(dm, DBG_RF_IQK, "retry cnt = %d\n", cnt);
1606
1607
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, 0x13126);
1608
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, 0x13124);
1609
/* 3 Restore original situation */
1610
if ((reg0x914 & 70000) == 0)
1611
odm_write_1byte(dm, REG_TXPAUSE, 0x00);
1612
1613
/* Recover channel number */
1614
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal);
1615
1616
pr_debug("Call %s\n", __FUNCTION__);
1617
}
1618
1619
void _phy_ap_calibrate_8814a(
1620
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1621
struct dm_struct *dm,
1622
#else
1623
void *adapter,
1624
#endif
1625
s8 delta, boolean is2T)
1626
{
1627
}
1628
1629
void phy_lc_calibrate_8814a(void *dm_void)
1630
{
1631
struct dm_struct *dm = (struct dm_struct *)dm_void;
1632
1633
_phy_lc_calibrate_8814a(dm, true);
1634
}
1635
1636
void phy_ap_calibrate_8814a(
1637
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1638
struct dm_struct *dm,
1639
#else
1640
void *adapter,
1641
#endif
1642
s8 delta)
1643
{
1644
}
1645
1646
void phy_dp_calibrate_8814a(struct dm_struct *dm)
1647
{
1648
}
1649
1650
boolean
1651
_phy_query_rf_path_switch_8814a(void *adapter)
1652
{
1653
return true;
1654
}
1655
1656
boolean phy_query_rf_path_switch_8814a(void *adapter)
1657
{
1658
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1659
1660
#if DISABLE_BB_RF
1661
return true;
1662
#endif
1663
1664
return _phy_query_rf_path_switch_8814a(adapter);
1665
}
1666
1667
void _phy_set_rf_path_switch_8814a(
1668
#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
1669
struct dm_struct *dm,
1670
#else
1671
void *adapter,
1672
#endif
1673
boolean is_main, boolean is2T)
1674
{
1675
}
1676
void phy_set_rf_path_switch_8814a(
1677
#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
1678
struct dm_struct *dm,
1679
#else
1680
void *adapter,
1681
#endif
1682
boolean is_main)
1683
{
1684
}
1685
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#endif /* (RTL8814A_SUPPORT == 0)*/
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