CoCalc -- halrf_8814a

GitHub Repository: nu11secur1ty/Kali-Linux
Path: blob/master/ALFA-W1F1/RTL8814AU/hal/phydm/halrf/rtl8814a/halrf_8814a_win.c
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/******************************************************************************
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 *
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 * Copyright(c) 2007 - 2017 Realtek Corporation.
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 *
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms of version 2 of the GNU General Public License as
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 * published by the Free Software Foundation.
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 *
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 * This program is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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 * more details.
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 *
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 *****************************************************************************/
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#include "mp_precomp.h"
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18
#if RT_PLATFORM==PLATFORM_MACOSX
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#include "phydm_precomp.h"
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#else
21
#include "../phydm_precomp.h"
22
#endif
23
#if (RTL8814A_SUPPORT == 1)
24

25

26
/*---------------------------Define Local Constant---------------------------*/
27
/* 2010/04/25 MH Define the max tx power tracking tx agc power. */
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#define		ODM_TXPWRTRACK_MAX_IDX_8814A		6
29

30
/*---------------------------Define Local Constant---------------------------*/
31

32
/*3============================================================*/
33
/* 3 Tx Power Tracking
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 *3============================================================*/
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#define	REG_A_TX_AGC	0xC94
36
#define	REG_B_TX_AGC	0xE94
37
#define	REG_C_TX_AGC	0x1894
38
#define	REG_D_TX_AGC	0x1A94
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#define	TXAGC_BITMASK	(BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25))
40
#define	REG_A_BBSWING	0xC1C
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#define	REG_B_BBSWING	0xE1C
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#define	REG_C_BBSWING	0x181C
43
#define	REG_D_BBSWING	0x1A1C
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#define	BBSWING_BITMASK	0xFFE00000
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46

47
#if 0
48

49
u8 check_rf_gain_offset(
50
	struct dm_struct			*dm,
51
	enum pwrtrack_method			method,
52
	u8				rf_path
53
)
54
{
55
	s8	upper_bound = 10, lower_bound = -5;	/*4'b1010 = 10*/
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	s8	final_rf_index = 0;
57
	boolean	is_positive = false;
58
	u32	bit_mask = 0;
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	u8	final_ofdm_swing_index = 0, tx_scaling_upper_bound = 28, tx_scaling_lower_bound = 4;	/*upper bound +2dB, lower bound -10dB*/
60
	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
61

62
	if (method == MIX_MODE) {	/*normal Tx power tracking*/
63
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "is 8814 MP chip\n");
64
		bit_mask = BIT(19);
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		cali_info->absolute_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path] + cali_info->kfree_offset[rf_path];
66

67
		if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0)				/*check if RF_Index is positive or not*/
68
			is_positive = true;
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		else
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			is_positive = false;
71

72
		odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, bit_mask, is_positive);
73

74
		bit_mask = BIT(18) | BIT(17) | BIT(16) | BIT(15);
75
		final_rf_index = cali_info->absolute_ofdm_swing_idx[rf_path] / 2;		/*TxBB 1 step equal 1dB, BB swing 1step equal 0.5dB*/
76

77
	}
78

79
	if (final_rf_index > upper_bound) {		/*Upper bound = 10dB, if more htan upper bound, then move to bb swing max = +2dB*/
80
		odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, bit_mask, upper_bound);	/*set RF Reg0x55 per path*/
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82
		final_ofdm_swing_index = cali_info->default_ofdm_index + (cali_info->absolute_ofdm_swing_idx[rf_path] - (upper_bound << 1));
83

84
		if (final_ofdm_swing_index > tx_scaling_upper_bound)	/*bb swing upper bound = +2dB*/
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			final_ofdm_swing_index = tx_scaling_upper_bound;
86

87
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
88
			"******path-%d Compensate with TXBB = %d\n", rf_path, upper_bound);
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90
		return final_ofdm_swing_index;
91
	} else if (final_rf_index < lower_bound) {	/*lower bound = -5dB*/
92
		odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, bit_mask, (-1) * (lower_bound));	/*set RF Reg0x55 per path*/
93

94
		final_ofdm_swing_index = cali_info->default_ofdm_index - ((lower_bound << 1) - cali_info->absolute_ofdm_swing_idx[rf_path]);
95

96
		if (final_ofdm_swing_index < tx_scaling_lower_bound)	/*bb swing lower bound = -10dB*/
97
			final_ofdm_swing_index = tx_scaling_lower_bound;
98

99
		return final_ofdm_swing_index;
100

101
	} else {	/*normal case*/
102

103
		if (is_positive == true)
104
			odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, bit_mask, final_rf_index);	/*set RF Reg0x55 per path*/
105
		else
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			odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, bit_mask, (-1) * final_rf_index);	/*set RF Reg0x55 per path*/
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108
		final_ofdm_swing_index = cali_info->default_ofdm_index + (cali_info->absolute_ofdm_swing_idx[rf_path]) % 2;
109
		return final_ofdm_swing_index;
110
	}
111

112
	return false;
113
}
114

115
#endif
116

117
u8 get_tssivalue(
118
	struct dm_struct			*dm,
119
	enum pwrtrack_method	method,
120
	u8				rf_path
121
)
122
{
123

124
	struct _ADAPTER *adapter = dm->adapter;
125
	struct dm_rf_calibration_struct		*cali_info = &(dm->rf_calibrate_info);
126
	HAL_DATA_TYPE		*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
127

128
	s8				power_by_rate_value = 0;
129
	u8				tx_num, tssi_value = 0;
130
	u8				channel  = *dm->channel;
131
	u8				band_width  = hal_data->CurrentChannelBW;
132
	u8				tx_rate = 0xFF;
133
	u8				tx_limit = 0;
134
	u8				reg_pwr_tbl_sel = 0;
135

136
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
137
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
138
	PMGNT_INFO			mgnt_info = &(((PADAPTER)adapter)->MgntInfo);
139

140
	reg_pwr_tbl_sel = mgnt_info->RegPwrTblSel;
141
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
142
	reg_pwr_tbl_sel = adapter->registrypriv.reg_pwr_tbl_sel;
143
#endif
144
#endif
145

146
	if (*(dm->mp_mode) == true) {
147
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
148
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
149
#if (MP_DRIVER == 1)
150
		PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx);
151

152
		tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
153
#endif
154
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
155
#ifdef CONFIG_MP_INCLUDED
156
		PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
157

158
		tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
159
#endif
160
#endif
161
#endif
162
	} else {
163
		u16	rate	 = *(dm->forced_data_rate);
164

165
		if (!rate) { /*auto rate*/
166
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
167
			tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
168
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
169
			tx_rate = hw_rate_to_m_rate(dm->tx_rate);
170
#endif
171
		} else   /*force rate*/
172
			tx_rate = (u8) rate;
173
	}
174

175
	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__, tx_rate);
176
	tx_num = MgntQuery_NssTxRate(tx_rate);
177

178

179
	if (channel >= 1 && channel <= 14) {
180
		power_by_rate_value = PHY_GetTxPowerByRateOriginal(adapter, BAND_ON_2_4G, (enum rf_path) rf_path, tx_num, tx_rate);
181
		tx_limit = PHY_GetTxPowerLimitOriginal(adapter, reg_pwr_tbl_sel, BAND_ON_2_4G, (enum channel_width) band_width, RF_PATH_A, tx_rate, channel);
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183
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s power_by_rate_value=%d   tx_rate=0x%X rf_path=%d   tx_num=%d\n", __func__, power_by_rate_value, tx_rate, rf_path, tx_num);
184
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_limit=%d   reg_pwr_tbl_sel=0x%X band_width=%d   channel=%d\n", __func__, tx_limit, reg_pwr_tbl_sel, band_width, channel);
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186
		power_by_rate_value = power_by_rate_value > tx_limit ? tx_limit : power_by_rate_value;
187

188
		if (IS_CCK_RATE(tx_rate)) {
189
			switch (rf_path) {
190
			case RF_PATH_A:
191
				tssi_value = cali_info->delta_swing_tssi_table_2g_cck_a[power_by_rate_value];
192
				break;
193

194
			case RF_PATH_B:
195
				tssi_value = cali_info->delta_swing_tssi_table_2g_cck_b[power_by_rate_value];
196
				break;
197

198
			case RF_PATH_C:
199
				tssi_value = cali_info->delta_swing_tssi_table_2g_cck_c[power_by_rate_value];
200
				break;
201

202
			case RF_PATH_D:
203
				tssi_value = cali_info->delta_swing_tssi_table_2g_cck_d[power_by_rate_value];
204
				break;
205

206
			default:
207
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Call:%s Wrong path name!!!\n", __func__);
208
				break;
209
			}
210
		} else {
211
			switch (rf_path) {
212
			case RF_PATH_A:
213
				tssi_value = cali_info->delta_swing_tssi_table_2ga[power_by_rate_value];
214
				break;
215

216
			case RF_PATH_B:
217
				tssi_value = cali_info->delta_swing_tssi_table_2gb[power_by_rate_value];
218
				break;
219

220
			case RF_PATH_C:
221
				tssi_value = cali_info->delta_swing_tssi_table_2gc[power_by_rate_value];
222
				break;
223

224
			case RF_PATH_D:
225
				tssi_value = cali_info->delta_swing_tssi_table_2gd[power_by_rate_value];
226
				break;
227

228
			default:
229
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Call:%s Wrong path name!!!!\n", __func__);
230
				break;
231
			}
232
		}
233
	} else if (channel >= 36 && channel <= 64) {
234
		power_by_rate_value = PHY_GetTxPowerByRateOriginal(adapter, BAND_ON_5G, (enum rf_path) rf_path, tx_num, tx_rate);
235

236
		tx_limit = PHY_GetTxPowerLimitOriginal(adapter, reg_pwr_tbl_sel, BAND_ON_5G, (enum channel_width) band_width, RF_PATH_A, tx_rate, channel);
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238
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s power_by_rate_value=%d   tx_rate=0x%X rf_path=%d   tx_num=%d\n", __func__, power_by_rate_value, tx_rate, rf_path, tx_num);
239
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_limit=%d   reg_pwr_tbl_sel=0x%X band_width=%d   channel=%d\n", __func__, tx_limit, reg_pwr_tbl_sel, band_width, channel);
240

241
		power_by_rate_value = power_by_rate_value > tx_limit ? tx_limit : power_by_rate_value;
242

243
		switch (rf_path) {
244
		case RF_PATH_A:
245
			tssi_value = cali_info->delta_swing_tssi_table_5ga[0][power_by_rate_value];
246
			break;
247

248
		case RF_PATH_B:
249
			tssi_value = cali_info->delta_swing_tssi_table_5gb[0][power_by_rate_value];
250
			break;
251

252
		case RF_PATH_C:
253
			tssi_value = cali_info->delta_swing_tssi_table_5gc[0][power_by_rate_value];
254
			break;
255

256
		case RF_PATH_D:
257
			tssi_value = cali_info->delta_swing_tssi_table_5gd[0][power_by_rate_value];
258
			break;
259

260
		default:
261
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Call:%s Wrong path name!!!!\n", __func__);
262
			break;
263
		}
264
	} else if (channel >= 100 && channel <= 144) {
265
		power_by_rate_value = PHY_GetTxPowerByRateOriginal(adapter, BAND_ON_5G, (enum rf_path) rf_path, tx_num, tx_rate);
266

267
		tx_limit = PHY_GetTxPowerLimitOriginal(adapter, reg_pwr_tbl_sel, BAND_ON_5G, (enum channel_width) band_width, RF_PATH_A, tx_rate, channel);
268

269
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s power_by_rate_value=%d   tx_rate=0x%X rf_path=%d   tx_num=%d\n", __func__, power_by_rate_value, tx_rate, rf_path, tx_num);
270
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_limit=%d   reg_pwr_tbl_sel=0x%X band_width=%d   channel=%d\n", __func__, tx_limit, reg_pwr_tbl_sel, band_width, channel);
271

272
		power_by_rate_value = power_by_rate_value > tx_limit ? tx_limit : power_by_rate_value;
273

274
		switch (rf_path) {
275
		case RF_PATH_A:
276
			tssi_value = cali_info->delta_swing_tssi_table_5ga[1][power_by_rate_value];
277
			break;
278

279
		case RF_PATH_B:
280
			tssi_value = cali_info->delta_swing_tssi_table_5gb[1][power_by_rate_value];
281
			break;
282

283
		case RF_PATH_C:
284
			tssi_value = cali_info->delta_swing_tssi_table_5gc[1][power_by_rate_value];
285
			break;
286

287
		case RF_PATH_D:
288
			tssi_value = cali_info->delta_swing_tssi_table_5gd[1][power_by_rate_value];
289
			break;
290

291
		default:
292
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Call:%s Wrong path name!!!!\n", __func__);
293
			break;
294
		}
295
	} else if (channel >= 149 && channel <= 173) {
296
		power_by_rate_value = PHY_GetTxPowerByRateOriginal(adapter, BAND_ON_5G, (enum rf_path) rf_path, tx_num, tx_rate);
297

298
		tx_limit = PHY_GetTxPowerLimitOriginal(adapter, reg_pwr_tbl_sel, BAND_ON_5G, (enum channel_width) band_width, RF_PATH_A, tx_rate, channel);
299

300
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s power_by_rate_value=%d   tx_rate=0x%X rf_path=%d   tx_num=%d\n", __func__, power_by_rate_value, tx_rate, rf_path, tx_num);
301
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_limit=%d   reg_pwr_tbl_sel=0x%X band_width=%d   channel=%d\n", __func__, tx_limit, reg_pwr_tbl_sel, band_width, channel);
302

303
		power_by_rate_value = power_by_rate_value > tx_limit ? tx_limit : power_by_rate_value;
304

305
		switch (rf_path) {
306
		case RF_PATH_A:
307
			tssi_value = cali_info->delta_swing_tssi_table_5ga[2][power_by_rate_value];
308
			break;
309

310
		case RF_PATH_B:
311
			tssi_value = cali_info->delta_swing_tssi_table_5gb[2][power_by_rate_value];
312
			break;
313

314
		case RF_PATH_C:
315
			tssi_value = cali_info->delta_swing_tssi_table_5gc[2][power_by_rate_value];
316
			break;
317

318
		case RF_PATH_D:
319
			tssi_value = cali_info->delta_swing_tssi_table_5gd[2][power_by_rate_value];
320
			break;
321

322
		default:
323
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Call:%s Wrong path name!!!!\n", __func__);
324
			break;
325
		}
326
	}
327

328
	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s index=%d   tssi_value=%d\n", __func__, power_by_rate_value, tssi_value);
329

330
	return tssi_value;
331
}
332

333
boolean get_tssi_mode_tx_agc_bb_swing_offset(
334
	struct dm_struct			*dm,
335
	enum pwrtrack_method	method,
336
	u8					rf_path,
337
	u32					offset_vaule,
338
	u8					tx_power_index_offest
339
)
340
{
341
	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
342

343
	u8		bb_swing_upper_bound = cali_info->default_ofdm_index + 10;
344
	u8		bb_swing_lower_bound = 0;
345
	u8		tx_agc_index = (u8) cali_info->absolute_ofdm_swing_idx[rf_path];
346
	u8		tx_bb_swing_index = (u8) cali_info->bb_swing_idx_ofdm[rf_path];
347

348
	if (tx_power_index_offest > 0XF)
349
		tx_power_index_offest = 0XF;
350

351
	if (tx_agc_index == 0 && tx_bb_swing_index == cali_info->default_ofdm_index) {
352
		if ((offset_vaule & 0X20) >> 5 == 0) {
353
			offset_vaule = offset_vaule & 0X1F;
354

355
			if (offset_vaule > tx_power_index_offest) {
356
				tx_agc_index = tx_power_index_offest;
357
				tx_bb_swing_index = tx_bb_swing_index + (u8) offset_vaule - tx_power_index_offest;
358

359
				if (tx_bb_swing_index > bb_swing_upper_bound)
360
					tx_bb_swing_index = bb_swing_upper_bound;
361

362
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"tx_agc_index(0) tx_bb_swing_index(18) +++ ( offset_vaule > 0XF) offset_vaule = 0X%X	TXAGCIndex = 0X%X	tx_bb_swing_index = %d\n", offset_vaule, tx_agc_index, tx_bb_swing_index);
363
			} else {
364
				tx_agc_index = (u8) offset_vaule;
365
				tx_bb_swing_index = cali_info->default_ofdm_index;
366

367
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"tx_agc_index(0) tx_bb_swing_index(18) +++ ( offset_vaule <= 0XF) offset_vaule = 0X%X	TXAGCIndex = 0X%X	tx_bb_swing_index = %d\n", offset_vaule, tx_agc_index, tx_bb_swing_index);
368
			}
369
		} else {
370
			tx_agc_index = 0;
371
			offset_vaule = ((~offset_vaule) + 1) & 0X1F;
372

373
			if (tx_bb_swing_index >= (u8) offset_vaule)
374
				tx_bb_swing_index = tx_bb_swing_index - (u8) offset_vaule;
375
			else
376
				tx_bb_swing_index = bb_swing_lower_bound;
377

378
			if (tx_bb_swing_index <= bb_swing_lower_bound)
379
				tx_bb_swing_index = bb_swing_lower_bound;
380

381
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"tx_agc_index(0) tx_bb_swing_index(18) --- offset_vaule = 0X%X   TXAGCIndex = 0X%X   tx_bb_swing_index = %d\n", offset_vaule, tx_agc_index, tx_bb_swing_index);
382
		}
383

384
	} else if (tx_agc_index > 0 && tx_bb_swing_index == cali_info->default_ofdm_index) {
385
		if ((offset_vaule & 0X20) >> 5 == 0) {
386
			if (offset_vaule > tx_power_index_offest) {
387
				tx_agc_index = tx_power_index_offest;
388
				tx_bb_swing_index = tx_bb_swing_index + (u8) offset_vaule - tx_power_index_offest;
389

390
				if (tx_bb_swing_index > bb_swing_upper_bound)
391
					tx_bb_swing_index = bb_swing_upper_bound;
392
			} else
393
				tx_agc_index = (u8) offset_vaule;
394

395
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"tx_agc_index > 0 tx_bb_swing_index(18) +++ offset_vaule = 0X%X   TXAGCIndex = 0X%X   tx_bb_swing_index = %d\n", offset_vaule, tx_agc_index, tx_bb_swing_index);
396
		} else {
397
			tx_agc_index = 0;
398
			offset_vaule = ((~offset_vaule) + 1) & 0X1F;
399

400
			if (tx_bb_swing_index >= (u8) offset_vaule)
401
				tx_bb_swing_index = tx_bb_swing_index - (u8) offset_vaule;
402
			else
403
				tx_bb_swing_index = bb_swing_lower_bound;
404

405
			if (tx_bb_swing_index <= bb_swing_lower_bound)
406
				tx_bb_swing_index = bb_swing_lower_bound;
407

408
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"tx_agc_index > 0 tx_bb_swing_index(18)  --- offset_vaule = 0X%X	TXAGCIndex = 0X%X	tx_bb_swing_index = %d\n", offset_vaule, tx_agc_index, tx_bb_swing_index);
409
		}
410

411

412
	} else if (tx_agc_index > 0 && tx_bb_swing_index > cali_info->default_ofdm_index) {
413
		if ((offset_vaule & 0X20) >> 5 == 0) {
414
			tx_agc_index = tx_power_index_offest;
415
			tx_bb_swing_index = tx_bb_swing_index + (u8) offset_vaule - tx_power_index_offest;
416

417
			if (tx_bb_swing_index > bb_swing_upper_bound)
418
				tx_bb_swing_index = bb_swing_upper_bound;
419

420
			if (tx_bb_swing_index < cali_info->default_ofdm_index) {
421
				tx_agc_index = tx_power_index_offest - (cali_info->default_ofdm_index - tx_bb_swing_index);
422
				tx_bb_swing_index = cali_info->default_ofdm_index;
423
			}
424
		} else {
425
			tx_agc_index = 0;
426
			offset_vaule = ((~offset_vaule) + 1) & 0X1F;
427

428
			if (tx_bb_swing_index >= (u8) offset_vaule)
429
				tx_bb_swing_index = cali_info->default_ofdm_index - (u8) offset_vaule;
430
			else
431
				tx_bb_swing_index = bb_swing_lower_bound;
432

433
			if (tx_bb_swing_index <= bb_swing_lower_bound)
434
				tx_bb_swing_index = bb_swing_lower_bound;
435
		}
436

437
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"tx_agc_index>0 tx_bb_swing_index>18 --- offset_vaule = 0X%X	 TXAGCIndex = 0X%X	 tx_bb_swing_index = %d	 offset_vaule=%d\n", offset_vaule, tx_agc_index, tx_bb_swing_index, offset_vaule - tx_power_index_offest);
438

439
	} else if (tx_agc_index == 0 && tx_bb_swing_index < cali_info->default_ofdm_index) {
440
		if ((offset_vaule & 0X20) >> 5 == 1) {
441
			offset_vaule = ((~offset_vaule) + 1) & 0X1F;
442

443
			if (tx_bb_swing_index >= (u8) offset_vaule)
444
				tx_bb_swing_index = tx_bb_swing_index - (u8) offset_vaule;
445
			else
446
				tx_bb_swing_index = bb_swing_lower_bound;
447
		} else {
448
			offset_vaule = (offset_vaule & 0x1F);
449
			tx_bb_swing_index = tx_bb_swing_index + (u8) offset_vaule;
450

451
			if (tx_bb_swing_index > cali_info->default_ofdm_index) {
452
				tx_agc_index = tx_bb_swing_index - cali_info->default_ofdm_index;
453
				tx_bb_swing_index = cali_info->default_ofdm_index;
454

455
				if (tx_agc_index > tx_power_index_offest) {
456
					tx_bb_swing_index = cali_info->default_ofdm_index + (u8)(tx_agc_index) - tx_power_index_offest;
457
					tx_agc_index = tx_power_index_offest;
458

459
					if (tx_bb_swing_index  > bb_swing_upper_bound)
460
						tx_bb_swing_index = bb_swing_upper_bound;
461
				}
462
			}
463
		}
464

465
		if (tx_bb_swing_index <= bb_swing_lower_bound) {
466
			tx_bb_swing_index = bb_swing_lower_bound;
467
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Call %s  Path_%d BBSwing Lower Bound\n", __func__, rf_path);
468
		}
469

470
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"tx_agc_index(0) tx_bb_swing_index < 18 offset_vaule = 0X%X	 TXAGCIndex = 0X%X	 tx_bb_swing_index = %d\n", offset_vaule, tx_agc_index, tx_bb_swing_index);
471

472
	}
473

474
	if ((tx_agc_index == cali_info->absolute_ofdm_swing_idx[rf_path]) && (tx_bb_swing_index == cali_info->bb_swing_idx_ofdm[rf_path]))
475
		return false;
476

477
	else {
478
		cali_info->absolute_ofdm_swing_idx[rf_path] = tx_agc_index;
479
		cali_info->bb_swing_idx_ofdm[rf_path] = tx_bb_swing_index;
480
		return true;
481
	}
482

483
}
484

485

486
void set_tx_agc_bb_swing_offset(
487
	struct dm_struct			*dm,
488
	enum pwrtrack_method	method,
489
	u8				rf_path
490
)
491
{
492

493
	struct _ADAPTER *adapter = dm->adapter;
494
	HAL_DATA_TYPE		*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
495

496
	u8				tx_rate = 0xFF;
497
	u8				channel  = *dm->channel;
498
	u8				band_width  = hal_data->CurrentChannelBW;
499
	u32				tx_path  = hal_data->AntennaTxPath;
500

501
	u8				tssi_value = 0;
502
	u8				tx_power_index = 0;
503
	u8				tx_power_index_offest = 0;
504
	u32				offset_vaule = 0;
505
	u32				tssi_function = 0;
506
	u32				txbb_swing = 0;
507
	u8				tx_bb_swing_index = 0;
508
	u32				tx_agc_index = 0;
509
	u32				wait_tx_agc_offset_timer = 0;
510
	u8				i = 0;
511
	boolean			rtn = false;
512

513
	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
514

515
	if (*(dm->mp_mode) == true) {
516
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
517
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
518
#if (MP_DRIVER == 1)
519
		PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx);
520

521
		tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
522
#endif
523
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
524
#ifdef CONFIG_MP_INCLUDED
525
		PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
526

527
		tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
528
#endif
529
#endif
530
#endif
531
	} else {
532
		u16	rate	 = *(dm->forced_data_rate);
533

534
		if (!rate) { /*auto rate*/
535
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
536
			tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
537
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
538
			tx_rate = hw_rate_to_m_rate(dm->tx_rate);
539
#endif
540
		} else   /*force rate*/
541
			tx_rate = (u8) rate;
542
	}
543

544
	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__, tx_rate);
545

546
	if (method == TSSI_MODE) {
547
		switch (rf_path) {
548
		case RF_PATH_A:
549
			/*Disable path B TSSI Circuit*/
550
			odm_set_rf_reg(dm, RF_PATH_B, RF_0x65, BIT(10), 0);
551
			/*Enable path A TSSI Circuit*/
552
			odm_set_rf_reg(dm, RF_PATH_A, RF_0x65, BIT(10), 1);
553

554
			/*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/
555
			tssi_value = get_tssivalue(dm, TSSI_MODE, (enum rf_path) rf_path);
556

557
			odm_set_rf_reg(dm, (enum rf_path) rf_path, RF_0x65, BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15), tssi_value);
558

559
			/*Write BB 0xC8C for setting Max. packet (30) of tracking power and the initial value of TXAGC*/
560
			odm_set_bb_reg(dm, R_0xc8c, BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14), 30);
561

562
			odm_set_bb_reg(dm, R_0xc8c, BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8), 0);
563

564
			/*Write BB TXAGC Initial Power index for EEPROM*/
565
			tx_power_index = PHY_GetTxPowerIndex_8814A(adapter, (enum rf_path) rf_path, tx_rate, (enum channel_width) band_width, channel);
566
			odm_set_bb_reg(dm, R_0xc8c, BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), tx_power_index);
567

568
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Call %s   tx_power_index=%d    rf_path=%d   tx_rate=%d   band_width=%d   channel=%d   0x65[19:15]=0X%X   0x65[11:10]=0X%X\n",
569
				      __func__,
570
				odm_get_bb_reg(dm, R_0xc8c, BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)),
571
				      rf_path, tx_rate, band_width, channel,
572
				odm_get_rf_reg(dm, (enum rf_path) rf_path, RF_0x65, BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15)),
573
				odm_get_rf_reg(dm, (enum rf_path) rf_path, RF_0x65, BIT(11) | BIT(10))
574
				     );
575

576
			/*Disable BB TSSI Power Tracking*/
577
			odm_set_bb_reg(dm, R_0xc8c, BIT(7), 0);
578
			/*Enable path A TSSI Circuit*/
579
			odm_set_rf_reg(dm, RF_PATH_A, RF_0x65, BIT(10), 1);
580
			/*Enable BB TSSI Power Tracking*/
581
			odm_set_bb_reg(dm, R_0xc8c, BIT(7), 1);
582

583
			/*			delay_us(500);*/
584
			wait_tx_agc_offset_timer = 0;
585

586
			while ((odm_get_bb_reg(dm, R_0xd2c, BIT(30)) != 1) && ((tx_path & 8) == 8)) {
587
				wait_tx_agc_offset_timer++;
588

589
				if (wait_tx_agc_offset_timer >= 1000)
590
					break;
591
			}
592

593
			/*Read the offset value at BB Reg.*/
594
			offset_vaule = odm_get_bb_reg(dm, R_0xd2c, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24));
595

596
			tssi_function = odm_get_bb_reg(dm, R_0xd2c, BIT(30));
597

598
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Call %s  0XD2C	 tssi_function[30]=0X%X offset_vaule[29:24]=0X%X	rf_path=%d\n", __func__, tssi_function, offset_vaule, rf_path);
599

600
			/*Disable BB TSSI Power Tracking*/
601
			odm_set_bb_reg(dm, R_0xc8c, BIT(7), 0);
602
			/*Disable path A TSSI Circuit*/
603
			odm_set_rf_reg(dm, RF_PATH_A, RF_0x65, BIT(10), 0);
604

605
			if (tssi_function == 1) {
606
				txbb_swing = odm_get_bb_reg(dm, REG_A_BBSWING, BBSWING_BITMASK);
607

608
				for (i = 0; i <= 36; i++) {
609
					if (txbb_swing == tx_scaling_table_jaguar[i]) {
610
						cali_info->bb_swing_idx_ofdm[rf_path] = i;
611
						RF_DBG(dm, DBG_RF_TX_PWR_TRACK," PathA txbb_swing = %d txbb_swing=0X%X\n", tx_bb_swing_index, txbb_swing);
612
						break;
613

614
					} else
615
						cali_info->bb_swing_idx_ofdm[rf_path] = cali_info->default_ofdm_index;
616
				}
617

618
				cali_info->absolute_ofdm_swing_idx[rf_path] = (u8) odm_get_bb_reg(dm, REG_A_TX_AGC, TXAGC_BITMASK);
619

620

621
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TXAGCIndex = 0X%X  tx_bb_swing_index = %d\n", cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->bb_swing_idx_ofdm[rf_path]);
622

623
				tx_power_index_offest = 63 - tx_power_index;
624

625
				rtn = get_tssi_mode_tx_agc_bb_swing_offset(dm, method, (enum rf_path) rf_path, offset_vaule, tx_power_index_offest);
626

627
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," tx_agc_index = %d   tx_bb_swing_index = %d rtn=%d\n", cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->bb_swing_idx_ofdm[rf_path], rtn);
628

629
				if (rtn == true) {
630
					odm_set_bb_reg(dm, REG_A_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
631
					odm_set_bb_reg(dm, REG_A_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);	/*set BBswing*/
632
				} else
633
					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TXAGC And BB Swing are the same path=%d\n", rf_path);
634

635
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," ========================================================\n");
636

637

638
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"  OffsetValue(0XD2C)=0X%X   TXAGC(REG_A_TX_AGC)=0X%X   0XC1C(PathC BBSwing)(%d)=0X%X\n",
639
					odm_get_bb_reg(dm, R_0xd2c, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24)),
640
					odm_get_bb_reg(dm, REG_A_TX_AGC, TXAGC_BITMASK),
641
					cali_info->bb_swing_idx_ofdm[rf_path],
642
					odm_get_bb_reg(dm, REG_A_BBSWING, BBSWING_BITMASK)
643
					     );
644

645
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," 0X55[13:9]=0X%X	 0X56=0X%X\n",
646
					odm_get_rf_reg(dm, (enum rf_path) rf_path, 0X55, BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9)),
647
					odm_get_rf_reg(dm, (enum rf_path) rf_path, 0X56, 0XFFFFFFFF)
648
					     );
649

650
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," ========================================================\n");
651

652
			} else
653
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," TSSI does not Calculate Finish\n");
654

655
			break;
656

657
		case RF_PATH_B:
658
			/*Disable path A TSSI Circuit*/
659
			odm_set_rf_reg(dm, RF_PATH_A, RF_0x65, BIT(10), 0);
660
			/*Enable path B TSSI Circuit*/
661
			odm_set_rf_reg(dm, RF_PATH_B, RF_0x65, BIT(10), 1);
662

663
			/*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/
664
			tssi_value = get_tssivalue(dm, TSSI_MODE, (enum rf_path) rf_path);
665

666
			odm_set_rf_reg(dm, (enum rf_path) rf_path, RF_0x65, BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15), tssi_value);
667

668
			/*Write BB 0xE8C for setting Max. packet (30) of tracking power and the initial value of TXAGC*/
669
			odm_set_bb_reg(dm, R_0xe8c, BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14), 30);
670

671
			odm_set_bb_reg(dm, R_0xe8c, BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8), 0);
672

673
			/*Write BB TXAGC Initial Power index for EEPROM*/
674
			tx_power_index = PHY_GetTxPowerIndex_8814A(adapter, (enum rf_path) rf_path, tx_rate, (enum channel_width) band_width, channel);
675
			odm_set_bb_reg(dm, R_0xe8c, BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), tx_power_index);
676

677
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Call %s   tx_power_index=%d    rf_path=%d   tx_rate=%d   band_width=%d   channel=%d   0x65[19:15]=0X%X   0x65[11:10]=0X%X\n",
678
				      __func__,
679
				odm_get_bb_reg(dm, R_0xe8c, BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)),
680
				      rf_path, tx_rate, band_width, channel,
681
				odm_get_rf_reg(dm, (enum rf_path) rf_path, RF_0x65, BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15)),
682
				odm_get_rf_reg(dm, (enum rf_path) rf_path, RF_0x65, BIT(11) | BIT(10))
683
				     );
684

685
			/*Disable BB TSSI Power Tracking*/
686
			odm_set_bb_reg(dm, R_0xe8c, BIT(7), 0);
687
			/*Enable path B TSSI Circuit*/
688
			odm_set_rf_reg(dm, RF_PATH_B, RF_0x65, BIT(10), 1);
689
			/*Enable BB TSSI Power Tracking*/
690
			odm_set_bb_reg(dm, R_0xe8c, BIT(7), 1);
691

692
			/*				delay_us(500);*/
693
			wait_tx_agc_offset_timer = 0;
694

695
			while ((odm_get_bb_reg(dm, R_0xd6c, BIT(30)) != 1) && ((tx_path & 4) == 4)) {
696
				wait_tx_agc_offset_timer++;
697

698
				if (wait_tx_agc_offset_timer >= 1000)
699
					break;
700
			}
701

702
			/*Read the offset value at BB Reg.*/
703
			offset_vaule = odm_get_bb_reg(dm, R_0xd6c, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24));
704

705
			tssi_function = odm_get_bb_reg(dm, R_0xd6c, BIT(30));
706

707
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Call %s  0XD6C	 tssi_function[30]=0X%X offset_vaule[29:24]=0X%X	rf_path=%d\n", __func__, tssi_function, offset_vaule, rf_path);
708

709
			/*Disable BB TSSI Power Tracking*/
710
			odm_set_bb_reg(dm, R_0xe8c, BIT(7), 0);
711
			/*Disable path B TSSI Circuit*/
712
			odm_set_rf_reg(dm, RF_PATH_B, RF_0x65, BIT(10), 0);
713

714
			if (tssi_function == 1) {
715
				txbb_swing = odm_get_bb_reg(dm, REG_B_BBSWING, BBSWING_BITMASK);
716

717
				for (i = 0; i <= 36; i++) {
718
					if (txbb_swing == tx_scaling_table_jaguar[i]) {
719
						cali_info->bb_swing_idx_ofdm[rf_path] = i;
720
						RF_DBG(dm, DBG_RF_TX_PWR_TRACK," PathB txbb_swing = %d txbb_swing=0X%X\n", tx_bb_swing_index, txbb_swing);
721
						break;
722

723
					} else
724
						cali_info->bb_swing_idx_ofdm[rf_path] = cali_info->default_ofdm_index;
725
				}
726

727
				cali_info->absolute_ofdm_swing_idx[rf_path] = (u8) odm_get_bb_reg(dm, REG_B_TX_AGC, TXAGC_BITMASK);
728

729
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TXAGCIndex = 0X%X  tx_bb_swing_index = %d\n", cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->bb_swing_idx_ofdm[rf_path]);
730

731
				tx_power_index_offest = 63 - tx_power_index;
732

733
				rtn = get_tssi_mode_tx_agc_bb_swing_offset(dm, method, (enum rf_path) rf_path, offset_vaule, tx_power_index_offest);
734

735
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," tx_agc_index = %d   tx_bb_swing_index = %d rtn=%d\n", cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->bb_swing_idx_ofdm[rf_path], rtn);
736

737
				if (rtn == true) {
738
					odm_set_bb_reg(dm, REG_B_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
739
					odm_set_bb_reg(dm, REG_B_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);	/*set BBswing*/
740
				} else
741
					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TXAGC And BB Swing are the same path=%d\n", rf_path);
742

743
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," ========================================================\n");
744

745

746
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," OffsetValue(0XD6C)=0X%X   TXAGC(REG_B_TX_AGC)=0X%X   0XE1C(PathB BBSwing)(%d)=0X%X\n",
747
					odm_get_bb_reg(dm, R_0xd6c, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24)),
748
					odm_get_bb_reg(dm, REG_B_TX_AGC, TXAGC_BITMASK),
749
					cali_info->bb_swing_idx_ofdm[rf_path],
750
					odm_get_bb_reg(dm, REG_B_BBSWING, BBSWING_BITMASK)
751
					     );
752

753
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," 0X55[13:9]=0X%X	 0X56=0X%X\n",
754
					odm_get_rf_reg(dm, (enum rf_path) rf_path, 0X55, BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9)),
755
					odm_get_rf_reg(dm, (enum rf_path) rf_path, 0X56, 0XFFFFFFFF)
756
					     );
757

758
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," ========================================================\n");
759

760
			} else
761
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," TSSI does not Calculate Finish\n");
762

763
			break;
764

765
		case RF_PATH_C:
766
			/*Disable path D TSSI Circuit*/
767
			odm_set_rf_reg(dm, RF_PATH_D, RF_0x65, BIT(10), 0);
768
			/*Enable path C TSSI Circuit*/
769
			odm_set_rf_reg(dm, RF_PATH_C, RF_0x65, BIT(10), 1);
770

771
			/*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/
772
			tssi_value = get_tssivalue(dm, TSSI_MODE, (enum rf_path) rf_path);
773

774
			odm_set_rf_reg(dm, (enum rf_path) rf_path, RF_0x65, BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15), tssi_value);
775

776
			/*Write BB 0x188C for setting Max. packet (30) of tracking power and the initial value of TXAGC*/
777
			odm_set_bb_reg(dm, R_0x188c, BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14), 30);
778

779
			odm_set_bb_reg(dm, R_0x188c, BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8), 0);
780

781
			/*Write BB TXAGC Initial Power index for EEPROM*/
782
			tx_power_index = PHY_GetTxPowerIndex_8814A(adapter, (enum rf_path) rf_path, tx_rate, (enum channel_width) band_width, channel);
783
			odm_set_bb_reg(dm, R_0x188c, BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), tx_power_index);
784

785
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Call %s   tx_power_index=%d    rf_path=%d   tx_rate=%d   band_width=%d   channel=%d   0x65[19:15]=0X%X   0x65[11:10]=0X%X\n",
786
				      __func__,
787
				odm_get_bb_reg(dm, R_0x188c, BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)),
788
				      rf_path, tx_rate, band_width, channel,
789
				odm_get_rf_reg(dm, (enum rf_path) rf_path, RF_0x65, BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15)),
790
				odm_get_rf_reg(dm, (enum rf_path) rf_path, RF_0x65, BIT(11) | BIT(10))
791
				     );
792

793
			/*Disable BB TSSI Power Tracking*/
794
			odm_set_bb_reg(dm, R_0x188c, BIT(7), 0);
795
			/*Enable path C TSSI Circuit*/
796
			odm_set_rf_reg(dm, RF_PATH_C, RF_0x65, BIT(10), 1);
797
			/*Enable BB TSSI Power Tracking*/
798
			odm_set_bb_reg(dm, R_0x188c, BIT(7), 1);
799

800
			/*				delay_us(500);*/
801
			wait_tx_agc_offset_timer = 0;
802

803
			while ((odm_get_bb_reg(dm, R_0xdac, BIT(30)) != 1) && ((tx_path & 2) == 2)) {
804
				wait_tx_agc_offset_timer++;
805

806
				if (wait_tx_agc_offset_timer >= 1000)
807
					break;
808
			}
809

810
			/*Read the offset value at BB Reg.*/
811
			offset_vaule = odm_get_bb_reg(dm, R_0xdac, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24));
812

813
			tssi_function = odm_get_bb_reg(dm, R_0xdac, BIT(30));
814

815
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Call %s  0XDAC	 tssi_function[30]=0X%X offset_vaule[29:24]=0X%X	rf_path=%d\n", __func__, tssi_function, offset_vaule, rf_path);
816

817
			/*Disable BB TSSI Power Tracking*/
818
			odm_set_bb_reg(dm, R_0x188c, BIT(7), 0);
819
			/*Disable path C TSSI Circuit*/
820
			odm_set_rf_reg(dm, RF_PATH_C, RF_0x65, BIT(10), 0);
821

822
			if (tssi_function == 1) {
823
				txbb_swing = odm_get_bb_reg(dm, REG_C_BBSWING, BBSWING_BITMASK);
824

825
				for (i = 0; i <= 36; i++) {
826
					if (txbb_swing == tx_scaling_table_jaguar[i]) {
827
						cali_info->bb_swing_idx_ofdm[rf_path] = i;
828
						RF_DBG(dm, DBG_RF_TX_PWR_TRACK," PathC txbb_swing = %d txbb_swing=0X%X\n", tx_bb_swing_index, txbb_swing);
829
						break;
830

831
					} else
832
						cali_info->bb_swing_idx_ofdm[rf_path] = cali_info->default_ofdm_index;
833
				}
834

835
				cali_info->absolute_ofdm_swing_idx[rf_path] = (u8) odm_get_bb_reg(dm, REG_C_TX_AGC, TXAGC_BITMASK);
836

837
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TXAGCIndex = 0X%X  tx_bb_swing_index = %d\n", cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->bb_swing_idx_ofdm[rf_path]);
838

839
				tx_power_index_offest = 63 - tx_power_index;
840

841
				rtn = get_tssi_mode_tx_agc_bb_swing_offset(dm, method, (enum rf_path) rf_path, offset_vaule, tx_power_index_offest);
842

843
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," tx_agc_index = %d   tx_bb_swing_index = %d rtn=%d\n", cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->bb_swing_idx_ofdm[rf_path], rtn);
844

845
				if (rtn == true) {
846
					odm_set_bb_reg(dm, REG_C_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
847
					odm_set_bb_reg(dm, REG_C_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);	/*set BBswing*/
848
				} else
849
					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TXAGC And BB Swing are the same path=%d\n", rf_path);
850

851
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," ========================================================\n");
852

853

854
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," OffsetValue(0XDAC)=0X%X   TXAGC(REG_C_TX_AGC)=0X%X   0X181C(PathC BBSwing)(%d)=0X%X\n",
855
					odm_get_bb_reg(dm, R_0xdac, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24)),
856
					odm_get_bb_reg(dm, REG_C_TX_AGC, TXAGC_BITMASK),
857
					cali_info->bb_swing_idx_ofdm[rf_path],
858
					odm_get_bb_reg(dm, REG_C_BBSWING, BBSWING_BITMASK)
859
					     );
860

861
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," 0X55[13:9]=0X%X	 0X56=0X%X\n",
862
					odm_get_rf_reg(dm, (enum rf_path) rf_path, 0X55, BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9)),
863
					odm_get_rf_reg(dm, (enum rf_path) rf_path, 0X56, 0XFFFFFFFF)
864
					     );
865

866
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," ========================================================\n");
867

868
			} else
869
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," TSSI does not Calculate Finish\n");
870

871
			break;
872

873

874
		case RF_PATH_D:
875
			/*Disable path C TSSI Circuit*/
876
			odm_set_rf_reg(dm, RF_PATH_C, RF_0x65, BIT(10), 0);
877
			/*Enable path D TSSI Circuit*/
878
			odm_set_rf_reg(dm, RF_PATH_D, RF_0x65, BIT(10), 1);
879

880
			/*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/
881
			tssi_value = get_tssivalue(dm, TSSI_MODE, (enum rf_path) rf_path);
882

883
			odm_set_rf_reg(dm, (enum rf_path) rf_path, RF_0x65, BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15), tssi_value);
884

885
			/*Write BB 0x1A8C for setting Max. packet (30) of tracking power and the initial value of TXAGC*/
886
			odm_set_bb_reg(dm, R_0x1a8c, BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14), 30);
887

888
			odm_set_bb_reg(dm, R_0x1a8c, BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8), 0);
889

890
			/*Write BB TXAGC Initial Power index for EEPROM*/
891
			tx_power_index = PHY_GetTxPowerIndex_8814A(adapter, (enum rf_path) rf_path, tx_rate, (enum channel_width) band_width, channel);
892
			odm_set_bb_reg(dm, R_0x1a8c, BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), tx_power_index);
893

894
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Call %s   tx_power_index=%d	  rf_path=%d   tx_rate=%d   band_width=%d	 channel=%d   0x65[19:15]=0X%X	 0x65[11:10]=0X%X\n",
895
				      __func__,
896
				odm_get_bb_reg(dm, R_0x1a8c, BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)),
897
				      rf_path, tx_rate, band_width, channel,
898
				odm_get_rf_reg(dm, (enum rf_path) rf_path, RF_0x65, BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15)),
899
				odm_get_rf_reg(dm, (enum rf_path) rf_path, RF_0x65, BIT(11) | BIT(10))
900
				     );
901

902
			/*Disable BB TSSI Power Tracking*/
903
			odm_set_bb_reg(dm, R_0x1a8c, BIT(7), 0);
904
			/*Enable path D TSSI Circuit*/
905
			odm_set_rf_reg(dm, RF_PATH_D, RF_0x65, BIT(10), 1);
906
			/*Enable BB TSSI Power Tracking*/
907
			odm_set_bb_reg(dm, R_0x1a8c, BIT(7), 1);
908

909
			/*				delay_us(500);*/
910
			wait_tx_agc_offset_timer = 0;
911

912
			while ((odm_get_bb_reg(dm, R_0xdec, BIT(30)) != 1) && ((tx_path & 1) == 1)) {
913
				wait_tx_agc_offset_timer++;
914

915
				if (wait_tx_agc_offset_timer >= 1000)
916
					break;
917
			}
918

919
			/*Read the offset value at BB Reg.*/
920
			offset_vaule = odm_get_bb_reg(dm, R_0xdec, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24));
921

922
			tssi_function = odm_get_bb_reg(dm, R_0xdec, BIT(30));
923

924
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Call %s  0XDEC  tssi_function[30]=0X%X offset_vaule[29:24]=0X%X	rf_path=%d\n", __func__, tssi_function, offset_vaule, rf_path);
925

926
			/*Disable BB TSSI Power Tracking*/
927
			odm_set_bb_reg(dm, R_0x1a8c, BIT(7), 0);
928
			/*Disable path D TSSI Circuit*/
929
			odm_set_rf_reg(dm, RF_PATH_D, RF_0x65, BIT(10), 0);
930

931
			if (tssi_function == 1) {
932
				txbb_swing = odm_get_bb_reg(dm, REG_D_BBSWING, BBSWING_BITMASK);
933

934
				for (i = 0; i <= 36; i++) {
935
					if (txbb_swing == tx_scaling_table_jaguar[i]) {
936
						cali_info->bb_swing_idx_ofdm[rf_path] = i;
937
						RF_DBG(dm, DBG_RF_TX_PWR_TRACK," PathD txbb_swing = %d txbb_swing=0X%X\n", tx_bb_swing_index, txbb_swing);
938
						break;
939

940
					} else
941
						cali_info->bb_swing_idx_ofdm[rf_path] = cali_info->default_ofdm_index;
942
				}
943

944
				cali_info->absolute_ofdm_swing_idx[rf_path] = (u8) odm_get_bb_reg(dm, REG_D_TX_AGC, TXAGC_BITMASK);
945

946
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TXAGCIndex = 0X%X	tx_bb_swing_index = %d\n", cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->bb_swing_idx_ofdm[rf_path]);
947

948
				tx_power_index_offest = 63 - tx_power_index;
949

950
				rtn = get_tssi_mode_tx_agc_bb_swing_offset(dm, method, (enum rf_path) rf_path, offset_vaule, tx_power_index_offest);
951

952
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," tx_agc_index = %d   tx_bb_swing_index = %d rtn=%d\n", cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->bb_swing_idx_ofdm[rf_path], rtn);
953

954
				if (rtn == true) {
955
					odm_set_bb_reg(dm, REG_D_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
956
					odm_set_bb_reg(dm, REG_D_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);	/*set BBswing*/
957
				} else
958
					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TXAGC And BB Swing are the same path=%d\n", rf_path);
959

960
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," ========================================================\n");
961

962

963
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," OffsetValue(0XDEC)=0X%X	TXAGC(REG_D_TX_AGC)=0X%X	 0X1A1C(PathD BBSwing)(%d)=0X%X\n",
964
					odm_get_bb_reg(dm, R_0xdec, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24)),
965
					odm_get_bb_reg(dm, REG_D_TX_AGC, TXAGC_BITMASK),
966
					cali_info->bb_swing_idx_ofdm[rf_path],
967
					odm_get_bb_reg(dm, REG_D_BBSWING, BBSWING_BITMASK)
968
					     );
969

970
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," 0X55[13:9]=0X%X	 0X56=0X%X\n",
971
					odm_get_rf_reg(dm, (enum rf_path) rf_path, 0X55, BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9)),
972
					odm_get_rf_reg(dm, (enum rf_path) rf_path, 0X56, 0XFFFFFFFF)
973
					     );
974

975
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," ========================================================\n");
976

977
			} else
978
				RF_DBG(dm, DBG_RF_TX_PWR_TRACK," TSSI does not Calculate Finish\n");
979

980
			break;
981

982

983
		default:
984
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Wrong path name!!!!\n");
985

986
			break;
987
		}
988
	}
989

990
}
991

992
boolean get_mix_mode_tx_agc_bb_swing_offset(
993
	struct dm_struct			*dm,
994
	enum pwrtrack_method	method,
995
	u8					rf_path,
996
	u8					tx_power_index_offest
997
)
998
{
999
	struct dm_rf_calibration_struct		*cali_info = &(dm->rf_calibrate_info);
1000

1001
	u8	bb_swing_upper_bound = cali_info->default_ofdm_index + 10;
1002
	u8	bb_swing_lower_bound = 0;
1003

1004
	s8	tx_agc_index = 0;
1005
	u8	tx_bb_swing_index = cali_info->default_ofdm_index;
1006

1007
	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Path_%d cali_info->absolute_ofdm_swing_idx[rf_path]=%d, tx_power_index_offest=%d\n",
1008
		rf_path, cali_info->absolute_ofdm_swing_idx[rf_path], tx_power_index_offest);
1009

1010
	if (tx_power_index_offest > 0XF)
1011
		tx_power_index_offest = 0XF;
1012

1013
	if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0 && cali_info->absolute_ofdm_swing_idx[rf_path] <= tx_power_index_offest) {
1014
		tx_agc_index = cali_info->absolute_ofdm_swing_idx[rf_path];
1015
		tx_bb_swing_index = cali_info->default_ofdm_index;
1016
	} else if (cali_info->absolute_ofdm_swing_idx[rf_path] > tx_power_index_offest) {
1017
		tx_agc_index = tx_power_index_offest;
1018
		cali_info->remnant_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest;
1019
		tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->remnant_ofdm_swing_idx[rf_path];
1020

1021
		if (tx_bb_swing_index > bb_swing_upper_bound)
1022
			tx_bb_swing_index = bb_swing_upper_bound;
1023
	} else {
1024
		tx_agc_index = 0;
1025

1026
		if (cali_info->default_ofdm_index > (cali_info->absolute_ofdm_swing_idx[rf_path] * (-1)))
1027
			tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->absolute_ofdm_swing_idx[rf_path];
1028
		else
1029
			tx_bb_swing_index = bb_swing_lower_bound;
1030

1031
		if (tx_bb_swing_index <  bb_swing_lower_bound)
1032
			tx_bb_swing_index = bb_swing_lower_bound;
1033
	}
1034

1035
	cali_info->absolute_ofdm_swing_idx[rf_path] = tx_agc_index;
1036
	cali_info->bb_swing_idx_ofdm[rf_path] = tx_bb_swing_index;
1037

1038
	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"MixMode Offset Path_%d   cali_info->absolute_ofdm_swing_idx[rf_path]=%d   cali_info->bb_swing_idx_ofdm[rf_path]=%d   tx_power_index_offest=%d\n",
1039
		rf_path, cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->bb_swing_idx_ofdm[rf_path], tx_power_index_offest);
1040

1041
	return true;
1042
}
1043

1044
void power_tracking_by_mix_mode(
1045
	struct dm_struct			*dm,
1046
	enum pwrtrack_method	method,
1047
	u8				rf_path
1048
)
1049
{
1050
	struct _ADAPTER *adapter = dm->adapter;
1051
	HAL_DATA_TYPE		*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
1052
	struct dm_rf_calibration_struct		*cali_info = &(dm->rf_calibrate_info);
1053

1054
	u8				tx_rate = 0xFF;
1055
	u8				channel  = *dm->channel;
1056
	u8				band_width  = hal_data->CurrentChannelBW;
1057
	u8				tx_power_index_offest = 0;
1058
	u8				tx_power_index = 0;
1059

1060
	if (*(dm->mp_mode) == true) {
1061
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1062
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1063
#if (MP_DRIVER == 1)
1064
		PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx);
1065

1066
		tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
1067
#endif
1068
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1069
#ifdef CONFIG_MP_INCLUDED
1070
		PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
1071

1072
		tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
1073
#endif
1074
#endif
1075
#endif
1076
	} else {
1077
		u16	rate	 = *(dm->forced_data_rate);
1078

1079
		if (!rate) { /*auto rate*/
1080
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1081
			tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
1082
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1083
			tx_rate = hw_rate_to_m_rate(dm->tx_rate);
1084
#endif
1085
		} else   /*force rate*/
1086
			tx_rate = (u8) rate;
1087
	}
1088

1089
	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__, tx_rate);
1090

1091
	if ((cali_info->power_index_offset[RF_PATH_A] != 0 ||
1092
	     cali_info->power_index_offset[RF_PATH_B] != 0 ||
1093
	     cali_info->power_index_offset[RF_PATH_C] != 0 ||
1094
	     cali_info->power_index_offset[RF_PATH_D] != 0) &&
1095
	    cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {
1096

1097
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"****************Path_%d POWER Tracking MIX MODE**********\n", rf_path);
1098

1099
		tx_power_index = PHY_GetTxPowerIndex_8814A(adapter, (enum rf_path) rf_path, tx_rate, (enum channel_width)band_width, channel);
1100
		tx_power_index_offest = 63 - tx_power_index;
1101

1102
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"cali_info->absolute_ofdm_swing_idx[%d] =%d   tx_power_index=%d\n", rf_path, cali_info->absolute_ofdm_swing_idx[rf_path], tx_power_index);
1103

1104
		switch (rf_path) {
1105
		case RF_PATH_A:
1106
			get_mix_mode_tx_agc_bb_swing_offset(dm, method, (enum rf_path) rf_path, tx_power_index_offest);
1107
			odm_set_bb_reg(dm, REG_A_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
1108
			odm_set_bb_reg(dm, REG_A_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);	/*set BBswing*/
1109
			break;
1110

1111
		case RF_PATH_B:
1112
			get_mix_mode_tx_agc_bb_swing_offset(dm, method, (enum rf_path) rf_path, tx_power_index_offest);
1113
			odm_set_bb_reg(dm, REG_B_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
1114
			odm_set_bb_reg(dm, REG_B_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);	/*set BBswing*/
1115
			break;
1116

1117
		case RF_PATH_C:
1118
			get_mix_mode_tx_agc_bb_swing_offset(dm, method, (enum rf_path) rf_path, tx_power_index_offest);
1119
			odm_set_bb_reg(dm, REG_C_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
1120
			odm_set_bb_reg(dm, REG_C_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);	/*set BBswing*/
1121
			break;
1122

1123
		case RF_PATH_D:
1124
			get_mix_mode_tx_agc_bb_swing_offset(dm, method, (enum rf_path) rf_path, tx_power_index_offest);
1125
			odm_set_bb_reg(dm, REG_D_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
1126
			odm_set_bb_reg(dm, REG_D_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);	/*set BBswing*/
1127
			break;
1128

1129
		default:
1130
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Wrong path name!!!!\n");
1131
			break;
1132
		}
1133
	} else
1134
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Power index is the same, eeprom_thermal_meter = 0XFF or txpowertrack_control is Disable !!!!\n");
1135
}
1136

1137
void power_tracking_by_tssi_mode(
1138
	struct dm_struct			*dm,
1139
	enum pwrtrack_method	method,
1140
	u8				rf_path
1141
)
1142
{
1143
	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"****************Path_%d POWER Tracking TSSI_MODE**********\n", rf_path);
1144

1145
	set_tx_agc_bb_swing_offset(dm, TSSI_MODE, (enum rf_path) rf_path);
1146

1147
	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"****************Path_%d End POWER Tracking TSSI_MODE**********\n", rf_path);
1148

1149
	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n");
1150
}
1151

1152

1153

1154
void odm_tx_pwr_track_set_pwr8814a(
1155
	void		*dm_void,
1156
	enum pwrtrack_method	method,
1157
	u8				rf_path,
1158
	u8				channel_mapped_index
1159
)
1160
{
1161
	struct dm_struct		*dm = (struct dm_struct *)dm_void;
1162
	void		*adapter = dm->adapter;
1163

1164
	u8			channel  = *dm->channel;
1165
	struct dm_rf_calibration_struct		*cali_info = &(dm->rf_calibrate_info);
1166

1167

1168
	/*K-Free*/
1169
#if 0
1170
	s8			txbb_index = 0;
1171
	s8			txbb_upper_bound = 10, txbb_lower_bound = -5;
1172

1173
	txbb_index = cali_info->kfree_offset[rf_path] / 2;
1174

1175
	if (txbb_index > txbb_upper_bound)
1176
		txbb_index = txbb_upper_bound;
1177
	else if (txbb_index < txbb_lower_bound)
1178
		txbb_index = txbb_lower_bound;
1179

1180
	if (txbb_index >= 0) {
1181
		odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 1);
1182
		odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, (BIT(18) | BIT17 | BIT16 | BIT15), txbb_index);	/*set RF Reg0x55 per path*/
1183
	} else {
1184
		odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 0);
1185
		odm_set_rf_reg(dm, (enum rf_path) rf_path, REG_RF_TX_GAIN_OFFSET, (BIT(18) | BIT(17) | BIT(16) | BIT(15)), (-1) * txbb_index);
1186
	}
1187

1188
#endif
1189

1190
	if (method == TXAGC) {
1191
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"****************Path_%d POWER Tracking No TXAGC MODE**********\n", rf_path);
1192

1193
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "cali_info->absolute_ofdm_swing_idx[%d] =%d\n",
1194
			rf_path, cali_info->absolute_ofdm_swing_idx[rf_path]);
1195
	} else if (method == TSSI_MODE)
1196
		power_tracking_by_tssi_mode(dm, TSSI_MODE, (enum rf_path) rf_path);
1197
	else if (method == BBSWING) {	/*use for mp driver clean power tracking status*/
1198
		switch (rf_path) {
1199
		case RF_PATH_A:
1200
			odm_set_bb_reg(dm, REG_A_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
1201
			odm_set_bb_reg(dm, REG_A_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);	/*set BBswing*/
1202
			break;
1203

1204
		case RF_PATH_B:
1205
			odm_set_bb_reg(dm, REG_B_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
1206
			odm_set_bb_reg(dm, REG_B_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);	/*set BBswing*/
1207
			break;
1208

1209
		case RF_PATH_C:
1210
			odm_set_bb_reg(dm, REG_C_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
1211
			odm_set_bb_reg(dm, REG_C_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);	/*set BBswing*/
1212
			break;
1213

1214
		case RF_PATH_D:
1215
			odm_set_bb_reg(dm, REG_D_TX_AGC, TXAGC_BITMASK, cali_info->absolute_ofdm_swing_idx[rf_path]);
1216
			odm_set_bb_reg(dm, REG_D_BBSWING, BBSWING_BITMASK, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);	/*set BBswing*/
1217
			break;
1218

1219
		default:
1220
			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Wrong path name!!!!\n");
1221

1222
			break;
1223
		}
1224

1225
		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "rf_path=%d   Clear 8814 Power tracking TXAGC=%d  BBSwing=%d\n",
1226
			rf_path, cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->bb_swing_idx_ofdm[rf_path]);
1227

1228
	} else if (method == MIX_MODE)
1229
		power_tracking_by_mix_mode(dm, MIX_MODE, (enum rf_path) rf_path);
1230
	else if (method == MIX_2G_TSSI_5G_MODE) {
1231
		if (channel <= 14)
1232
			power_tracking_by_mix_mode(dm, MIX_MODE, (enum rf_path) rf_path);
1233
		else
1234
			power_tracking_by_tssi_mode(dm, TSSI_MODE, (enum rf_path) rf_path);
1235
	} else if (method == MIX_5G_TSSI_2G_MODE) {
1236
		if (channel <= 14)
1237
			power_tracking_by_tssi_mode(dm, TSSI_MODE, (enum rf_path) rf_path);
1238
		else
1239
			power_tracking_by_mix_mode(dm, MIX_MODE, (enum rf_path) rf_path);
1240
	}
1241
}	/*odm_tx_pwr_track_set_pwr8814a*/
1242

1243

1244
void get_delta_swing_table_8814a(
1245
	void		*dm_void,
1246
	u8 **temperature_up_a,
1247
	u8 **temperature_down_a,
1248
	u8 **temperature_up_b,
1249
	u8 **temperature_down_b
1250
)
1251
{
1252
	struct dm_struct		*dm = (struct dm_struct *)dm_void;
1253
	struct _ADAPTER *adapter = dm->adapter;
1254
	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
1255
	u8		tx_rate			= 0xFF;
1256
	u8	channel		 = *dm->channel;
1257

1258
	if (*(dm->mp_mode) == true) {
1259
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1260
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1261
#if (MP_DRIVER == 1)
1262
		PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx);
1263

1264
		tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
1265
#endif
1266
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1267
#ifdef CONFIG_MP_INCLUDED
1268
		PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
1269

1270
		tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
1271
#endif
1272
#endif
1273
#endif
1274
	} else {
1275
		u16	rate	 = *(dm->forced_data_rate);
1276

1277
		if (!rate) { /*auto rate*/
1278
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1279
			tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
1280
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1281
			tx_rate = hw_rate_to_m_rate(dm->tx_rate);
1282
#endif
1283
		} else   /*force rate*/
1284
			tx_rate = (u8) rate;
1285
	}
1286

1287
	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__, tx_rate);
1288

1289
	if (1 <= channel && channel <= 14) {
1290
		if (IS_CCK_RATE(tx_rate)) {
1291
			*temperature_up_a   = cali_info->delta_swing_table_idx_2g_cck_a_p;
1292
			*temperature_down_a = cali_info->delta_swing_table_idx_2g_cck_a_n;
1293
			*temperature_up_b   = cali_info->delta_swing_table_idx_2g_cck_b_p;
1294
			*temperature_down_b = cali_info->delta_swing_table_idx_2g_cck_b_n;
1295
		} else {
1296
			*temperature_up_a   = cali_info->delta_swing_table_idx_2ga_p;
1297
			*temperature_down_a = cali_info->delta_swing_table_idx_2ga_n;
1298
			*temperature_up_b   = cali_info->delta_swing_table_idx_2gb_p;
1299
			*temperature_down_b = cali_info->delta_swing_table_idx_2gb_n;
1300
		}
1301
	} else if (36 <= channel && channel <= 64) {
1302
		*temperature_up_a   = cali_info->delta_swing_table_idx_5ga_p[0];
1303
		*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[0];
1304
		*temperature_up_b   = cali_info->delta_swing_table_idx_5gb_p[0];
1305
		*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[0];
1306
	} else if (100 <= channel && channel <= 144) {
1307
		*temperature_up_a   = cali_info->delta_swing_table_idx_5ga_p[1];
1308
		*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[1];
1309
		*temperature_up_b   = cali_info->delta_swing_table_idx_5gb_p[1];
1310
		*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[1];
1311
	} else if (149 <= channel && channel <= 177) {
1312
		*temperature_up_a   = cali_info->delta_swing_table_idx_5ga_p[2];
1313
		*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[2];
1314
		*temperature_up_b   = cali_info->delta_swing_table_idx_5gb_p[2];
1315
		*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[2];
1316
	} else {
1317
		*temperature_up_a   = (u8 *)delta_swing_table_idx_2ga_p_8188e;
1318
		*temperature_down_a = (u8 *)delta_swing_table_idx_2ga_n_8188e;
1319
		*temperature_up_b   = (u8 *)delta_swing_table_idx_2ga_p_8188e;
1320
		*temperature_down_b = (u8 *)delta_swing_table_idx_2ga_n_8188e;
1321
	}
1322

1323
	return;
1324
}
1325

1326

1327
void get_delta_swing_table_8814a_path_cd(
1328
	void		*dm_void,
1329
	u8 **temperature_up_c,
1330
	u8 **temperature_down_c,
1331
	u8 **temperature_up_d,
1332
	u8 **temperature_down_d
1333
)
1334
{
1335
	struct dm_struct		*dm = (struct dm_struct *)dm_void;
1336
	struct _ADAPTER *adapter = dm->adapter;
1337
	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
1338
	u8		tx_rate			= 0xFF;
1339
	u8	channel		 = *dm->channel;
1340

1341
	if (*(dm->mp_mode) == true) {
1342
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1343
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1344
#if (MP_DRIVER == 1)
1345
		PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx);
1346

1347
		tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
1348
#endif
1349
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1350
#ifdef CONFIG_MP_INCLUDED
1351
		PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
1352

1353
		tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
1354
#endif
1355
#endif
1356
#endif
1357
	} else {
1358
		u16	rate	 = *(dm->forced_data_rate);
1359

1360
		if (!rate) { /*auto rate*/
1361
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1362
			tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
1363
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1364
			tx_rate = hw_rate_to_m_rate(dm->tx_rate);
1365
#endif
1366
		} else   /*force rate*/
1367
			tx_rate = (u8) rate;
1368
	}
1369

1370
	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__, tx_rate);
1371

1372
	if (1 <= channel && channel <= 14) {
1373
		if (IS_CCK_RATE(tx_rate)) {
1374
			*temperature_up_c  = cali_info->delta_swing_table_idx_2g_cck_c_p;
1375
			*temperature_down_c = cali_info->delta_swing_table_idx_2g_cck_c_n;
1376
			*temperature_up_d   = cali_info->delta_swing_table_idx_2g_cck_d_p;
1377
			*temperature_down_d = cali_info->delta_swing_table_idx_2g_cck_d_n;
1378
		} else {
1379
			*temperature_up_c   = cali_info->delta_swing_table_idx_2gc_p;
1380
			*temperature_down_c = cali_info->delta_swing_table_idx_2gc_n;
1381
			*temperature_up_d   = cali_info->delta_swing_table_idx_2gd_p;
1382
			*temperature_down_d = cali_info->delta_swing_table_idx_2gd_n;
1383
		}
1384
	} else if (36 <= channel && channel <= 64) {
1385
		*temperature_up_c   = cali_info->delta_swing_table_idx_5gc_p[0];
1386
		*temperature_down_c = cali_info->delta_swing_table_idx_5gc_n[0];
1387
		*temperature_up_d   = cali_info->delta_swing_table_idx_5gd_p[0];
1388
		*temperature_down_d = cali_info->delta_swing_table_idx_5gd_n[0];
1389
	} else if (100 <= channel && channel <= 144) {
1390
		*temperature_up_c   = cali_info->delta_swing_table_idx_5gc_p[1];
1391
		*temperature_down_c = cali_info->delta_swing_table_idx_5gc_n[1];
1392
		*temperature_up_d   = cali_info->delta_swing_table_idx_5gd_p[1];
1393
		*temperature_down_d = cali_info->delta_swing_table_idx_5gd_n[1];
1394
	} else if (149 <= channel && channel <= 177) {
1395
		*temperature_up_c   = cali_info->delta_swing_table_idx_5gc_p[2];
1396
		*temperature_down_c = cali_info->delta_swing_table_idx_5gc_n[2];
1397
		*temperature_up_d   = cali_info->delta_swing_table_idx_5gd_p[2];
1398
		*temperature_down_d = cali_info->delta_swing_table_idx_5gd_n[2];
1399
	} else {
1400
		*temperature_up_c   = (u8 *)delta_swing_table_idx_2ga_p_8188e;
1401
		*temperature_down_c = (u8 *)delta_swing_table_idx_2ga_n_8188e;
1402
		*temperature_up_d   = (u8 *)delta_swing_table_idx_2ga_p_8188e;
1403
		*temperature_down_d = (u8 *)delta_swing_table_idx_2ga_n_8188e;
1404
	}
1405

1406
	return;
1407
}
1408

1409
void configure_txpower_track_8814a(
1410
	struct txpwrtrack_cfg	*config
1411
)
1412
{
1413
	config->swing_table_size_cck = CCK_TABLE_SIZE;
1414
	config->swing_table_size_ofdm = OFDM_TABLE_SIZE;
1415
	config->threshold_iqk = 8;
1416
	config->average_thermal_num = AVG_THERMAL_NUM_8814A;
1417
	config->rf_path_count = MAX_PATH_NUM_8814A;
1418
	config->thermal_reg_addr = RF_T_METER_88E;
1419

1420
	config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr8814a;
1421
	config->do_iqk = do_iqk_8814a;
1422
	config->phy_lc_calibrate = halrf_lck_trigger;
1423
	config->get_delta_swing_table = get_delta_swing_table_8814a;
1424
	config->get_delta_swing_table8814only = get_delta_swing_table_8814a_path_cd;
1425
}
1426

1427
void _phy_lc_calibrate_8814a(
1428
	struct dm_struct		*dm
1429
)
1430
{
1431
	u32	lc_cal = 0, cnt;
1432

1433
	/*Check continuous TX and Packet TX*/
1434
	u32	reg0x914 = odm_read_4byte(dm, REG_SINGLE_TONE_CONT_TX_JAGUAR);;
1435

1436
	/*Backup RF reg18.*/
1437
	lc_cal = odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK);
1438

1439
	if ((reg0x914 & 0x70000) == 0)
1440
		odm_write_1byte(dm, REG_TXPAUSE_8812A, 0xFF);
1441

1442
	/*3 3. Read RF reg18*/
1443
	lc_cal = odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK);
1444

1445
	/*3 4. Set LC calibration begin bit15*/
1446
	odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000);
1447

1448
	ODM_delay_ms(100);
1449

1450
	for (cnt = 0; cnt < 100; cnt++) {
1451
		if (odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
1452
			break;
1453

1454
		ODM_delay_ms(10);
1455
	}
1456

1457
	RF_DBG(dm, DBG_RF_IQK, "retry cnt = %d\n", cnt);
1458

1459

1460

1461
	/*3 Restore original situation*/
1462
	if ((reg0x914 & 70000) == 0)
1463
		odm_write_1byte(dm, REG_TXPAUSE_8812A, 0x00);
1464

1465
	/*Recover channel number*/
1466
	odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal);
1467

1468
	pr_debug("Call %s\n", __func__);
1469
}
1470

1471
void phy_lc_calibrate_8814a(
1472
	void		*dm_void
1473
)
1474
{
1475
	struct dm_struct		*dm = (struct dm_struct *)dm_void;
1476

1477
	_phy_lc_calibrate_8814a(dm);
1478
}
1479

1480

1481
#if 0
1482
void _phy_ap_calibrate_8814a(
1483
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1484
	struct dm_struct		*dm,
1485
#else
1486
	void	*adapter,
1487
#endif
1488
	s8		delta,
1489
	boolean		is2T
1490
)
1491
{
1492
}
1493

1494
void phy_ap_calibrate_8814a(
1495
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1496
	struct dm_struct		*dm,
1497
#else
1498
	void	*adapter,
1499
#endif
1500
	s8		delta
1501
)
1502
{
1503

1504
}
1505

1506
#endif
1507
void phy_dp_calibrate_8814a(
1508
	struct dm_struct	*dm
1509
)
1510
{
1511
}
1512

1513

1514
boolean _phy_query_rf_path_switch_8814a(
1515
	void	*adapter
1516
)
1517
{
1518
	return true;
1519
}
1520

1521

1522
boolean phy_query_rf_path_switch_8814a(
1523
	void	*adapter
1524
)
1525
{
1526

1527
#if DISABLE_BB_RF
1528
	return true;
1529
#endif
1530

1531
	return _phy_query_rf_path_switch_8814a(adapter);
1532
}
1533

1534

1535
void _phy_set_rf_path_switch_8814a(
1536
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1537
	struct dm_struct		*dm,
1538
#else
1539
	void	*adapter,
1540
#endif
1541
	boolean		is_main,
1542
	boolean		is2T
1543
)
1544
{
1545
}
1546
void phy_set_rf_path_switch_8814a(
1547
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1548
	struct dm_struct		*dm,
1549
#else
1550
	void	*adapter,
1551
#endif
1552
	boolean		is_main
1553
)
1554
{
1555
}
1556

1557

1558

1559

1560
#else	/*(RTL8814A_SUPPORT == 0)*/
1561
void phy_lc_calibrate_8814a(
1562
	struct dm_struct		*dm
1563
) {}
1564

1565
void phy_iq_calibrate_8814a(
1566
	struct dm_struct	*dm,
1567
	boolean is_recovery
1568
) {}
1569
#endif	/* (RTL8814A_SUPPORT == 0)*/
1570

1571
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