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nu11secur1ty
GitHub Repository: nu11secur1ty/Kali-Linux
Path: blob/master/ALFA-W1F1/RTL8814AU/hal/rtl8814a/rtl8814a_hal_init.c
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1
/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#define _RTL8814A_HAL_INIT_C_
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17
/* #include <drv_types.h> */
18
#include <rtl8814a_hal.h>
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#include "hal8814a_fw.h"
20
/* -------------------------------------------------------------------------
21
*
22
* LLT R/W/Init function
23
*
24
* ------------------------------------------------------------------------- */
25
void
26
Hal_InitEfuseVars_8814A(
27
PADAPTER Adapter
28
)
29
{
30
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
31
PEFUSE_HAL pEfuseHal = &(pHalData->EfuseHal);
32
u16 *ptr;
33
34
#define INIT_EFUSE(var, value) ptr = (u16 *)&var; *ptr = value
35
36
RTW_INFO("====> %s\n", __func__);
37
/* 2 Common */
38
INIT_EFUSE(pEfuseHal->WordUnit , EFUSE_MAX_WORD_UNIT);
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RTW_INFO("====>pEfuseHal->WordUnit %d\n", pEfuseHal->WordUnit);
40
INIT_EFUSE(pEfuseHal->BankSize , 512);
41
INIT_EFUSE(pEfuseHal->OOBProtectBytes, EFUSE_OOB_PROTECT_BYTES);
42
RTW_INFO("====>pEfuseHal->OOBProtectBytes %d\n", pEfuseHal->OOBProtectBytes);
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INIT_EFUSE(pEfuseHal->ProtectBytes , EFUSE_PROTECT_BYTES_BANK_8814A);
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RTW_INFO("====>pEfuseHal->ProtectBytes %d\n", pEfuseHal->ProtectBytes);
45
INIT_EFUSE(pEfuseHal->BankAvailBytes , (pEfuseHal->BankSize - pEfuseHal->OOBProtectBytes));
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INIT_EFUSE(pEfuseHal->TotalBankNum , EFUSE_MAX_BANK_8814A);
47
INIT_EFUSE(pEfuseHal->HeaderRetry , 0);
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INIT_EFUSE(pEfuseHal->DataRetry , 0);
49
50
/* 2 Wi-Fi */
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INIT_EFUSE(pEfuseHal->MaxSecNum_WiFi , EFUSE_MAX_SECTION_8814A);
52
RTW_INFO("====>pEfuseHal->MaxSecNum_WiFi %d\n", pEfuseHal->MaxSecNum_WiFi);
53
INIT_EFUSE(pEfuseHal->PhysicalLen_WiFi , EFUSE_REAL_CONTENT_LEN_8814A);
54
RTW_INFO("====>pEfuseHal->PhysicalLen_WiFi %d\n", pEfuseHal->PhysicalLen_WiFi);
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INIT_EFUSE(pEfuseHal->LogicalLen_WiFi , EFUSE_MAP_LEN_8814A);
56
RTW_INFO("====>pEfuseHal->LogicalLen_WiFi %d\n", pEfuseHal->LogicalLen_WiFi);
57
INIT_EFUSE(pEfuseHal->BankNum_WiFi , pEfuseHal->PhysicalLen_WiFi / pEfuseHal->BankSize);
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INIT_EFUSE(pEfuseHal->TotalAvailBytes_WiFi, (pEfuseHal->PhysicalLen_WiFi - (pEfuseHal->TotalBankNum * pEfuseHal->OOBProtectBytes)));
59
60
/* 2 BT */
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INIT_EFUSE(pEfuseHal->MaxSecNum_BT , 0);
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INIT_EFUSE(pEfuseHal->PhysicalLen_BT , 0);
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INIT_EFUSE(pEfuseHal->LogicalLen_BT , 0);
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INIT_EFUSE(pEfuseHal->BankNum_BT , 0);
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INIT_EFUSE(pEfuseHal->TotalAvailBytes_BT, 0);
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67
RTW_INFO("%s <====\n", __func__);
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}
69
70
71
s32 InitLLTTable8814A(
72
PADAPTER Adapter
73
)
74
{
75
/* Auto-init LLT table ( Set REG:0x208[BIT0] ) */
76
/* Write 1 to enable HW init LLT, driver need polling to 0 meaning init success */
77
u8 tmp1byte = 0, testcnt = 0;
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s32 Status = _SUCCESS;
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80
tmp1byte = rtw_read8(Adapter, REG_AUTO_LLT_8814A);
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rtw_write8(Adapter, REG_AUTO_LLT_8814A, tmp1byte | BIT0);
82
while (tmp1byte & BIT0) {
83
tmp1byte = rtw_read8(Adapter, REG_AUTO_LLT_8814A);
84
rtw_mdelay_os(100);
85
testcnt++;
86
if (testcnt > 100) {
87
Status = _FAIL;
88
break;
89
}
90
}
91
return Status;
92
}
93
94
#ifdef CONFIG_WOWLAN
95
void hal_DetectWoWMode(PADAPTER pAdapter)
96
{
97
adapter_to_pwrctl(pAdapter)->bSupportRemoteWakeup = _TRUE;
98
}
99
#endif
100
101
void
102
_FWDownloadEnable_8814A(
103
PADAPTER Adapter,
104
BOOLEAN enable
105
)
106
{
107
u8 tmp;
108
u16 u2Tmp = 0;
109
110
if (enable) {
111
/* MCU firmware download enable. */
112
u2Tmp = rtw_read16(Adapter, REG_8051FW_CTRL_8814A);
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u2Tmp &= 0x3000;
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u2Tmp &= (~BIT12);
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u2Tmp |= BIT13;
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u2Tmp |= BIT0;
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rtw_write16(Adapter, REG_8051FW_CTRL_8814A, u2Tmp);
118
119
/* Clear Rom DL enable */
120
/* tmp = rtw_read8(Adapter, REG_8051FW_CTRL_8814A+2); */ /* modify by gw 20130826(advice by hw) */
121
/* rtw_write8(Adapter, REG_8051FW_CTRL_8814A+2, tmp&0xf7); */ /* clear bit3 */
122
} else {
123
/* MCU firmware download enable. */
124
tmp = rtw_read8(Adapter, REG_8051FW_CTRL_8814A);
125
rtw_write8(Adapter, REG_8051FW_CTRL_8814A, tmp & 0xfe);
126
}
127
}
128
129
#define MAX_REG_BOLCK_SIZE 196
130
131
void
132
_BlockWrite_8814A(
133
PADAPTER Adapter,
134
void *buffer,
135
u32 buffSize
136
)
137
{
138
u32 blockSize_p1 = 4; /* (Default) Phase #1 : PCI muse use 4-byte write to download FW */
139
u32 blockSize_p2 = 8; /* Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. */
140
u32 blockSize_p3 = 1; /* Phase #3 : Use 1-byte, the remnant of FW image. */
141
u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0;
142
u32 remainSize_p1 = 0, remainSize_p2 = 0;
143
u8 *bufferPtr = (u8 *)buffer;
144
u32 i = 0, offset = 0;
145
146
#ifdef CONFIG_USB_HCI
147
blockSize_p1 = MAX_REG_BOLCK_SIZE; /* Use 196-byte write to download FW */
148
/* Small block size will increase USB init speed. But prevent FW download fail */
149
/* use 4-Byte instead of 196-Byte to write FW. */
150
#endif
151
152
/* 3 Phase #1 */
153
blockCount_p1 = buffSize / blockSize_p1;
154
remainSize_p1 = buffSize % blockSize_p1;
155
156
157
158
for (i = 0 ; i < blockCount_p1 ; i++) {
159
#ifdef CONFIG_USB_HCI
160
rtw_writeN(Adapter, (FW_START_ADDRESS + i * blockSize_p1), blockSize_p1, (bufferPtr + i * blockSize_p1));
161
#else
162
rtw_write32(Adapter, (FW_START_ADDRESS + i * blockSize_p1), *((u32 *)(bufferPtr + i * blockSize_p1)));
163
#endif
164
}
165
166
/* 3 Phase #2 */
167
if (remainSize_p1) {
168
offset = blockCount_p1 * blockSize_p1;
169
170
blockCount_p2 = remainSize_p1 / blockSize_p2;
171
remainSize_p2 = remainSize_p1 % blockSize_p2;
172
173
174
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#ifdef CONFIG_USB_HCI
176
for (i = 0 ; i < blockCount_p2 ; i++)
177
rtw_writeN(Adapter, (FW_START_ADDRESS + offset + i * blockSize_p2), blockSize_p2, (bufferPtr + offset + i * blockSize_p2));
178
#endif
179
}
180
181
/* 3 Phase #3 */
182
if (remainSize_p2) {
183
offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2);
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185
blockCount_p3 = remainSize_p2 / blockSize_p3;
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187
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for (i = 0 ; i < blockCount_p3 ; i++)
189
rtw_write8(Adapter, (FW_START_ADDRESS + offset + i), *(bufferPtr + offset + i));
190
}
191
}
192
193
void
194
_PageWrite_8814A(
195
PADAPTER Adapter,
196
u32 page,
197
void *buffer,
198
u32 size
199
)
200
{
201
u8 value8;
202
u8 u8Page = (u8)(page & 0x07) ;
203
204
value8 = (rtw_read8(Adapter, REG_8051FW_CTRL_8814A + 2) & 0xF8) | u8Page ;
205
rtw_write8(Adapter, REG_8051FW_CTRL_8814A + 2, value8);
206
207
_BlockWrite_8814A(Adapter, buffer, size);
208
}
209
210
void
211
_FillDummy_8814A(
212
u8 *pFwBuf,
213
u32 *pFwLen
214
)
215
{
216
u32 FwLen = *pFwLen;
217
u8 remain = (u8)(FwLen % 4);
218
remain = (remain == 0) ? 0 : (4 - remain);
219
220
while (remain > 0) {
221
pFwBuf[FwLen] = 0;
222
FwLen++;
223
remain--;
224
}
225
226
*pFwLen = FwLen;
227
}
228
229
void
230
_WriteFW_8814A(
231
PADAPTER Adapter,
232
void *buffer,
233
u32 size
234
)
235
{
236
u32 pageNums, remainSize ;
237
u32 page, offset;
238
u8 *bufferPtr = (u8 *)buffer;
239
240
#ifdef CONFIG_PCI_HCI
241
/* 20100120 Joseph: Add for 88CE normal chip. */
242
/* Fill in zero to make firmware image to dword alignment. */
243
_FillDummy_8814A(bufferPtr, &size);
244
#endif /* CONFIG_PCI_HCI */
245
246
pageNums = size / MAX_PAGE_SIZE ;
247
248
/* RT_ASSERT((pageNums <= 8), ("Page numbers should not greater then 8\n")); */
249
250
remainSize = size % MAX_PAGE_SIZE;
251
252
for (page = 0; page < pageNums; page++) {
253
offset = page * MAX_PAGE_SIZE;
254
_PageWrite_8814A(Adapter, page, (bufferPtr + offset), MAX_PAGE_SIZE);
255
rtw_udelay_os(2);
256
}
257
if (remainSize) {
258
offset = pageNums * MAX_PAGE_SIZE;
259
page = pageNums;
260
_PageWrite_8814A(Adapter, page, (bufferPtr + offset), remainSize);
261
}
262
}
263
264
void
265
_3081Disable8814A(
266
PADAPTER Adapter
267
)
268
{
269
u8 u1bTmp;
270
u1bTmp = rtw_read8(Adapter, REG_SYS_FUNC_EN_8814A + 1);
271
rtw_write8(Adapter, REG_SYS_FUNC_EN_8814A + 1, u1bTmp & (~BIT2));
272
273
274
}
275
276
void
277
_3081Enable8814A(
278
PADAPTER Adapter
279
)
280
{
281
u8 u1bTmp;
282
u1bTmp = rtw_read8(Adapter, REG_SYS_FUNC_EN_8814A + 1);
283
rtw_write8(Adapter, REG_SYS_FUNC_EN_8814A + 1, u1bTmp | BIT2);
284
}
285
286
287
/* add by ylb 20130814 for 3081 download FW */
288
static
289
BOOLEAN
290
IDDMADownLoadFW_3081(
291
PADAPTER Adapter,
292
u32 source,
293
u32 dest,
294
u32 length,
295
BOOLEAN fs,
296
BOOLEAN ls
297
)
298
{
299
u32 ch0ctrl = (DDMA_CHKSUM_EN | DDMA_CH_OWN);
300
u32 cnt;
301
u8 tmp;
302
/* check if ddma ch0 is idle */
303
cnt = 20;
304
while (rtw_read32(Adapter, REG_DDMA_CH0CTRL) & DDMA_CH_OWN) {
305
rtw_udelay_os(1000);
306
cnt--;
307
if (cnt == 0) {
308
RTW_INFO("IDDMADownLoadFW_3081, line%d: CNT fail\n", __LINE__);
309
return _FALSE;
310
}
311
}
312
ch0ctrl |= length & DDMA_LEN_MASK;
313
314
/* check if chksum continuous */
315
if (fs == _FALSE)
316
ch0ctrl |= DDMA_CH_CHKSUM_CNT;
317
rtw_write32(Adapter, REG_DDMA_CH0SA, source);
318
rtw_write32(Adapter, REG_DDMA_CH0DA, dest);
319
rtw_write32(Adapter, REG_DDMA_CH0CTRL, ch0ctrl);
320
321
cnt = 20;
322
while (rtw_read32(Adapter, REG_DDMA_CH0CTRL) & DDMA_CH_OWN) {
323
rtw_udelay_os(1000);
324
cnt--;
325
if (cnt == 0) {
326
RTW_INFO("IDDMADownLoadFW_3081, line%d: CNT fail\n", __LINE__);
327
return _FALSE;
328
}
329
}
330
331
/* check checksum */
332
if (ls == _TRUE) {
333
tmp = rtw_read8(Adapter, REG_8051FW_CTRL_8814A);
334
if (0 == (rtw_read32(Adapter, REG_DDMA_CH0CTRL) & DDMA_CHKSUM_FAIL)) {
335
/* chksum ok */
336
RTW_INFO("Check sum OK\n");
337
/* imem */
338
if (dest < OCPBASE_DMEM_3081) {
339
tmp |= IMEM_DL_RDY;
340
rtw_write8(Adapter, REG_8051FW_CTRL_8814A, tmp | IMEM_CHKSUM_OK);
341
RTW_INFO("imem check sum tmp %d\n", tmp);
342
}
343
/* dmem */
344
else {
345
tmp |= DMEM_DL_RDY;
346
rtw_write8(Adapter, REG_8051FW_CTRL_8814A, tmp | DMEM_CHKSUM_OK);
347
RTW_INFO("dmem check sum tmp %d\n", tmp);
348
}
349
} else {
350
/* chksum fail */
351
RTW_INFO("Check sum fail\n");
352
ch0ctrl = rtw_read32(Adapter, REG_DDMA_CH0CTRL);
353
rtw_write32(Adapter, REG_DDMA_CH0CTRL, ch0ctrl | DDMA_RST_CHKSUM_STS);
354
355
/* imem */
356
if (dest < OCPBASE_DMEM_3081) {
357
tmp &= (~IMEM_DL_RDY);
358
rtw_write8(Adapter, REG_8051FW_CTRL_8814A, tmp & ~IMEM_CHKSUM_OK);
359
}
360
/* dmem */
361
else {
362
tmp &= (~DMEM_DL_RDY);
363
rtw_write8(Adapter, REG_8051FW_CTRL_8814A, tmp & ~DMEM_CHKSUM_OK);
364
}
365
return _FALSE;
366
}
367
}
368
return _TRUE;
369
}
370
371
372
/* add by ylb 20130814 for 3081 download FW */
373
static
374
BOOLEAN
375
WaitDownLoadRSVDPageOK_3081(
376
PADAPTER Adapter
377
)
378
{
379
u8 BcnValidReg = 0, TxBcReg = 0;
380
u8 count = 0, DLBcnCount = 0;
381
BOOLEAN bRetValue = _FALSE;
382
383
#if defined(CONFIG_PCI_HCI)
384
/* Polling Beacon Queue to send Beacon */
385
TxBcReg = rtw_read8(Adapter, REG_MGQ_TXBD_NUM_8814A + 3);
386
count = 0;
387
while ((count < 20) && (TxBcReg & BIT4)) {
388
count++;
389
rtw_udelay_os(10);
390
TxBcReg = rtw_read8(Adapter, REG_MGQ_TXBD_NUM_8814A + 3);
391
}
392
393
rtw_write8(Adapter, REG_MGQ_TXBD_NUM_8814A + 3, TxBcReg | BIT4);
394
#endif /* #if defined(CONFIG_PCI_HCI) */
395
/* check rsvd page download OK. */
396
BcnValidReg = rtw_read8(Adapter, REG_FIFOPAGE_CTRL_2_8814A + 1);
397
count = 0;
398
while (!(BcnValidReg & BIT7) && count < 20) {
399
count++;
400
rtw_udelay_os(50);
401
BcnValidReg = rtw_read8(Adapter, REG_FIFOPAGE_CTRL_2_8814A + 1);
402
}
403
404
/* Set 1 to Clear BIT7 by SW */
405
if (BcnValidReg & BIT7) {
406
rtw_write8(Adapter, REG_FIFOPAGE_CTRL_2_8814A + 1, (BcnValidReg | BIT7));
407
bRetValue = _TRUE;
408
} else {
409
RTW_INFO("WaitDownLoadRSVDPageOK_3081(): Download RSVD page failed!\n");
410
bRetValue = _FALSE;
411
}
412
413
return bRetValue;
414
}
415
416
417
void
418
SetDownLoadFwRsvdPagePkt_8814A(
419
PADAPTER Adapter,
420
void *buffer,
421
u32 len
422
)
423
{
424
PHAL_DATA_TYPE pHalData;
425
struct xmit_frame *pcmdframe;
426
struct xmit_priv *pxmitpriv;
427
struct pkt_attrib *pattrib;
428
/* The desc lengh in Tx packet buffer of 8814A is 40 bytes. */
429
u16 BufIndex = 0, TxDescOffset = TXDESC_OFFSET;
430
u32 TotalPacketLen = len;
431
BOOLEAN bDLOK = FALSE;
432
u8 *ReservedPagePacket;
433
434
pHalData = GET_HAL_DATA(Adapter);
435
pxmitpriv = &Adapter->xmitpriv;
436
437
#ifdef CONFIG_BCN_ICF
438
pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv);
439
#else
440
pcmdframe = alloc_mgtxmitframe(pxmitpriv);
441
#endif
442
if (pcmdframe == NULL)
443
return;
444
445
ReservedPagePacket = pcmdframe->buf_addr;
446
447
BufIndex = TxDescOffset;
448
449
TotalPacketLen = len + BufIndex;
450
451
_rtw_memcpy(&ReservedPagePacket[BufIndex], buffer, len);
452
/* RTW_INFO("SetFwRsvdPagePkt_8814A(): HW_VAR_SET_TX_CMD: BCN, %p, %d\n", &ReservedPagePacket[BufIndex], len); */
453
454
/* RTW_INFO("SetFwRsvdPagePkt(): TotalPacketLen=%d\n", TotalPacketLen); */
455
456
/* update attribute */
457
pattrib = &pcmdframe->attrib;
458
update_mgntframe_attrib(Adapter, pattrib);
459
pattrib->qsel = QSLT_BEACON;
460
pattrib->pktlen = pattrib->last_txcmdsz = TotalPacketLen - TxDescOffset;
461
462
dump_mgntframe(Adapter, pcmdframe);
463
464
/* ReturnGenTempBuffer(pAdapter, pGenBufReservedPagePacket); */
465
}
466
467
468
void
469
HalROMDownloadFWRSVDPage8814A(
470
PADAPTER Adapter,
471
void *buffer,
472
u32 Len
473
)
474
{
475
u8 u1bTmp = 0, tmpReg422 = 0;
476
u8 BcnValidReg = 0, TxBcReg = 0;
477
BOOLEAN bSendBeacon = _FALSE, bDownLoadRSVDPageOK = _FALSE;
478
u8 *pbuffer = buffer;
479
480
BOOLEAN fs = _TRUE, ls = _FALSE;
481
u8 FWHeaderSize = 64, PageSize = 128 ;
482
u16 RsvdPageNum = 0;
483
u32 dmem_pkt_size = 0, iram_pkt_size = 0 , MaxRsvdPageBufSize = 0;
484
u32 last_block_size = 0, filesize_ram_block = 0, pkt_offset = 0;
485
u32 txpktbuf_bndy = 0;
486
u32 BeaconHeaderInTxPacketBuf = 0, MEMOffsetInTxPacketBuf = 0;
487
u8 bcn_ctrl = rtw_read8(Adapter, REG_BCN_CTRL);
488
489
/* Set REG_CR bit 8. DMA beacon by SW. */
490
u1bTmp = rtw_read8(Adapter, REG_CR_8814A + 1);
491
rtw_write8(Adapter, REG_CR_8814A + 1, (u1bTmp | BIT0));
492
/*RTW_INFO("%s-%d: enable SW BCN, REG_CR=0x%x\n", __func__, __LINE__, rtw_read32(Adapter, REG_CR));*/
493
494
/* Disable Hw protection for a time which revserd for Hw sending beacon. */
495
/* Fix download reserved page packet fail that access collision with the protection time. */
496
/* 2010.05.11. Added by tynli. 0x550[4]=1, 0x550[3]=0 */
497
rtw_write8(Adapter, REG_BCN_CTRL, (bcn_ctrl & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT);
498
499
/* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. 0x422[6]=0 */
500
tmpReg422 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL_8814A + 2);
501
rtw_write8(Adapter, REG_FWHW_TXQ_CTRL_8814A + 2, tmpReg422 & (~BIT6));
502
503
if (tmpReg422 & BIT6) {
504
RTW_INFO("HalROMDownloadFWRSVDPage8814A(): There is an Adapter is sending beacon.\n");
505
bSendBeacon = _TRUE;
506
}
507
508
/* Set The head page of packet of Bcnq */
509
rtw_hal_get_def_var(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&txpktbuf_bndy);
510
rtw_write16(Adapter, REG_FIFOPAGE_CTRL_2_8814A, txpktbuf_bndy);
511
512
/* RTW_INFO("HalROMDownloadFWRSVDPage8814A: txpktbuf_bndy=%d\n", txpktbuf_bndy); */
513
514
/* Clear beacon valid check bit. 0x205[7]=1 */
515
BcnValidReg = rtw_read8(Adapter, REG_FIFOPAGE_CTRL_2_8814A + 1);
516
rtw_write8(Adapter, REG_FIFOPAGE_CTRL_2_8814A + 1, (BcnValidReg | BIT7));
517
518
/* Return Beacon TCB. */
519
/* ReturnBeaconQueueTcb_8814A(Adapter); */
520
521
dmem_pkt_size = (u32)GET_FIRMWARE_HDR_TOTAL_DMEM_SZ_3081(pbuffer);
522
iram_pkt_size = (u32)GET_FIRMWARE_HDR_IRAM_SZ_3081(pbuffer);
523
dmem_pkt_size += (u32)FW_CHKSUM_DUMMY_SZ;
524
iram_pkt_size += (u32)FW_CHKSUM_DUMMY_SZ;
525
526
if (dmem_pkt_size + iram_pkt_size + FWHeaderSize != Len) {
527
RTW_INFO("ERROR: Fw Hdr size do not match the real fw size!!\n");
528
RTW_INFO("dmem_pkt_size = %d, iram_pkt_size = %d,FWHeaderSize = %d, Len = %d!!\n", dmem_pkt_size, iram_pkt_size, FWHeaderSize, Len);
529
return;
530
}
531
RTW_INFO("dmem_pkt_size = %d, iram_pkt_size = %d,FWHeaderSize = %d, Len = %d!!\n", dmem_pkt_size, iram_pkt_size, FWHeaderSize, Len);
532
533
/* download rsvd page. */
534
/* RsvdPageNum = GetTxBufferRsvdPageNum8814A(Adapter, _FALSE); */
535
#ifdef CONFIG_BCN_IC
536
/* TODO: check tx buffer and DMA size */
537
MaxRsvdPageBufSize = MAX_CMDBUF_SZ - TXDESC_OFFSET;
538
#else
539
MaxRsvdPageBufSize = MAX_XMIT_EXTBUF_SZ - TXDESC_OFFSET;/* RsvdPageNum*PageSize - 40 -16 modified for usb; */ /* TX_INFO_SIZE_8814AE; */
540
#endif
541
RTW_INFO("MaxRsvdPageBufSize %d, Total len %d\n", MaxRsvdPageBufSize, Len);
542
543
BeaconHeaderInTxPacketBuf = txpktbuf_bndy * PageSize;
544
MEMOffsetInTxPacketBuf = OCPBASE_TXBUF_3081 + BeaconHeaderInTxPacketBuf + 40;/* TX_INFO_SIZE_8814AE; */
545
/* download DMEM */
546
while (dmem_pkt_size > 0) {
547
if (dmem_pkt_size > MaxRsvdPageBufSize) {
548
filesize_ram_block = MaxRsvdPageBufSize;
549
ls = _FALSE;
550
551
last_block_size = dmem_pkt_size - MaxRsvdPageBufSize;
552
if (last_block_size < MaxRsvdPageBufSize) {
553
if (((last_block_size + 40) & 0x3F) == 0) /* Multiples of 64 */
554
filesize_ram_block -= 4;
555
}
556
} else {
557
filesize_ram_block = dmem_pkt_size;
558
ls = _TRUE;
559
}
560
fs = (pkt_offset == 0 ? _TRUE : _FALSE);
561
/* Return Beacon TCB. */
562
/* ReturnBeaconQueueTcb_8814A(Adapter); */
563
/* RTW_INFO("%d packet offset %d dmem_pkt_size %d\n", __LINE__,pkt_offset, dmem_pkt_size); */
564
SetDownLoadFwRsvdPagePkt_8814A(Adapter, pbuffer + FWHeaderSize + pkt_offset, filesize_ram_block);
565
bDownLoadRSVDPageOK = WaitDownLoadRSVDPageOK_3081(Adapter);
566
if (!bDownLoadRSVDPageOK) {
567
RTW_INFO("ERROR: DMEM bDownLoadRSVDPageOK is false!!\n");
568
return;
569
}
570
571
IDDMADownLoadFW_3081(Adapter, MEMOffsetInTxPacketBuf, OCPBASE_DMEM_3081 + pkt_offset, filesize_ram_block, fs, ls);
572
dmem_pkt_size -= filesize_ram_block;
573
pkt_offset += filesize_ram_block;
574
}
575
576
/* download IRAM */
577
pkt_offset = 0;
578
while (iram_pkt_size > 0) {
579
if (iram_pkt_size > MaxRsvdPageBufSize) {
580
filesize_ram_block = MaxRsvdPageBufSize;
581
ls = _FALSE;
582
583
last_block_size = iram_pkt_size - MaxRsvdPageBufSize;
584
if (last_block_size < MaxRsvdPageBufSize) {
585
if (((last_block_size + 40) & 0x3F) == 0) /* Multiples of 64 */
586
filesize_ram_block -= 4;
587
}
588
} else {
589
filesize_ram_block = iram_pkt_size;
590
ls = _TRUE;
591
}
592
593
fs = (pkt_offset == 0 ? _TRUE : _FALSE);
594
/* Return Beacon TCB. */
595
/* ReturnBeaconQueueTcb_8814A(Adapter); */
596
/* RTW_INFO("%d packet offset %d iram_pkt_size %d\n", __LINE__,pkt_offset, iram_pkt_size); */
597
SetDownLoadFwRsvdPagePkt_8814A(Adapter, pbuffer + Len - iram_pkt_size, filesize_ram_block);
598
599
bDownLoadRSVDPageOK = WaitDownLoadRSVDPageOK_3081(Adapter);
600
if (!bDownLoadRSVDPageOK) {
601
RTW_INFO("ERROR: IRAM bDownLoadRSVDPageOK is false!!\n");
602
return;
603
}
604
605
IDDMADownLoadFW_3081(Adapter, MEMOffsetInTxPacketBuf, OCPBASE_IMEM_3081 + pkt_offset, filesize_ram_block, fs, ls);
606
607
iram_pkt_size -= filesize_ram_block;
608
pkt_offset += filesize_ram_block;
609
}
610
611
/* restore bcn_ctrl */
612
rtw_write8(Adapter, REG_BCN_CTRL, bcn_ctrl);
613
614
/* To make sure that if there exists an adapter which would like to send beacon. */
615
/* If exists, the origianl value of 0x422[6] will be 1, we should check this to */
616
/* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
617
/* the beacon cannot be sent by HW. */
618
/* 2010.06.23. Added by tynli. */
619
if (bSendBeacon)
620
rtw_write8(Adapter, REG_FWHW_TXQ_CTRL_8814A + 2, tmpReg422);
621
622
/* Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli. */
623
/* if(!Adapter->bEnterPnpSleep) */
624
{
625
/* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
626
u1bTmp = rtw_read8(Adapter, REG_CR_8814A + 1);
627
rtw_write8(Adapter, REG_CR_8814A + 1, (u1bTmp & (~BIT0)));
628
}
629
630
u1bTmp = rtw_read8(Adapter, REG_8051FW_CTRL_8814A); /* add by gw for flags to show the fw download ok 20130826 */
631
if (u1bTmp & DMEM_CHKSUM_OK) {
632
if (u1bTmp & IMEM_CHKSUM_OK) {
633
u8 tem;
634
tem = rtw_read8(Adapter, REG_8051FW_CTRL_8814A + 1);
635
rtw_write8(Adapter, REG_8051FW_CTRL_8814A + 1, (tem | BIT6));
636
}
637
}
638
}
639
640
s32
641
_FWFreeToGo8814A(
642
PADAPTER Adapter
643
)
644
{
645
u32 counter = 0;
646
u32 value32;
647
648
/* polling CheckSum report */
649
do {
650
rtw_mdelay_os(50);
651
value32 = rtw_read32(Adapter, REG_8051FW_CTRL_8814A);
652
653
} while ((counter++ < 100) && (!(value32 & CPU_DL_READY)));
654
655
if (counter >= 100) {
656
return _FAIL;
657
}
658
659
660
return _SUCCESS;
661
}
662
663
664
#ifdef CONFIG_FILE_FWIMG
665
u8 FwBuffer8814[FW_SIZE];
666
#endif /* CONFIG_FILE_FWIMG */
667
668
s32
669
FirmwareDownload8814A(
670
PADAPTER Adapter,
671
BOOLEAN bUsedWoWLANFw
672
)
673
{
674
s32 rtStatus = _SUCCESS;
675
u8 write_fw = 0;
676
systime fwdl_start_time;
677
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
678
679
u8 *pFwImageFileName;
680
u8 *pucMappedFile = NULL;
681
PRT_FIRMWARE_8814 pFirmware = NULL;
682
u8 *pFwHdr = NULL;
683
u8 *pFirmwareBuf;
684
u32 FirmwareLen;
685
#ifdef CONFIG_FILE_FWIMG
686
u8 *fwfilepath;
687
#endif
688
u32 u32tmp;
689
690
691
pFirmware = (PRT_FIRMWARE_8814)rtw_zmalloc(sizeof(RT_FIRMWARE_8814));
692
if (!pFirmware) {
693
rtStatus = _FAIL;
694
goto exit;
695
}
696
697
#ifdef CONFIG_FILE_FWIMG
698
#ifdef CONFIG_WOWLAN
699
if (bUsedWoWLANFw)
700
fwfilepath = rtw_fw_wow_file_path;
701
else
702
#endif /* CONFIG_WOWLAN */
703
{
704
fwfilepath = rtw_fw_file_path;
705
}
706
707
if (rtw_is_file_readable(fwfilepath) == _TRUE) {
708
RTW_INFO("%s acquire FW from file:%s\n", __FUNCTION__, fwfilepath);
709
pFirmware->eFWSource = FW_SOURCE_IMG_FILE;
710
} else
711
#endif /* CONFIG_FILE_FWIMG */
712
{
713
RTW_INFO("%s fw source from Header\n", __FUNCTION__);
714
pFirmware->eFWSource = FW_SOURCE_HEADER_FILE;
715
}
716
717
switch (pFirmware->eFWSource) {
718
case FW_SOURCE_IMG_FILE:
719
#ifdef CONFIG_FILE_FWIMG
720
rtStatus = rtw_retrieve_from_file(fwfilepath, FwBuffer8814, FW_SIZE);
721
pFirmware->ulFwLength = rtStatus >= 0 ? rtStatus : 0;
722
pFirmware->szFwBuffer = FwBuffer8814;
723
RTW_INFO("%s fw size: %d\n", __FUNCTION__, pFirmware->ulFwLength);
724
#endif /* CONFIG_FILE_FWIMG */
725
break;
726
case FW_SOURCE_HEADER_FILE:
727
if (bUsedWoWLANFw) {
728
#ifdef CONFIG_WOWLAN
729
pFirmware->szFwBuffer = array_mp_8814a_fw_wowlan;
730
pFirmware->ulFwLength = array_length_mp_8814a_fw_wowlan;
731
RTW_INFO("%s fw:%s, size: %d\n", __FUNCTION__, "WoWLAN", pFirmware->ulFwLength);
732
#endif /* CONFIG_WOWLAN */
733
} else {
734
pFirmware->szFwBuffer = array_mp_8814a_fw_nic;
735
pFirmware->ulFwLength = array_length_mp_8814a_fw_nic;
736
RTW_INFO("%s fw:%s, size: %d\n", __FUNCTION__, "NIC", pFirmware->ulFwLength);
737
}
738
break;
739
}
740
741
if (pFirmware->ulFwLength == 0) {
742
RTW_ERR("Firmware size:%u\n", pFirmware->ulFwLength);
743
goto exit;
744
}
745
746
if ((pFirmware->ulFwLength - 64) > FW_SIZE) {
747
rtStatus = _FAIL;
748
RTW_ERR("Firmware size:%u exceed %u\n", pFirmware->ulFwLength, FW_SIZE);
749
goto exit;
750
}
751
752
pFirmwareBuf = pFirmware->szFwBuffer;
753
FirmwareLen = pFirmware->ulFwLength;
754
pFwHdr = (u8 *)pFirmware->szFwBuffer;
755
756
pHalData->firmware_version = (u16)GET_FIRMWARE_HDR_VERSION_3081(pFwHdr);
757
pHalData->firmware_sub_version = (u16)GET_FIRMWARE_HDR_SUB_VER_3081(pFwHdr);
758
pHalData->FirmwareSignature = (u16)GET_FIRMWARE_HDR_SIGNATURE_3081(pFwHdr);
759
760
RTW_INFO("%s: fw_ver=%d fw_subver=%d sig=0x%x\n",
761
__FUNCTION__, pHalData->firmware_version, pHalData->firmware_sub_version, pHalData->FirmwareSignature);
762
fwdl_start_time = rtw_get_current_time();
763
764
_FWDownloadEnable_8814A(Adapter, _TRUE);
765
766
_3081Disable8814A(Adapter);/* add by gw 2013026 for disable mcu core */
767
768
/* DDMA reset, suggest by MAC yodar */
769
u32tmp = rtw_read32(Adapter, REG_CPU_DMEM_CON_8814A);
770
rtw_write32(Adapter, REG_CPU_DMEM_CON_8814A, u32tmp&(~BIT16));
771
rtw_write32(Adapter, REG_CPU_DMEM_CON_8814A, u32tmp | BIT16);
772
773
HalROMDownloadFWRSVDPage8814A(Adapter, pFirmwareBuf, FirmwareLen);
774
775
_3081Enable8814A(Adapter);/* add by gw 2013026 for Enable mcu core */
776
777
_FWDownloadEnable_8814A(Adapter, _FALSE);
778
779
rtStatus = _FWFreeToGo8814A(Adapter);
780
if (_SUCCESS != rtStatus)
781
goto fwdl_stat;
782
783
fwdl_stat:
784
RTW_INFO("FWDL %s. write_fw:%u, %dms\n"
785
, (rtStatus == _SUCCESS) ? "success" : "fail"
786
, write_fw
787
, rtw_get_passing_time_ms(fwdl_start_time)
788
);
789
790
exit:
791
if (pFirmware)
792
rtw_mfree((u8 *)pFirmware, sizeof(RT_FIRMWARE_8814));
793
794
InitializeFirmwareVars8814(Adapter);
795
796
return rtStatus;
797
}
798
799
800
801
void InitializeFirmwareVars8814(PADAPTER padapter)
802
{
803
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
804
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
805
806
/* Init Fw LPS related. */
807
pwrpriv->bFwCurrentInPSMode = _FALSE;
808
809
/* Init H2C cmd.*/
810
rtw_write8(padapter, REG_HMETFR_8814A, 0x0f);
811
812
/* Init H2C counter. by tynli. 2009.12.09. */
813
pHalData->LastHMEBoxNum = 0;
814
}
815
816
#if 0
817
/* */
818
/* Description: Determine the contents of H2C BT_FW_PATCH Command sent to FW. */
819
/* 2013.01.23 by tynli */
820
/* Porting from 8723B. 2013.04.01 */
821
/* */
822
void
823
SetFwBTFwPatchCmd(
824
PADAPTER Adapter,
825
u16 FwSize
826
)
827
{
828
u8 u1BTFwPatchParm[6] = {0};
829
830
RTW_INFO("SetFwBTFwPatchCmd_8821(): FwSize = %d\n", FwSize);
831
832
/* SET_8812_H2CCMD_BT_FW_PATCH_ENABLE(u1BTFwPatchParm, 1); */
833
SET_H2CCMD_BT_FW_PATCH_SIZE(u1BTFwPatchParm, FwSize);
834
SET_H2CCMD_BT_FW_PATCH_ADDR0(u1BTFwPatchParm, 0);
835
SET_H2CCMD_BT_FW_PATCH_ADDR1(u1BTFwPatchParm, 0xa0);
836
SET_H2CCMD_BT_FW_PATCH_ADDR2(u1BTFwPatchParm, 0x10);
837
SET_H2CCMD_BT_FW_PATCH_ADDR3(u1BTFwPatchParm, 0x80);
838
839
fill_h2c_cmd_8812(Adapter, H2C_BT_FW_PATCH, 6 , u1BTFwPatchParm);
840
}
841
842
843
int ReservedPage_Compare(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware, u32 BTPatchSize)
844
{
845
u8 temp, ret, lastBTsz;
846
u32 u1bTmp = 0, address_start = 0, count = 0, i = 0;
847
u8 *myBTFwBuffer = NULL;
848
849
myBTFwBuffer = rtw_zmalloc(BTPatchSize);
850
if (myBTFwBuffer == NULL) {
851
RTW_INFO("%s can't be executed due to the failed malloc.\n", __FUNCTION__);
852
Adapter->mppriv.bTxBufCkFail = _TRUE;
853
return _FALSE;
854
}
855
856
temp = rtw_read8(Adapter, 0x209);
857
858
address_start = (temp * 128) / 8;
859
860
rtw_write32(Adapter, 0x140, 0x00000000);
861
rtw_write32(Adapter, 0x144, 0x00000000);
862
rtw_write32(Adapter, 0x148, 0x00000000);
863
864
rtw_write8(Adapter, 0x106, 0x69);
865
866
867
for (i = 0; i < (BTPatchSize / 8); i++) {
868
rtw_write32(Adapter, 0x140, address_start + 5 + i) ;
869
870
/* polling until reg 0x140[23]=1; */
871
do {
872
u1bTmp = rtw_read32(Adapter, 0x140);
873
if (u1bTmp & BIT(23)) {
874
ret = _SUCCESS;
875
break;
876
}
877
count++;
878
RTW_INFO("0x140=%x, wait for 10 ms (%d) times.\n", u1bTmp, count);
879
rtw_msleep_os(10); /* 10ms */
880
} while (!(u1bTmp & BIT(23)) && count < 50);
881
882
myBTFwBuffer[i * 8 + 0] = rtw_read8(Adapter, 0x144);
883
myBTFwBuffer[i * 8 + 1] = rtw_read8(Adapter, 0x145);
884
myBTFwBuffer[i * 8 + 2] = rtw_read8(Adapter, 0x146);
885
myBTFwBuffer[i * 8 + 3] = rtw_read8(Adapter, 0x147);
886
myBTFwBuffer[i * 8 + 4] = rtw_read8(Adapter, 0x148);
887
myBTFwBuffer[i * 8 + 5] = rtw_read8(Adapter, 0x149);
888
myBTFwBuffer[i * 8 + 6] = rtw_read8(Adapter, 0x14a);
889
myBTFwBuffer[i * 8 + 7] = rtw_read8(Adapter, 0x14b);
890
}
891
892
rtw_write32(Adapter, 0x140, address_start + 5 + BTPatchSize / 8) ;
893
894
lastBTsz = BTPatchSize % 8;
895
896
/* polling until reg 0x140[23]=1; */
897
u1bTmp = 0;
898
count = 0;
899
do {
900
u1bTmp = rtw_read32(Adapter, 0x140);
901
if (u1bTmp & BIT(23)) {
902
ret = _SUCCESS;
903
break;
904
}
905
count++;
906
RTW_INFO("0x140=%x, wait for 10 ms (%d) times.\n", u1bTmp, count);
907
rtw_msleep_os(10); /* 10ms */
908
} while (!(u1bTmp & BIT(23)) && count < 50);
909
910
for (i = 0; i < lastBTsz; i++)
911
myBTFwBuffer[(BTPatchSize / 8) * 8 + i] = rtw_read8(Adapter, (0x144 + i));
912
913
914
for (i = 0; i < BTPatchSize; i++) {
915
if (myBTFwBuffer[i] != pFirmware->szFwBuffer[i]) {
916
RTW_INFO(" In direct myBTFwBuffer[%d]=%x , pFirmware->szFwBuffer=%x\n", i, myBTFwBuffer[i], pFirmware->szFwBuffer[i]);
917
Adapter->mppriv.bTxBufCkFail = _TRUE;
918
break;
919
}
920
}
921
922
if (myBTFwBuffer != NULL)
923
rtw_mfree(myBTFwBuffer, BTPatchSize);
924
925
return _TRUE;
926
}
927
928
#ifdef CONFIG_RTL8821A
929
s32 FirmwareDownloadBT(PADAPTER padapter, PRT_MP_FIRMWARE pFirmware)
930
{
931
s32 rtStatus;
932
u8 *pBTFirmwareBuf;
933
u32 BTFirmwareLen;
934
u8 download_time;
935
s8 i;
936
937
938
rtStatus = _SUCCESS;
939
pBTFirmwareBuf = NULL;
940
BTFirmwareLen = 0;
941
942
/* */
943
/* Patch BT Fw. Download BT RAM code to Tx packet buffer. */
944
/* */
945
if (GET_HAL_DATA(padapter)->bBTFWReady) {
946
RTW_INFO("%s: BT Firmware is ready!!\n", __FUNCTION__);
947
return _FAIL;
948
}
949
950
#ifdef CONFIG_FILE_FWIMG
951
if (rtw_is_file_readable(rtw_fw_mp_bt_file_path) == _TRUE) {
952
RTW_INFO("%s: accquire MP BT FW from file:%s\n", __FUNCTION__, rtw_fw_mp_bt_file_path);
953
954
rtStatus = rtw_retrieve_from_file(rtw_fw_mp_bt_file_path, FwBuffer, 0x8000);
955
BTFirmwareLen = rtStatus >= 0 ? rtStatus : 0;
956
pBTFirmwareBuf = FwBuffer;
957
} else
958
#endif /* CONFIG_FILE_FWIMG */
959
{
960
#ifdef CONFIG_EMBEDDED_FWIMG
961
RTW_INFO("%s: Download MP BT FW from header\n", __FUNCTION__);
962
963
pBTFirmwareBuf = (u8 *)Rtl8821A_BT_MP_Patch_FW;
964
BTFirmwareLen = Rtl8812BFwBTImgArrayLength;
965
pFirmware->szFwBuffer = pBTFirmwareBuf;
966
pFirmware->ulFwLength = BTFirmwareLen;
967
#endif /* CONFIG_EMBEDDED_FWIMG */
968
}
969
970
RTW_INFO("%s: MP BT Firmware size=%d\n", __FUNCTION__, BTFirmwareLen);
971
972
/* for h2c cam here should be set to true */
973
GET_HAL_DATA(padapter)->bFWReady = _TRUE;
974
975
download_time = (BTFirmwareLen + 4095) / 4096;
976
RTW_INFO("%s: download_time is %d\n", __FUNCTION__, download_time);
977
978
/* Download BT patch Fw. */
979
for (i = (download_time - 1); i >= 0; i--) {
980
if (i == (download_time - 1)) {
981
rtStatus = _WriteBTFWtoTxPktBuf8812(padapter, pBTFirmwareBuf + (4096 * i), (BTFirmwareLen - (4096 * i)), 1);
982
RTW_INFO("%s: start %d, len %d, time 1\n", __FUNCTION__, 4096 * i, BTFirmwareLen - (4096 * i));
983
} else {
984
rtStatus = _WriteBTFWtoTxPktBuf8812(padapter, pBTFirmwareBuf + (4096 * i), 4096, (download_time - i));
985
RTW_INFO("%s: start %d, len 4096, time %d\n", __FUNCTION__, 4096 * i, download_time - i);
986
}
987
988
if (rtStatus != _SUCCESS) {
989
RTW_INFO("%s: BT Firmware download to Tx packet buffer fail!\n", __FUNCTION__);
990
GET_HAL_DATA(padapter)->bBTFWReady = _FALSE;
991
return rtStatus;
992
}
993
}
994
995
ReservedPage_Compare(padapter, pFirmware, BTFirmwareLen);
996
997
GET_HAL_DATA(padapter)->bBTFWReady = _TRUE;
998
SetFwBTFwPatchCmd_8821(padapter, (u16)BTFirmwareLen);
999
rtStatus = _CheckWLANFwPatchBTFwReady_8821A(padapter);
1000
1001
RTW_INFO("<===%s: return %s!\n", __FUNCTION__, rtStatus == _SUCCESS ? "SUCCESS" : "FAIL");
1002
return rtStatus;
1003
}
1004
#endif /* CONFIG_RTL8821A */
1005
#endif
1006
1007
/* ***********************************************************
1008
* Efuse related code
1009
* *********************************************************** */
1010
void
1011
hal_EfuseParseBTCoexistInfo8814A(
1012
PADAPTER Adapter,
1013
u8 *hwinfo,
1014
BOOLEAN AutoLoadFail
1015
)
1016
{
1017
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1018
u8 tempval = 0x0;
1019
1020
if (!AutoLoadFail) {
1021
tempval = hwinfo[EEPROM_RF_BOARD_OPTION_8814];
1022
if (((tempval & 0xe0) >> 5) == 0x1) /* [7:5] */
1023
pHalData->EEPROMBluetoothCoexist = 1;
1024
else
1025
pHalData->EEPROMBluetoothCoexist = 0;
1026
pHalData->EEPROMBluetoothType = BT_RTL8814A;
1027
1028
tempval = hwinfo[EEPROM_RF_BT_SETTING_8814];
1029
if (tempval != 0xFF)
1030
pHalData->EEPROMBluetoothAntNum = (tempval&0x1) ? Ant_x1 : Ant_x2;
1031
} else {
1032
pHalData->EEPROMBluetoothCoexist = 0;
1033
pHalData->EEPROMBluetoothType = BT_RTL8814A;
1034
pHalData->EEPROMBluetoothAntNum = Ant_x1;
1035
}
1036
1037
RTW_INFO("EEPROMBluetoothCoexist = %d, EEPROMBluetoothAntNum = %s\n",
1038
pHalData->EEPROMBluetoothCoexist,
1039
(pHalData->EEPROMBluetoothAntNum == Ant_x1) ? "Ant_x1" : "Ant_x2");
1040
}
1041
1042
void
1043
hal_ReadPROMVersion8814A(
1044
PADAPTER Adapter,
1045
u8 *PROMContent,
1046
BOOLEAN AutoloadFail
1047
)
1048
{
1049
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1050
1051
if (AutoloadFail)
1052
pHalData->EEPROMVersion = EEPROM_Default_Version;
1053
else {
1054
pHalData->EEPROMVersion = *(u8 *)&PROMContent[EEPROM_VERSION_8814];
1055
if (pHalData->EEPROMVersion == 0xFF)
1056
pHalData->EEPROMVersion = EEPROM_Default_Version;
1057
}
1058
}
1059
1060
void
1061
hal_ReadTxPowerInfo8814A(
1062
PADAPTER Adapter,
1063
u8 *PROMContent,
1064
BOOLEAN AutoLoadFail
1065
)
1066
{
1067
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1068
1069
/* 2010/10/19 MH Add Regulator recognize for CU. */
1070
if (!AutoLoadFail) {
1071
struct registry_priv *registry_par = &Adapter->registrypriv;
1072
1073
pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_8814] & 0x7); /* bit0~2 */
1074
if (PROMContent[EEPROM_RF_BOARD_OPTION_8814] == 0xFF)
1075
pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION & 0x7); /* bit0~2 */
1076
} else
1077
pHalData->EEPROMRegulatory = 0;
1078
1079
RTW_INFO("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory);
1080
1081
}
1082
1083
void
1084
hal_ReadBoardType8814A(
1085
PADAPTER Adapter,
1086
u8 *PROMContent,
1087
BOOLEAN AutoloadFail
1088
)
1089
{
1090
1091
1092
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1093
1094
if (!AutoloadFail) {
1095
pHalData->InterfaceSel = (PROMContent[EEPROM_RF_BOARD_OPTION_8814] & 0xE0) >> 5;
1096
if (PROMContent[EEPROM_RF_BOARD_OPTION_8814] == 0xFF)
1097
pHalData->InterfaceSel = (EEPROM_DEFAULT_BOARD_OPTION & 0xE0) >> 5;
1098
} else
1099
pHalData->InterfaceSel = 0;
1100
}
1101
1102
enum rf_type rtl8814a_rfpath_decision(_adapter *adapter)
1103
{
1104
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1105
struct registry_priv *regpriv = &adapter->registrypriv;
1106
enum rf_type rf_path = RF_TYPE_MAX;
1107
u8 trx_antenna;
1108
1109
if (!hal_data->bautoload_fail_flag) {
1110
u8 option = hal_data->efuse_eeprom_data[EEPROM_TRX_ANTENNA_OPTION_8814];
1111
1112
if (option == 0xff) {
1113
trx_antenna = RF_4T4R;
1114
RTW_INFO("EEPROM RF set 4T4R\n");
1115
} else if (option == 0xee) {
1116
trx_antenna = RF_3T3R;
1117
RTW_INFO("EEPROM RF set 3T3R\n");
1118
} else if (option == 0x66) {
1119
trx_antenna = RF_2T2R;
1120
RTW_INFO("EEPROM RF set 2T2R\n");
1121
} else if (option == 0x6f) {
1122
trx_antenna = RF_2T4R;
1123
RTW_INFO("EEPROM RF set 2T4R\n");
1124
} else {
1125
trx_antenna = RF_2T4R;
1126
RTW_INFO("unknown EEPROM RF set, default to 2T4R\n");
1127
}
1128
} else {
1129
trx_antenna = RF_2T4R;
1130
RTW_INFO("AutoloadFail, default to 2T4R\n");
1131
}
1132
1133
/* if driver doesn't set rf_path in registry, use the value of EEPROM */
1134
if (!RF_TYPE_VALID(regpriv->rf_path)) {
1135
if ((trx_antenna == RF_4T4R || trx_antenna == RF_3T3R)
1136
#ifdef CONFIG_USB_HCI
1137
&& IS_SUPER_SPEED_USB(adapter)
1138
#endif
1139
)
1140
rf_path = RF_3T3R;
1141
else if (trx_antenna == RF_2T4R)
1142
rf_path = RF_2T4R;
1143
else {
1144
rf_path = RF_2T4R;
1145
RTW_INFO("default rf type: %d\n", rf_path);
1146
}
1147
} else {
1148
rf_path = regpriv->rf_path;
1149
#ifdef CONFIG_USB_HCI
1150
if (!IS_SUPER_SPEED_USB(adapter))
1151
rf_path = RF_2T4R;
1152
#endif
1153
}
1154
1155
RTW_INFO("[8814A] Final rf_config: %d\n", rf_path);
1156
1157
return rf_path;
1158
}
1159
1160
void
1161
hal_Read_TRX_antenna_8814A(
1162
PADAPTER Adapter,
1163
u8 *PROMContent,
1164
BOOLEAN AutoloadFail
1165
)
1166
{
1167
/* move to rtl8814a_rfpath_decision */
1168
}
1169
1170
void
1171
hal_ReadThermalMeter_8814A(
1172
PADAPTER Adapter,
1173
u8 *PROMContent,
1174
BOOLEAN AutoloadFail
1175
)
1176
{
1177
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1178
1179
pHalData->eeprom_thermal_meter = 0xff;
1180
1181
if (!AutoloadFail)
1182
pHalData->eeprom_thermal_meter = PROMContent[EEPROM_THERMAL_METER_8814];
1183
1184
#if 0 /* ToDo: check with RF */
1185
else
1186
pHalData->eeprom_thermal_meter = EEPROM_Default_ThermalMeter_8814A;
1187
1188
if ((pHalData->eeprom_thermal_meter == 0xff) || (_TRUE == AutoloadFail)) {
1189
pHalData->odmpriv.RFCalibrateInfo.bAPKThermalMeterIgnore = _TRUE;
1190
pHalData->eeprom_thermal_meter = EEPROM_Default_ThermalMeter_8814A;
1191
}
1192
#endif
1193
1194
/* pHalData->ThermalMeter[0] = pHalData->eeprom_thermal_meter; */
1195
RTW_INFO("ThermalMeter = 0x%x\n", pHalData->eeprom_thermal_meter);
1196
}
1197
1198
1199
void hal_ReadRemoteWakeup_8814A(
1200
PADAPTER padapter,
1201
u8 *hwinfo,
1202
BOOLEAN AutoLoadFail
1203
)
1204
{
1205
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
1206
struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
1207
u8 tmpvalue;
1208
1209
if (AutoLoadFail) {
1210
pwrctl->bHWPowerdown = _FALSE;
1211
pwrctl->bSupportRemoteWakeup = _FALSE;
1212
} else {
1213
/* decide hw if support remote wakeup function */
1214
/* if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume */
1215
#if 0
1216
/* todo: wowlan should check the efuse again */
1217
#ifdef CONFIG_USB_HCI
1218
if (IS_HARDWARE_TYPE_8821U(padapter))
1219
pwrctl->bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0_8811AU] & BIT1) ? _TRUE : _FALSE;
1220
else
1221
pwrctl->bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT1) ? _TRUE : _FALSE;
1222
#endif /* CONFIG_USB_HCI */
1223
#endif
1224
RTW_INFO("%s...bSupportRemoteWakeup(%x)\n", __FUNCTION__, pwrctl->bSupportRemoteWakeup);
1225
}
1226
}
1227
1228
void
1229
hal_ReadChannelPlan8814A(
1230
PADAPTER padapter,
1231
u8 *hwinfo,
1232
BOOLEAN AutoLoadFail
1233
)
1234
{
1235
hal_com_config_channel_plan(
1236
padapter
1237
, hwinfo ? &hwinfo[EEPROM_COUNTRY_CODE_8814] : NULL
1238
, hwinfo ? hwinfo[EEPROM_ChannelPlan_8814] : 0xFF
1239
, padapter->registrypriv.alpha2
1240
, padapter->registrypriv.channel_plan
1241
, RTW_CHPLAN_REALTEK_DEFINE
1242
, AutoLoadFail
1243
);
1244
}
1245
1246
void hal_GetRxGainOffset_8814A(
1247
PADAPTER Adapter,
1248
u8 *PROMContent,
1249
BOOLEAN AutoloadFail
1250
)
1251
{
1252
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1253
struct registry_priv *pregistrypriv = &Adapter->registrypriv;
1254
1255
pHalData->RxGainOffset[0] = 0;
1256
pHalData->RxGainOffset[1] = 0;
1257
pHalData->RxGainOffset[2] = 0;
1258
pHalData->RxGainOffset[3] = 0;
1259
1260
if (((pregistrypriv->reg_rxgain_offset_2g != 0) && (pregistrypriv->reg_rxgain_offset_5gl != 0)) &&
1261
((pregistrypriv->reg_rxgain_offset_5gm != 0) && (pregistrypriv->reg_rxgain_offset_5gh != 0))) {
1262
1263
pHalData->RxGainOffset[0] = pregistrypriv->reg_rxgain_offset_2g;
1264
pHalData->RxGainOffset[1] = pregistrypriv->reg_rxgain_offset_5gl;
1265
pHalData->RxGainOffset[2] = pregistrypriv->reg_rxgain_offset_5gm;
1266
pHalData->RxGainOffset[3] = pregistrypriv->reg_rxgain_offset_5gh;
1267
RTW_INFO("%s():Use registrypriv 0x%x 0x%x 0x%x 0x%x !!\n", __func__, pregistrypriv->reg_rxgain_offset_2g, pregistrypriv->reg_rxgain_offset_5gl, pregistrypriv->reg_rxgain_offset_5gm,
1268
pregistrypriv->reg_rxgain_offset_5gh);
1269
1270
} else {
1271
RTW_INFO("%s(): AutoloadFail = %d!!\n", __func__, AutoloadFail);
1272
pHalData->RxGainOffset[0] = PROMContent[EEPROM_IG_OFFSET_4_CD_2G_8814A];
1273
pHalData->RxGainOffset[0] |= (PROMContent[EEPROM_IG_OFFSET_4_AB_2G_8814A]) << 8;
1274
pHalData->RxGainOffset[1] = PROMContent[EEPROM_IG_OFFSET_4_CD_5GL_8814A];
1275
pHalData->RxGainOffset[1] |= (PROMContent[EEPROM_IG_OFFSET_4_AB_5GL_8814A]) << 8;
1276
pHalData->RxGainOffset[2] = PROMContent[EEPROM_IG_OFFSET_4_CD_5GM_8814A];
1277
pHalData->RxGainOffset[2] |= (PROMContent[EEPROM_IG_OFFSET_4_AB_5GM_8814A]) << 8;
1278
pHalData->RxGainOffset[3] = PROMContent[EEPROM_IG_OFFSET_4_CD_5GH_8814A];
1279
pHalData->RxGainOffset[3] |= (PROMContent[EEPROM_IG_OFFSET_4_AB_5GH_8814A]) << 8;
1280
}
1281
RTW_INFO("hal_GetRxGainOffset_8814A(): RegRxGainOffset_2G = 0x%x!!\n", pHalData->RxGainOffset[0]);
1282
RTW_INFO("hal_GetRxGainOffset_8814A(): RegRxGainOffset_5GL = 0x%x!!\n", pHalData->RxGainOffset[1]);
1283
RTW_INFO("hal_GetRxGainOffset_8814A(): RegRxGainOffset_5GM = 0x%x!!\n", pHalData->RxGainOffset[2]);
1284
RTW_INFO("hal_GetRxGainOffset_8814A(): RegRxGainOffset_5GH = 0x%x!!\n", pHalData->RxGainOffset[3]);
1285
}
1286
1287
1288
void Hal_EfuseParseKFreeData_8814A(
1289
PADAPTER Adapter,
1290
u8 *PROMContent,
1291
BOOLEAN AutoloadFail)
1292
{
1293
#ifdef CONFIG_RF_POWER_TRIM
1294
1295
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1296
struct kfree_data_t *kfree_data = &pHalData->kfree_data;
1297
u8 kfreePhydata[KFREE_GAIN_DATA_LENGTH_8814A];
1298
u32 i = 0, j = 2, chidx = 0, efuseaddr = 0;
1299
u8 rfpath = 0;
1300
1301
if (GET_PG_KFREE_ON_8814A(PROMContent) && PROMContent[0xc8] != 0xff)
1302
kfree_data->flag |= KFREE_FLAG_ON;
1303
if (GET_PG_KFREE_THERMAL_K_ON_8814A(PROMContent) && PROMContent[0xc8] != 0xff)
1304
kfree_data->flag |= KFREE_FLAG_THERMAL_K_ON;
1305
1306
if (Adapter->registrypriv.RegPwrTrimEnable == 1) {
1307
kfree_data->flag |= KFREE_FLAG_ON;
1308
kfree_data->flag |= KFREE_FLAG_THERMAL_K_ON;
1309
}
1310
1311
_rtw_memset(kfree_data->bb_gain, 0xff, BB_GAIN_NUM * RF_PATH_MAX);
1312
1313
if (kfree_data->flag & KFREE_FLAG_ON) {
1314
1315
for (i = 0; i < KFREE_GAIN_DATA_LENGTH_8814A; i++) {
1316
efuseaddr = PPG_BB_GAIN_2G_TXBA_OFFSET_8814A - i;
1317
1318
if (efuseaddr <= PPG_BB_GAIN_2G_TXBA_OFFSET_8814A) {
1319
efuse_OneByteRead(Adapter, efuseaddr, &kfreePhydata[i], _FALSE);
1320
RTW_INFO("%s,kfreePhydata[%d] = %x\n", __func__, i, kfreePhydata[i]);
1321
}
1322
}
1323
kfree_data->bb_gain[0][RF_PATH_A]
1324
= (kfreePhydata[0] & PPG_BB_GAIN_2G_TX_OFFSET_MASK);
1325
kfree_data->bb_gain[0][RF_PATH_B]
1326
= (kfreePhydata[0] & PPG_BB_GAIN_2G_TXB_OFFSET_MASK) >> 4;
1327
kfree_data->bb_gain[0][RF_PATH_C]
1328
= (kfreePhydata[1] & PPG_BB_GAIN_2G_TX_OFFSET_MASK);
1329
kfree_data->bb_gain[0][RF_PATH_D]
1330
= (kfreePhydata[1] & PPG_BB_GAIN_2G_TXB_OFFSET_MASK) >> 4;
1331
1332
for (chidx = 1; chidx <= BB_GAIN_5GHB; chidx++) {
1333
for (rfpath = RF_PATH_A; rfpath < RF_PATH_MAX; rfpath++)
1334
kfree_data->bb_gain[chidx][rfpath] = kfreePhydata[j + rfpath] & PPG_BB_GAIN_5G_TX_OFFSET_MASK;
1335
1336
j = j + RF_PATH_MAX;
1337
}
1338
}
1339
1340
if (kfree_data->flag & KFREE_FLAG_THERMAL_K_ON)
1341
pHalData->eeprom_thermal_meter += kfree_data->thermal;
1342
1343
RTW_INFO("registrypriv.RegPwrTrimEnable = %d\n", Adapter->registrypriv.RegPwrTrimEnable);
1344
1345
RTW_INFO("kfree flag:%u\n", kfree_data->flag);
1346
if (Adapter->registrypriv.RegPwrTrimEnable == 1 || kfree_data->flag & KFREE_FLAG_ON) {
1347
for (chidx = 0 ; chidx <= BB_GAIN_5GHB; chidx++) {
1348
for (rfpath = RF_PATH_A; rfpath < RF_PATH_MAX; rfpath++)
1349
RTW_INFO("bb_gain[%d][%d]= %x\n", chidx, rfpath, kfree_data->bb_gain[chidx][rfpath]);
1350
}
1351
}
1352
1353
#endif /*CONFIG_RF_POWER_TRIM */
1354
}
1355
1356
1357
void
1358
hal_EfuseParseXtal_8814A(
1359
PADAPTER pAdapter,
1360
u8 *hwinfo,
1361
BOOLEAN AutoLoadFail
1362
)
1363
{
1364
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1365
1366
if (!AutoLoadFail) {
1367
pHalData->crystal_cap = hwinfo[EEPROM_XTAL_8814];
1368
if (pHalData->crystal_cap == 0xFF)
1369
pHalData->crystal_cap = EEPROM_Default_CrystalCap_8814; /* what value should 8814 set? */
1370
} else
1371
pHalData->crystal_cap = EEPROM_Default_CrystalCap_8814;
1372
RTW_INFO("crystal_cap: 0x%2x\n", pHalData->crystal_cap);
1373
}
1374
1375
void
1376
hal_ReadAntennaDiversity8814A(
1377
PADAPTER pAdapter,
1378
u8 *PROMContent,
1379
BOOLEAN AutoLoadFail
1380
)
1381
{
1382
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1383
1384
pHalData->AntDivCfg = 0;
1385
1386
RTW_INFO("SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
1387
pHalData->AntDivCfg, pHalData->TRxAntDivType);
1388
}
1389
1390
void
1391
hal_ReadPAType_8814A(
1392
PADAPTER Adapter,
1393
u8 *PROMContent,
1394
BOOLEAN AutoloadFail,
1395
u8 *pPAType,
1396
u8 *pLNAType
1397
)
1398
{
1399
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1400
u8 LNAType_AB, LNAType_CD;
1401
1402
if (!AutoloadFail) {
1403
u8 RFEType = PROMContent[EEPROM_RFE_OPTION_8814];
1404
1405
if (GetRegAmplifierType2G(Adapter) == 0) { /* AUTO */
1406
*pPAType = ReadLE1Byte(&PROMContent[EEPROM_PA_TYPE_8814]);
1407
1408
LNAType_AB = ReadLE1Byte(&PROMContent[EEPROM_LNA_TYPE_AB_2G_8814]);
1409
LNAType_CD = ReadLE1Byte(&PROMContent[EEPROM_LNA_TYPE_CD_2G_8814]);
1410
1411
if (*pPAType == 0xFF && RFEType == 0xFF)
1412
pHalData->ExternalPA_2G = (GetRegAmplifierType2G(Adapter) & ODM_BOARD_EXT_PA) ? 1 : 0;
1413
else
1414
pHalData->ExternalPA_2G = (*pPAType & BIT4) ? 1 : 0;
1415
1416
if (LNAType_AB == 0xFF)
1417
pHalData->ExternalLNA_2G = (GetRegAmplifierType2G(Adapter) & ODM_BOARD_EXT_LNA) ? 1 : 0;
1418
else
1419
pHalData->ExternalLNA_2G = (LNAType_AB & BIT3) ? 1 : 0;
1420
1421
*pLNAType = (LNAType_AB & BIT3) << 1 | (LNAType_AB & BIT7) >> 2 |
1422
(LNAType_CD & BIT3) << 3 | (LNAType_CD & BIT7);
1423
} else {
1424
pHalData->ExternalPA_2G = (GetRegAmplifierType2G(Adapter) & ODM_BOARD_EXT_PA) ? 1 : 0;
1425
pHalData->ExternalLNA_2G = (GetRegAmplifierType2G(Adapter) & ODM_BOARD_EXT_LNA) ? 1 : 0;
1426
}
1427
1428
if (GetRegAmplifierType5G(Adapter) == 0) { /* AUTO */
1429
LNAType_AB = ReadLE1Byte(&PROMContent[EEPROM_LNA_TYPE_AB_5G_8814]);
1430
LNAType_CD = ReadLE1Byte(&PROMContent[EEPROM_LNA_TYPE_CD_5G_8814]);
1431
1432
if (*pPAType == 0xFF && RFEType == 0xFF)
1433
pHalData->external_pa_5g = (GetRegAmplifierType5G(Adapter) & ODM_BOARD_EXT_PA) ? 1 : 0;
1434
else
1435
pHalData->external_pa_5g = (*pPAType & BIT0) ? 1 : 0;
1436
1437
if (LNAType_AB == 0xFF)
1438
pHalData->external_lna_5g = (GetRegAmplifierType5G(Adapter) & ODM_BOARD_EXT_LNA) ? 1 : 0;
1439
else
1440
pHalData->external_lna_5g = (LNAType_AB & BIT3) ? 1 : 0;
1441
1442
(*pLNAType) |= ((LNAType_AB & BIT3) >> 3 | (LNAType_AB & BIT7) >> 6 |
1443
(LNAType_CD & BIT3) >> 1 | (LNAType_CD & BIT7) >> 4);
1444
} else {
1445
pHalData->external_pa_5g = (GetRegAmplifierType5G(Adapter) & ODM_BOARD_EXT_PA_5G) ? 1 : 0;
1446
pHalData->external_lna_5g = (GetRegAmplifierType5G(Adapter) & ODM_BOARD_EXT_LNA_5G) ? 1 : 0;
1447
}
1448
} else {
1449
pHalData->ExternalPA_2G = EEPROM_Default_PAType;
1450
pHalData->external_pa_5g = 0xFF;
1451
pHalData->ExternalLNA_2G = EEPROM_Default_LNAType;
1452
pHalData->external_lna_5g = 0xFF;
1453
1454
if (GetRegAmplifierType2G(Adapter) == 0) {
1455
pHalData->ExternalPA_2G = 0;
1456
pHalData->ExternalLNA_2G = 0;
1457
} else {
1458
pHalData->ExternalPA_2G = (GetRegAmplifierType2G(Adapter) & ODM_BOARD_EXT_PA) ? 1 : 0;
1459
pHalData->ExternalLNA_2G = (GetRegAmplifierType2G(Adapter) & ODM_BOARD_EXT_LNA) ? 1 : 0;
1460
}
1461
if (GetRegAmplifierType5G(Adapter) == 0) {
1462
pHalData->external_pa_5g = 0;
1463
pHalData->external_lna_5g = 0;
1464
} else {
1465
pHalData->external_pa_5g = (GetRegAmplifierType5G(Adapter) & ODM_BOARD_EXT_PA_5G) ? 1 : 0;
1466
pHalData->external_lna_5g = (GetRegAmplifierType5G(Adapter) & ODM_BOARD_EXT_LNA_5G) ? 1 : 0;
1467
}
1468
}
1469
RTW_INFO("PAType is 0x%x, LNAType is 0x%x\n", *pPAType, *pLNAType);
1470
RTW_INFO("pHalData->ExternalPA_2G = %d, pHalData->external_pa_5g = %d\n", pHalData->ExternalPA_2G, pHalData->external_pa_5g);
1471
RTW_INFO("pHalData->ExternalLNA_2G = %d, pHalData->external_lna_5g = %d\n", pHalData->ExternalLNA_2G, pHalData->external_lna_5g);
1472
}
1473
1474
void hal_ReadAmplifierType_8814A(
1475
PADAPTER Adapter
1476
)
1477
{
1478
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1479
switch (pHalData->rfe_type) {
1480
case 1: /* 8814AU */
1481
pHalData->external_pa_5g = pHalData->external_lna_5g = _TRUE;
1482
pHalData->TypeAPA = pHalData->TypeALNA = 0;/* APA and ALNA is 0 */
1483
break;
1484
case 2: /* socket board 8814AR and 8194AR */
1485
pHalData->ExternalPA_2G = pHalData->external_pa_5g = _TRUE;
1486
pHalData->ExternalLNA_2G = pHalData->external_lna_5g = _TRUE;
1487
pHalData->TypeAPA = pHalData->TypeALNA = 0x55;/* APA and ALNA is 1 */
1488
pHalData->TypeGPA = pHalData->TypeGLNA = 0x55;/* GPA and GLNA is 1 */
1489
break;
1490
case 3: /* high power on-board 8814AR and 8194AR */
1491
pHalData->ExternalPA_2G = pHalData->external_pa_5g = _TRUE;
1492
pHalData->ExternalLNA_2G = pHalData->external_lna_5g = _TRUE;
1493
pHalData->TypeAPA = pHalData->TypeALNA = 0xaa;/* APA and ALNA is 2 */
1494
pHalData->TypeGPA = pHalData->TypeGLNA = 0xaa;/* GPA and GLNA is 2 */
1495
break;
1496
case 4: /* on-board 8814AR and 8194AR */
1497
pHalData->ExternalPA_2G = pHalData->external_pa_5g = _TRUE;
1498
pHalData->ExternalLNA_2G = pHalData->external_lna_5g = _TRUE;
1499
pHalData->TypeAPA = 0x55;/* APA is 1 */
1500
pHalData->TypeALNA = 0xff; /* ALNA is 3 */
1501
pHalData->TypeGPA = pHalData->TypeGLNA = 0x55;/* GPA and GLNA is 1 */
1502
break;
1503
case 5:
1504
pHalData->ExternalPA_2G = pHalData->external_pa_5g = _TRUE;
1505
pHalData->ExternalLNA_2G = pHalData->external_lna_5g = _TRUE;
1506
pHalData->TypeAPA = 0xaa; /* APA2 */
1507
pHalData->TypeALNA = 0x5500; /* ALNA4 */
1508
pHalData->TypeGPA = pHalData->TypeGLNA = 0xaa; /* GPA2,GLNA2 */
1509
break;
1510
case 6:
1511
pHalData->external_lna_5g = _TRUE;
1512
pHalData->TypeALNA = 0; /* ALNA0 */
1513
break;
1514
case 0:
1515
default: /* 8814AE */
1516
break;
1517
}
1518
1519
RTW_INFO("pHalData->ExternalPA_2G = %d, pHalData->external_pa_5g = %d\n", pHalData->ExternalPA_2G, pHalData->external_pa_5g);
1520
RTW_INFO("pHalData->ExternalLNA_2G = %d, pHalData->external_lna_5g = %d\n", pHalData->ExternalLNA_2G, pHalData->external_lna_5g);
1521
RTW_INFO("pHalData->TypeGPA = 0x%X, pHalData->TypeAPA = 0x%X\n", pHalData->TypeGPA, pHalData->TypeAPA);
1522
RTW_INFO("pHalData->TypeGLNA = 0x%X, pHalData->TypeALNA = 0x%X\n", pHalData->TypeGLNA, pHalData->TypeALNA);
1523
}
1524
1525
1526
void
1527
hal_ReadRFEType_8814A(
1528
PADAPTER Adapter,
1529
u8 *PROMContent,
1530
BOOLEAN AutoloadFail
1531
)
1532
{
1533
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1534
1535
if (!AutoloadFail) {
1536
if ((GetRegRFEType(Adapter) != 64) || 0xFF == PROMContent[EEPROM_RFE_OPTION_8814] || PROMContent[EEPROM_RFE_OPTION_8814] & BIT7) {
1537
if (GetRegRFEType(Adapter) != 64)
1538
pHalData->rfe_type = GetRegRFEType(Adapter);
1539
else if (IS_HARDWARE_TYPE_8814AE(Adapter))
1540
pHalData->rfe_type = 0;
1541
else if (IS_HARDWARE_TYPE_8814AU(Adapter))
1542
pHalData->rfe_type = 1;
1543
hal_ReadAmplifierType_8814A(Adapter);
1544
1545
} else {
1546
/* bit7==0 means RFE type defined by 0xCA[6:0] */
1547
pHalData->rfe_type = PROMContent[EEPROM_RFE_OPTION_8814] & 0x7F;
1548
hal_ReadAmplifierType_8814A(Adapter);
1549
}
1550
} else {
1551
if (GetRegRFEType(Adapter) != 64)
1552
pHalData->rfe_type = GetRegRFEType(Adapter);
1553
else if (IS_HARDWARE_TYPE_8814AE(Adapter))
1554
pHalData->rfe_type = 0;
1555
else if (IS_HARDWARE_TYPE_8814AU(Adapter))
1556
pHalData->rfe_type = 1;
1557
1558
hal_ReadAmplifierType_8814A(Adapter);
1559
}
1560
RTW_INFO("RFE Type: 0x%2x\n", pHalData->rfe_type);
1561
}
1562
1563
void
1564
hal_ReadPowerTrackingType_8814A(
1565
PADAPTER Adapter,
1566
u8 *PROMContent,
1567
BOOLEAN AutoloadFail
1568
)
1569
{
1570
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1571
1572
/*Efuse 0xC8[7:6] TX Power Tracking Mode*/
1573
u8 PowerTrackingType = ((PROMContent[EEPROM_TX_PWR_CALIBRATE_RATE_8812] & 0xC0) >> 6);
1574
1575
if (!AutoloadFail) {
1576
if (GetRegPowerTrackingType(Adapter) != 64)
1577
pHalData->rf_power_tracking_type = GetRegPowerTrackingType(Adapter);
1578
} else
1579
pHalData->rf_power_tracking_type = 0;
1580
1581
if (PowerTrackingType == 0 || PowerTrackingType == 1 || PowerTrackingType == 2 || PowerTrackingType == 3)
1582
pHalData->rf_power_tracking_type = PowerTrackingType;
1583
else
1584
pHalData->rf_power_tracking_type = 0;
1585
1586
RTW_INFO("PowerTracking Type: 0x%2x\n", pHalData->rf_power_tracking_type);
1587
}
1588
1589
1590
static void
1591
hal_EfusePowerSwitch8814A(
1592
PADAPTER pAdapter,
1593
u8 bWrite,
1594
u8 PwrState)
1595
{
1596
u8 tempval;
1597
u16 tmpV16;
1598
u8 EFUSE_ACCESS_ON_8814A = 0x69;
1599
u8 EFUSE_ACCESS_OFF_8814A = 0x00;
1600
1601
if (PwrState == _TRUE) {
1602
rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON_8814A);
1603
1604
/* Reset: 0x0000h[28], default valid */
1605
tmpV16 = PlatformEFIORead2Byte(pAdapter, REG_SYS_FUNC_EN);
1606
if (!(tmpV16 & FEN_ELDR)) {
1607
tmpV16 |= FEN_ELDR ;
1608
rtw_write16(pAdapter, REG_SYS_FUNC_EN, tmpV16);
1609
}
1610
1611
/* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid */
1612
tmpV16 = PlatformEFIORead2Byte(pAdapter, REG_SYS_CLKR);
1613
if ((!(tmpV16 & LOADER_CLK_EN)) || (!(tmpV16 & ANA8M))) {
1614
tmpV16 |= (LOADER_CLK_EN | ANA8M) ;
1615
rtw_write16(pAdapter, REG_SYS_CLKR, tmpV16);
1616
}
1617
1618
if (bWrite == _TRUE) {
1619
/* Enable LDO 2.5V before read/write action */
1620
tempval = rtw_read8(pAdapter, EFUSE_TEST + 3);
1621
tempval &= 0x0F;
1622
tempval |= (VOLTAGE_V25 << 4);
1623
rtw_write8(pAdapter, EFUSE_TEST + 3, (tempval | 0x80));
1624
}
1625
} else {
1626
rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF_8814A);
1627
1628
if (bWrite == _TRUE) {
1629
/* Disable LDO 2.5V after read/write action */
1630
tempval = rtw_read8(pAdapter, EFUSE_TEST + 3);
1631
rtw_write8(pAdapter, EFUSE_TEST + 3, (tempval & 0x7F));
1632
}
1633
}
1634
}
1635
1636
static void
1637
rtl8814_EfusePowerSwitch(
1638
PADAPTER pAdapter,
1639
u8 bWrite,
1640
u8 PwrState)
1641
{
1642
hal_EfusePowerSwitch8814A(pAdapter, bWrite, PwrState);
1643
}
1644
1645
static void
1646
hal_EfuseReadEFuse8814A(
1647
PADAPTER Adapter,
1648
u16 _offset,
1649
u16 _size_byte,
1650
u8 *pbuf,
1651
BOOLEAN bPseudoTest
1652
)
1653
{
1654
u8 *efuseTbl = NULL;
1655
u16 eFuse_Addr = 0;
1656
u8 offset = 0, wden = 0;
1657
u16 i, j;
1658
u16 **eFuseWord = NULL;
1659
u16 efuse_utilized = 0;
1660
u8 efuse_usage = 0;
1661
u8 offset_2_0 = 0;
1662
u8 efuseHeader = 0, efuseExtHdr = 0, efuseData = 0;
1663
1664
/* */
1665
/* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
1666
/* */
1667
if ((_offset + _size_byte) > EFUSE_MAP_LEN_8814A) {
1668
/* total E-Fuse table is 512bytes */
1669
RTW_INFO("Hal_EfuseReadEFuse8814A(): Invalid offset(%#x) with read bytes(%#x)!!\n", _offset, _size_byte);
1670
goto exit;
1671
}
1672
1673
efuseTbl = (u8 *)rtw_zmalloc(EFUSE_MAP_LEN_8814A);
1674
if (efuseTbl == NULL) {
1675
RTW_INFO("%s: alloc efuseTbl fail!\n", __FUNCTION__);
1676
goto exit;
1677
}
1678
1679
eFuseWord = (u16 **)rtw_malloc2d(EFUSE_MAX_SECTION_8814A, EFUSE_MAX_WORD_UNIT_8814A, 2);
1680
if (eFuseWord == NULL) {
1681
RTW_INFO("%s: alloc eFuseWord fail!\n", __FUNCTION__);
1682
goto exit;
1683
}
1684
1685
/* 0. Refresh efuse init map as all oxFF. */
1686
for (i = 0; i < EFUSE_MAX_SECTION_8814A; i++)
1687
for (j = 0; j < EFUSE_MAX_WORD_UNIT_8814A; j++)
1688
eFuseWord[i][j] = 0xFFFF;
1689
1690
/* */
1691
/* 1. Read the first byte to check if efuse is empty!!! */
1692
/* */
1693
/* */
1694
efuse_OneByteRead(Adapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
1695
1696
if (efuseHeader != 0xFF)
1697
efuse_utilized++;
1698
else {
1699
RTW_INFO("EFUSE is empty\n");
1700
efuse_utilized = 0;
1701
goto exit;
1702
}
1703
/* RT_DISP(FEEPROM, EFUSE_READ_ALL, ("Hal_EfuseReadEFuse8814A(): efuse_utilized: %d\n", efuse_utilized)); */
1704
1705
/* */
1706
/* 2. Read real efuse content. Filter PG header and every section data. */
1707
/* */
1708
while ((efuseHeader != 0xFF) && AVAILABLE_EFUSE_ADDR_8814A(eFuse_Addr)) {
1709
/* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr-1, *rtemp8)); */
1710
1711
/* Check PG header for section num. */
1712
if (EXT_HEADER(efuseHeader)) { /* extended header */
1713
offset_2_0 = GET_HDR_OFFSET_2_0(efuseHeader);
1714
/* RT_DISP(FEEPROM, EFUSE_READ_ALL, ("extended header offset_2_0=%X\n", offset_2_0)); */
1715
1716
efuse_OneByteRead(Adapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
1717
1718
/* RT_DISP(FEEPROM, EFUSE_READ_ALL, ("efuse[%X]=%X\n", eFuse_Addr-1, efuseExtHdr)); */
1719
1720
if (efuseExtHdr != 0xff) {
1721
efuse_utilized++;
1722
if (ALL_WORDS_DISABLED(efuseExtHdr)) {
1723
efuse_OneByteRead(Adapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
1724
if (efuseHeader != 0xff)
1725
efuse_utilized++;
1726
break;
1727
} else {
1728
offset = ((efuseExtHdr & 0xF0) >> 1) | offset_2_0;
1729
wden = (efuseExtHdr & 0x0F);
1730
}
1731
} else {
1732
RTW_INFO("Error condition, extended = 0xff\n");
1733
/* We should handle this condition. */
1734
break;
1735
}
1736
} else {
1737
offset = ((efuseHeader >> 4) & 0x0f);
1738
wden = (efuseHeader & 0x0f);
1739
}
1740
1741
if (offset < EFUSE_MAX_SECTION_8814A) {
1742
/* Get word enable value from PG header */
1743
/* RT_DISP(FEEPROM, EFUSE_READ_ALL, ("Offset-%X Worden=%X\n", offset, wden)); */
1744
1745
for (i = 0; i < EFUSE_MAX_WORD_UNIT_8814A; i++) {
1746
/* Check word enable condition in the section */
1747
if (!(wden & (0x01 << i))) {
1748
efuse_OneByteRead(Adapter, eFuse_Addr++, &efuseData, bPseudoTest);
1749
/* RT_DISP(FEEPROM, EFUSE_READ_ALL, ("efuse[%X]=%X\n", eFuse_Addr-1, efuseData)); */
1750
efuse_utilized++;
1751
eFuseWord[offset][i] = (efuseData & 0xff);
1752
1753
if (!AVAILABLE_EFUSE_ADDR_8814A(eFuse_Addr))
1754
break;
1755
1756
efuse_OneByteRead(Adapter, eFuse_Addr++, &efuseData, bPseudoTest);
1757
/* RT_DISP(FEEPROM, EFUSE_READ_ALL, ("efuse[%X]=%X\n", eFuse_Addr-1, efuseData)); */
1758
efuse_utilized++;
1759
eFuseWord[offset][i] |= (((u16)efuseData << 8) & 0xff00);
1760
1761
if (!AVAILABLE_EFUSE_ADDR_8814A(eFuse_Addr))
1762
break;
1763
}
1764
}
1765
} else { /* deal with error offset,skip error data */
1766
RTW_PRINT("invalid offset:0x%02x\n", offset);
1767
for (i = 0; i < EFUSE_MAX_WORD_UNIT_8814A; i++) {
1768
/* Check word enable condition in the section */
1769
if (!(wden & 0x01)) {
1770
eFuse_Addr++;
1771
efuse_utilized++;
1772
if (!AVAILABLE_EFUSE_ADDR_8814A(eFuse_Addr))
1773
break;
1774
eFuse_Addr++;
1775
efuse_utilized++;
1776
if (!AVAILABLE_EFUSE_ADDR_8814A(eFuse_Addr))
1777
break;
1778
}
1779
}
1780
}
1781
/* Read next PG header */
1782
efuse_OneByteRead(Adapter, eFuse_Addr, &efuseHeader, bPseudoTest);
1783
/* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d rtemp 0x%x\n", eFuse_Addr, *rtemp8)); */
1784
1785
if (efuseHeader != 0xFF) {
1786
eFuse_Addr++;
1787
efuse_utilized++;
1788
}
1789
1790
}
1791
1792
/* */
1793
/* 3. Collect 16 sections and 4 word unit into Efuse map. */
1794
/* */
1795
for (i = 0; i < EFUSE_MAX_SECTION_8814A; i++) {
1796
for (j = 0; j < EFUSE_MAX_WORD_UNIT_8814A; j++) {
1797
efuseTbl[(i * 8) + (j * 2)] = (eFuseWord[i][j] & 0xff);
1798
efuseTbl[(i * 8) + ((j * 2) + 1)] = ((eFuseWord[i][j] >> 8) & 0xff);
1799
}
1800
}
1801
1802
/* RT_DISP(FEEPROM, EFUSE_READ_ALL, ("Hal_EfuseReadEFuse8814A(): efuse_utilized: %d\n", efuse_utilized)); */
1803
1804
/* */
1805
/* 4. Copy from Efuse map to output pointer memory!!! */
1806
/* */
1807
for (i = 0; i < _size_byte; i++)
1808
pbuf[i] = efuseTbl[_offset + i];
1809
1810
/* */
1811
/* 5. Calculate Efuse utilization. */
1812
/* */
1813
efuse_usage = (u8)((eFuse_Addr * 100) / EFUSE_REAL_CONTENT_LEN_8814A);
1814
rtw_hal_set_hwreg(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&eFuse_Addr);
1815
1816
exit:
1817
if (efuseTbl)
1818
rtw_mfree(efuseTbl, EFUSE_MAP_LEN_8814A);
1819
1820
if (eFuseWord)
1821
rtw_mfree2d((void *)eFuseWord, EFUSE_MAX_SECTION_8814A, EFUSE_MAX_WORD_UNIT_8814A, sizeof(u16));
1822
}
1823
1824
static void
1825
rtl8814_ReadEFuse(
1826
PADAPTER Adapter,
1827
u8 efuseType,
1828
u16 _offset,
1829
u16 _size_byte,
1830
u8 *pbuf,
1831
BOOLEAN bPseudoTest
1832
)
1833
{
1834
hal_EfuseReadEFuse8814A(Adapter, _offset, _size_byte, pbuf, bPseudoTest);
1835
}
1836
1837
/* Do not support BT */
1838
void
1839
hal_EFUSEGetEfuseDefinition8814A(
1840
PADAPTER pAdapter,
1841
u8 efuseType,
1842
u8 type,
1843
void *pOut
1844
)
1845
{
1846
switch (type) {
1847
case TYPE_EFUSE_MAX_SECTION: {
1848
u8 *pMax_section;
1849
pMax_section = (u8 *)pOut;
1850
*pMax_section = EFUSE_MAX_SECTION_8814A;
1851
}
1852
break;
1853
case TYPE_EFUSE_REAL_CONTENT_LEN: {
1854
u16 *pu2Tmp;
1855
pu2Tmp = (u16 *)pOut;
1856
*pu2Tmp = EFUSE_REAL_CONTENT_LEN_8814A;
1857
}
1858
break;
1859
case TYPE_EFUSE_CONTENT_LEN_BANK: {
1860
u16 *pu2Tmp;
1861
pu2Tmp = (u16 *)pOut;
1862
*pu2Tmp = EFUSE_REAL_CONTENT_LEN_8814A;
1863
}
1864
break;
1865
case TYPE_AVAILABLE_EFUSE_BYTES_BANK: {
1866
u16 *pu2Tmp;
1867
pu2Tmp = (u16 *)pOut;
1868
*pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN_8814A - EFUSE_OOB_PROTECT_BYTES);
1869
}
1870
break;
1871
case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL: {
1872
u16 *pu2Tmp;
1873
pu2Tmp = (u16 *)pOut;
1874
*pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN_8814A - EFUSE_OOB_PROTECT_BYTES);
1875
}
1876
break;
1877
case TYPE_EFUSE_MAP_LEN: {
1878
u16 *pu2Tmp;
1879
pu2Tmp = (u16 *)pOut;
1880
*pu2Tmp = (u16)EFUSE_MAP_LEN_8814A;
1881
}
1882
break;
1883
case TYPE_EFUSE_PROTECT_BYTES_BANK: {
1884
u8 *pu1Tmp;
1885
pu1Tmp = (u8 *)pOut;
1886
*pu1Tmp = (u8)(EFUSE_OOB_PROTECT_BYTES);
1887
}
1888
break;
1889
default: {
1890
u8 *pu1Tmp;
1891
pu1Tmp = (u8 *)pOut;
1892
*pu1Tmp = 0;
1893
}
1894
break;
1895
}
1896
}
1897
1898
static void
1899
rtl8814_EFUSE_GetEfuseDefinition(
1900
PADAPTER pAdapter,
1901
u8 efuseType,
1902
u8 type,
1903
void *pOut,
1904
BOOLEAN bPseudoTest
1905
)
1906
{
1907
hal_EFUSEGetEfuseDefinition8814A(pAdapter, efuseType, type, pOut);
1908
}
1909
1910
static u8
1911
hal_EfuseWordEnableDataWrite8814A(PADAPTER pAdapter,
1912
u16 efuse_addr,
1913
u8 word_en,
1914
u8 *data,
1915
BOOLEAN bPseudoTest)
1916
{
1917
u16 readbackAddr = 0;
1918
u16 start_addr = efuse_addr;
1919
u8 badworden = 0x0F;
1920
u8 readbackData[PGPKT_DATA_SIZE];
1921
1922
_rtw_memset((void *)readbackData, 0xff, PGPKT_DATA_SIZE);
1923
1924
RTW_INFO("word_en = %x efuse_addr=%x\n", word_en, efuse_addr);
1925
1926
if (!(word_en & BIT0)) {
1927
readbackAddr = start_addr;
1928
efuse_OneByteWrite(pAdapter, start_addr++, data[0], bPseudoTest);
1929
efuse_OneByteWrite(pAdapter, start_addr++, data[1], bPseudoTest);
1930
1931
if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188E(pAdapter) ||
1932
IS_HARDWARE_TYPE_8192E(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter))
1933
phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 0); /* Use 10K Read, Suggested by Morris & Victor */
1934
1935
efuse_OneByteRead(pAdapter, readbackAddr, &readbackData[0], bPseudoTest);
1936
efuse_OneByteRead(pAdapter, readbackAddr + 1, &readbackData[1], bPseudoTest);
1937
1938
if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188E(pAdapter) ||
1939
IS_HARDWARE_TYPE_8192E(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter))
1940
phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 1); /* Restored to 1.5K Read, Suggested by Morris & Victor */
1941
1942
if ((data[0] != readbackData[0]) || (data[1] != readbackData[1]))
1943
badworden &= (~BIT0);
1944
}
1945
if (!(word_en & BIT1)) {
1946
readbackAddr = start_addr;
1947
efuse_OneByteWrite(pAdapter, start_addr++, data[2], bPseudoTest);
1948
efuse_OneByteWrite(pAdapter, start_addr++, data[3], bPseudoTest);
1949
1950
if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188E(pAdapter) ||
1951
IS_HARDWARE_TYPE_8192E(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter))
1952
phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 0); /* Use 10K Read, Suggested by Morris & Victor */
1953
1954
efuse_OneByteRead(pAdapter, readbackAddr , &readbackData[2], bPseudoTest);
1955
efuse_OneByteRead(pAdapter, readbackAddr + 1, &readbackData[3], bPseudoTest);
1956
1957
if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188E(pAdapter) ||
1958
IS_HARDWARE_TYPE_8192E(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter))
1959
phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 1); /* Restored to 1.5K Read, Suggested by Morris & Victor */
1960
1961
if ((data[2] != readbackData[2]) || (data[3] != readbackData[3]))
1962
badworden &= (~BIT1);
1963
}
1964
if (!(word_en & BIT2)) {
1965
readbackAddr = start_addr;
1966
efuse_OneByteWrite(pAdapter, start_addr++, data[4], bPseudoTest);
1967
efuse_OneByteWrite(pAdapter, start_addr++, data[5], bPseudoTest);
1968
1969
if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188E(pAdapter) ||
1970
IS_HARDWARE_TYPE_8192E(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter))
1971
phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 0); /* Use 10K Read, Suggested by Morris & Victor */
1972
1973
efuse_OneByteRead(pAdapter, readbackAddr, &readbackData[4], bPseudoTest);
1974
efuse_OneByteRead(pAdapter, readbackAddr + 1, &readbackData[5], bPseudoTest);
1975
1976
if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188E(pAdapter) ||
1977
IS_HARDWARE_TYPE_8192E(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter))
1978
phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 1); /* Restored to 1.5K Read, Suggested by Morris & Victor */
1979
1980
if ((data[4] != readbackData[4]) || (data[5] != readbackData[5]))
1981
badworden &= (~BIT2);
1982
}
1983
if (!(word_en & BIT3)) {
1984
readbackAddr = start_addr;
1985
efuse_OneByteWrite(pAdapter, start_addr++, data[6], bPseudoTest);
1986
efuse_OneByteWrite(pAdapter, start_addr++, data[7], bPseudoTest);
1987
1988
if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188E(pAdapter) ||
1989
IS_HARDWARE_TYPE_8192E(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter))
1990
phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 0); /* Use 10K Read, Suggested by Morris & Victor */
1991
1992
efuse_OneByteRead(pAdapter, readbackAddr, &readbackData[6], bPseudoTest);
1993
efuse_OneByteRead(pAdapter, readbackAddr + 1, &readbackData[7], bPseudoTest);
1994
1995
if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188E(pAdapter) ||
1996
IS_HARDWARE_TYPE_8192E(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter))
1997
phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 1); /* Restored to 1.5K Read, Suggested by Morris & Victor */
1998
1999
if ((data[6] != readbackData[6]) || (data[7] != readbackData[7]))
2000
badworden &= (~BIT3);
2001
}
2002
return badworden;
2003
}
2004
2005
static u8
2006
rtl8814_Efuse_WordEnableDataWrite(PADAPTER pAdapter,
2007
u16 efuse_addr,
2008
u8 word_en,
2009
u8 *data,
2010
BOOLEAN bPseudoTest)
2011
{
2012
u8 ret = 0;
2013
2014
ret = hal_EfuseWordEnableDataWrite8814A(pAdapter, efuse_addr, word_en, data, bPseudoTest);
2015
2016
return ret;
2017
}
2018
2019
2020
static u16 hal_EfuseGetCurrentSize_8814A(PADAPTER pAdapter, BOOLEAN bPseudoTest)
2021
{
2022
int bContinual = _TRUE;
2023
2024
u16 efuse_addr = 0;
2025
u8 hoffset = 0, hworden = 0;
2026
u8 efuse_data, word_cnts = 0;
2027
2028
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2029
PEFUSE_HAL pEfuseHal = &(pHalData->EfuseHal);
2030
2031
RTW_INFO("=======> %s()\n", __func__);
2032
2033
if (bPseudoTest)
2034
efuse_addr = (u16)(fakeEfuseUsedBytes);
2035
else
2036
rtw_hal_get_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
2037
/* RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseGetCurrentSize_8723A(), start_efuse_addr = %d\n", efuse_addr)); */
2038
2039
while (bContinual &&
2040
efuse_OneByteRead(pAdapter, efuse_addr , &efuse_data, bPseudoTest) &&
2041
(efuse_addr < EFUSE_REAL_CONTENT_LEN_8814A)) {
2042
if (efuse_data != 0xFF) {
2043
if ((efuse_data & 0x1F) == 0x0F) { /* extended header */
2044
hoffset = efuse_data;
2045
efuse_addr++;
2046
efuse_OneByteRead(pAdapter, efuse_addr, &efuse_data, bPseudoTest);
2047
if ((efuse_data & 0x0F) == 0x0F) {
2048
efuse_addr++;
2049
continue;
2050
} else {
2051
hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
2052
hworden = efuse_data & 0x0F;
2053
}
2054
} else {
2055
hoffset = (efuse_data >> 4) & 0x0F;
2056
hworden = efuse_data & 0x0F;
2057
}
2058
RTW_INFO(FUNC_ADPT_FMT": Offset=%d Worden=%#X\n",
2059
FUNC_ADPT_ARG(pAdapter), hoffset, hworden);
2060
word_cnts = Efuse_CalculateWordCnts(hworden);
2061
/* read next header */
2062
efuse_addr = efuse_addr + (word_cnts * 2) + 1;
2063
} else
2064
bContinual = _FALSE ;
2065
}
2066
2067
if (bPseudoTest) {
2068
fakeEfuseUsedBytes = efuse_addr;
2069
pEfuseHal->fakeEfuseUsedBytes = efuse_addr;
2070
RTW_INFO("%s(), return %d\n", __func__, pEfuseHal->fakeEfuseUsedBytes);
2071
} else {
2072
pEfuseHal->EfuseUsedBytes = efuse_addr;
2073
pEfuseHal->EfuseUsedPercentage = (u8)((pEfuseHal->EfuseUsedBytes * 100) / pEfuseHal->PhysicalLen_WiFi);
2074
rtw_hal_set_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
2075
rtw_hal_set_hwreg(pAdapter, HW_VAR_EFUSE_USAGE, (u8 *)&(pEfuseHal->EfuseUsedPercentage));
2076
RTW_INFO("%s(), return %d\n", __func__, efuse_addr);
2077
}
2078
2079
return efuse_addr;
2080
2081
}
2082
2083
static u16
2084
rtl8814_EfuseGetCurrentSize(
2085
PADAPTER pAdapter,
2086
u8 efuseType,
2087
BOOLEAN bPseudoTest)
2088
{
2089
u16 ret = 0;
2090
2091
ret = hal_EfuseGetCurrentSize_8814A(pAdapter, bPseudoTest);
2092
2093
return ret;
2094
}
2095
2096
2097
static int
2098
hal_EfusePgPacketRead_8814A(
2099
PADAPTER pAdapter,
2100
u8 offset,
2101
u8 *data,
2102
BOOLEAN bPseudoTest)
2103
{
2104
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2105
PEFUSE_HAL pEfuseHal = &(pHalData->EfuseHal);
2106
u8 ReadState = PG_STATE_HEADER;
2107
2108
int bContinual = _TRUE;
2109
int bDataEmpty = _TRUE ;
2110
2111
u8 efuse_data, word_cnts = 0;
2112
u16 efuse_addr = 0;
2113
u8 hoffset = 0, hworden = 0;
2114
u8 tmpidx = 0;
2115
u8 tmpdata[8];
2116
u8 tmp_header = 0;
2117
2118
if (data == NULL)
2119
return _FALSE;
2120
if (offset >= EFUSE_MAX_SECTION_JAGUAR)
2121
return _FALSE;
2122
2123
_rtw_memset((void *)data, 0xff, sizeof(u8) * PGPKT_DATA_SIZE);
2124
_rtw_memset((void *)tmpdata, 0xff, sizeof(u8) * PGPKT_DATA_SIZE);
2125
2126
/* */
2127
/* <Roger_TODO> Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. */
2128
/* Skip dummy parts to prevent unexpected data read from Efuse. */
2129
/* By pass right now. 2009.02.19. */
2130
/* */
2131
while (bContinual && (efuse_addr < pEfuseHal->PhysicalLen_WiFi)) {
2132
/* ------- Header Read ------------- */
2133
if (ReadState & PG_STATE_HEADER) {
2134
if (efuse_OneByteRead(pAdapter, efuse_addr , &efuse_data, bPseudoTest) && (efuse_data != 0xFF)) {
2135
if (ALL_WORDS_DISABLED(efuse_data)) {
2136
tmp_header = efuse_data;
2137
efuse_addr++;
2138
efuse_OneByteRead(pAdapter, efuse_addr , &efuse_data, bPseudoTest);
2139
if ((efuse_data & 0x0F) != 0x0F) {
2140
hoffset = ((tmp_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
2141
hworden = efuse_data & 0x0F;
2142
} else {
2143
efuse_addr++;
2144
break;
2145
}
2146
2147
} else {
2148
hoffset = (efuse_data >> 4) & 0x0F;
2149
hworden = efuse_data & 0x0F;
2150
}
2151
word_cnts = Efuse_CalculateWordCnts(hworden);
2152
bDataEmpty = _TRUE ;
2153
2154
if (hoffset == offset) {
2155
for (tmpidx = 0; tmpidx < word_cnts * 2 ; tmpidx++) {
2156
if (efuse_OneByteRead(pAdapter, efuse_addr + 1 + tmpidx , &efuse_data, bPseudoTest)) {
2157
tmpdata[tmpidx] = efuse_data;
2158
if (efuse_data != 0xff)
2159
bDataEmpty = _FALSE;
2160
}
2161
}
2162
if (bDataEmpty == _FALSE)
2163
ReadState = PG_STATE_DATA;
2164
else { /* read next header */
2165
efuse_addr = efuse_addr + (word_cnts * 2) + 1;
2166
ReadState = PG_STATE_HEADER;
2167
}
2168
} else { /* read next header */
2169
efuse_addr = efuse_addr + (word_cnts * 2) + 1;
2170
ReadState = PG_STATE_HEADER;
2171
}
2172
2173
} else
2174
bContinual = _FALSE ;
2175
}
2176
/* ------- Data section Read ------------- */
2177
else if (ReadState & PG_STATE_DATA) {
2178
efuse_WordEnableDataRead(hworden, tmpdata, data);
2179
efuse_addr = efuse_addr + (word_cnts * 2) + 1;
2180
ReadState = PG_STATE_HEADER;
2181
}
2182
2183
}
2184
2185
if ((data[0] == 0xff) && (data[1] == 0xff) && (data[2] == 0xff) && (data[3] == 0xff) &&
2186
(data[4] == 0xff) && (data[5] == 0xff) && (data[6] == 0xff) && (data[7] == 0xff))
2187
return _FALSE;
2188
else
2189
return _TRUE;
2190
}
2191
2192
static int
2193
rtl8814_Efuse_PgPacketRead(PADAPTER pAdapter,
2194
u8 offset,
2195
u8 *data,
2196
BOOLEAN bPseudoTest)
2197
{
2198
int ret = 0;
2199
2200
ret = hal_EfusePgPacketRead_8814A(pAdapter, offset, data, bPseudoTest);
2201
2202
return ret;
2203
}
2204
2205
BOOLEAN
2206
efuse_PgPacketCheck(
2207
PADAPTER pAdapter,
2208
u8 efuseType,
2209
BOOLEAN bPseudoTest
2210
)
2211
{
2212
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2213
2214
if (Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest) >= (EFUSE_REAL_CONTENT_LEN_8814A - EFUSE_PROTECT_BYTES_BANK_8814A)) {
2215
RTW_INFO("%s()error: %x >= %x\n", __func__, Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest), (EFUSE_REAL_CONTENT_LEN_8814A - EFUSE_PROTECT_BYTES_BANK_8814A));
2216
return _FALSE;
2217
}
2218
2219
return _TRUE;
2220
}
2221
2222
void
2223
efuse_PgPacketConstruct(
2224
u8 offset,
2225
u8 word_en,
2226
u8 *pData,
2227
PPGPKT_STRUCT pTargetPkt
2228
)
2229
{
2230
_rtw_memset((void *)pTargetPkt->data, 0xFF, sizeof(u8) * 8);
2231
pTargetPkt->offset = offset;
2232
pTargetPkt->word_en = word_en;
2233
efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data);
2234
pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
2235
2236
RTW_INFO("efuse_PgPacketConstruct(), targetPkt, offset=%d, word_en=0x%x, word_cnts=%d\n", pTargetPkt->offset, pTargetPkt->word_en, pTargetPkt->word_cnts);
2237
}
2238
2239
2240
u16
2241
efuse_PgPacketExceptionHandle(
2242
PADAPTER pAdapter,
2243
u16 ErrOffset
2244
)
2245
{
2246
RTW_INFO("===> efuse_PgPacketExceptionHandle(), ErrOffset = 0x%X\n", ErrOffset);
2247
2248
/* ErrOffset is the offset of bad (extension) header. */
2249
/* if (IS_HARDWARE_TYPE_8812AU(pAdapter)) */
2250
/* ErrOffset = Hal_EfusePgPacketExceptionHandle_8812A(pAdapter, ErrOffset); */
2251
2252
RTW_INFO("<=== efuse_PgPacketExceptionHandle(), recovered! Jump to Offset = 0x%X\n", ErrOffset);
2253
2254
return ErrOffset;
2255
}
2256
2257
2258
BOOLEAN
2259
hal_EfuseCheckIfDatafollowed(
2260
PADAPTER pAdapter,
2261
u8 word_cnts,
2262
u16 startAddr,
2263
BOOLEAN bPseudoTest
2264
)
2265
{
2266
BOOLEAN bRet = FALSE;
2267
u8 i, efuse_data;
2268
2269
for (i = 0; i < (word_cnts * 2) ; i++) {
2270
if (efuse_OneByteRead(pAdapter, (startAddr + i) , &efuse_data, bPseudoTest) && (efuse_data != 0xFF))
2271
bRet = TRUE;
2272
}
2273
2274
return bRet;
2275
}
2276
2277
BOOLEAN
2278
hal_EfuseWordEnMatched(
2279
PPGPKT_STRUCT pTargetPkt,
2280
PPGPKT_STRUCT pCurPkt,
2281
u8 *pWden
2282
)
2283
{
2284
u8 match_word_en = 0x0F; /* default all words are disabled */
2285
2286
/* check if the same words are enabled both target and current PG packet */
2287
if (((pTargetPkt->word_en & BIT0) == 0) &&
2288
((pCurPkt->word_en & BIT0) == 0)) {
2289
match_word_en &= ~BIT0; /* enable word 0 */
2290
}
2291
if (((pTargetPkt->word_en & BIT1) == 0) &&
2292
((pCurPkt->word_en & BIT1) == 0)) {
2293
match_word_en &= ~BIT1; /* enable word 1 */
2294
}
2295
if (((pTargetPkt->word_en & BIT2) == 0) &&
2296
((pCurPkt->word_en & BIT2) == 0)) {
2297
match_word_en &= ~BIT2; /* enable word 2 */
2298
}
2299
if (((pTargetPkt->word_en & BIT3) == 0) &&
2300
((pCurPkt->word_en & BIT3) == 0)) {
2301
match_word_en &= ~BIT3; /* enable word 3 */
2302
}
2303
2304
*pWden = match_word_en;
2305
2306
if (match_word_en != 0xf)
2307
return TRUE;
2308
else
2309
return FALSE;
2310
}
2311
2312
2313
BOOLEAN
2314
efuse_PgPacketPartialWrite(
2315
PADAPTER pAdapter,
2316
u8 efuseType,
2317
u16 *pAddr,
2318
PPGPKT_STRUCT pTargetPkt,
2319
BOOLEAN bPseudoTest
2320
)
2321
{
2322
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2323
PEFUSE_HAL pEfuseHal = &(pHalData->EfuseHal);
2324
BOOLEAN bRet = _FALSE;
2325
u8 i, efuse_data = 0, cur_header = 0;
2326
u8 matched_wden = 0, badworden = 0;
2327
u16 startAddr = 0;
2328
PGPKT_STRUCT curPkt;
2329
u16 max_sec_num = (efuseType == EFUSE_WIFI) ? pEfuseHal->MaxSecNum_WiFi : pEfuseHal->MaxSecNum_BT;
2330
u16 efuse_max = pEfuseHal->BankSize;
2331
u16 efuse_max_available_len =
2332
(efuseType == EFUSE_WIFI) ? pEfuseHal->TotalAvailBytes_WiFi : pEfuseHal->TotalAvailBytes_BT;
2333
2334
if (bPseudoTest) {
2335
pEfuseHal->fakeEfuseBank = (efuseType == EFUSE_WIFI) ? 0 : pEfuseHal->fakeEfuseBank;
2336
Efuse_GetCurrentSize(pAdapter, efuseType, _TRUE);
2337
}
2338
2339
/* EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_max_available_len, bPseudoTest); */
2340
/* EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_CONTENT_LEN_BANK, &efuse_max, bPseudoTest); */
2341
2342
if (efuseType == EFUSE_WIFI) {
2343
if (bPseudoTest) {
2344
#ifdef HAL_EFUSE_MEMORY
2345
startAddr = (u16)pEfuseHal->fakeEfuseUsedBytes;
2346
#else
2347
startAddr = (u16)fakeEfuseUsedBytes;
2348
#endif
2349
2350
} else
2351
rtw_hal_get_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr);
2352
} else {
2353
if (bPseudoTest) {
2354
#ifdef HAL_EFUSE_MEMORY
2355
startAddr = (u16)pEfuseHal->fakeBTEfuseUsedBytes;
2356
#else
2357
startAddr = (u16)fakeBTEfuseUsedBytes;
2358
#endif
2359
2360
} else
2361
rtw_hal_get_hwreg(pAdapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&startAddr);
2362
}
2363
2364
startAddr %= efuse_max;
2365
RTW_INFO("%s: startAddr=%#X\n", __FUNCTION__, startAddr);
2366
RTW_INFO("efuse_PgPacketPartialWrite(), startAddr = 0x%X\n", startAddr);
2367
2368
while (1) {
2369
if (startAddr >= efuse_max_available_len) {
2370
bRet = _FALSE;
2371
RTW_INFO("startAddr(%d) >= efuse_max_available_len(%d)\n",
2372
startAddr, efuse_max_available_len);
2373
break;
2374
}
2375
2376
if (efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest) && (efuse_data != 0xFF)) {
2377
if (EXT_HEADER(efuse_data)) {
2378
cur_header = efuse_data;
2379
startAddr++;
2380
efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest);
2381
if (ALL_WORDS_DISABLED(efuse_data)) {
2382
u16 recoveredAddr = startAddr;
2383
recoveredAddr = efuse_PgPacketExceptionHandle(pAdapter, startAddr - 1);
2384
2385
if (recoveredAddr == (startAddr - 1)) {
2386
RTW_INFO("Error! All words disabled and the recovery failed, (Addr, Data) = (0x%X, 0x%X)\n",
2387
startAddr, efuse_data);
2388
pAdapter->LastError = ERR_INVALID_DATA;
2389
break;
2390
} else {
2391
startAddr = recoveredAddr;
2392
RTW_INFO("Bad extension header but recovered => Keep going.\n");
2393
continue;
2394
}
2395
} else {
2396
curPkt.offset = ((cur_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
2397
curPkt.word_en = efuse_data & 0x0F;
2398
}
2399
} else {
2400
if (ALL_WORDS_DISABLED(efuse_data)) {
2401
u16 recoveredAddr = startAddr;
2402
recoveredAddr = efuse_PgPacketExceptionHandle(pAdapter, startAddr);
2403
if (recoveredAddr != startAddr) {
2404
efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest);
2405
RTW_INFO("Bad header but recovered => Read header again.\n");
2406
}
2407
}
2408
2409
cur_header = efuse_data;
2410
curPkt.offset = (cur_header >> 4) & 0x0F;
2411
curPkt.word_en = cur_header & 0x0F;
2412
}
2413
2414
if (curPkt.offset > max_sec_num) {
2415
pAdapter->LastError = ERR_OUT_OF_RANGE;
2416
pEfuseHal->Status = ERR_OUT_OF_RANGE;
2417
bRet = _FALSE;
2418
break;
2419
}
2420
2421
curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en);
2422
/* if same header is found but no data followed */
2423
/* write some part of data followed by the header. */
2424
if ((curPkt.offset == pTargetPkt->offset) &&
2425
(!hal_EfuseCheckIfDatafollowed(pAdapter, curPkt.word_cnts, startAddr + 1, bPseudoTest)) &&
2426
hal_EfuseWordEnMatched(pTargetPkt, &curPkt, &matched_wden)) {
2427
RTW_INFO("Need to partial write data by the previous wrote header\n");
2428
/* RT_ASSERT(_FALSE, ("Error, Need to partial write data by the previous wrote header!!\n")); */
2429
/* Here to write partial data */
2430
badworden = Efuse_WordEnableDataWrite(pAdapter, startAddr + 1, matched_wden, pTargetPkt->data, bPseudoTest);
2431
if (badworden != 0x0F) {
2432
u32 PgWriteSuccess = 0;
2433
/* if write fail on some words, write these bad words again */
2434
2435
PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
2436
2437
if (!PgWriteSuccess) {
2438
bRet = _FALSE; /* write fail, return */
2439
break;
2440
}
2441
}
2442
/* partial write ok, update the target packet for later use */
2443
for (i = 0; i < 4; i++) {
2444
if ((matched_wden & (0x1 << i)) == 0) { /* this word has been written */
2445
pTargetPkt->word_en |= (0x1 << i); /* disable the word */
2446
}
2447
}
2448
pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
2449
}
2450
/* read from next header */
2451
startAddr = startAddr + (curPkt.word_cnts * 2) + 1;
2452
} else {
2453
/* not used header, 0xff */
2454
*pAddr = startAddr;
2455
RTW_INFO("Started from unused header offset=%d\n", startAddr);
2456
bRet = _TRUE;
2457
break;
2458
}
2459
}
2460
return bRet;
2461
}
2462
2463
2464
BOOLEAN
2465
hal_EfuseFixHeaderProcess(
2466
PADAPTER pAdapter,
2467
u8 efuseType,
2468
PPGPKT_STRUCT pFixPkt,
2469
u16 *pAddr,
2470
BOOLEAN bPseudoTest
2471
)
2472
{
2473
u8 originaldata[8], badworden = 0;
2474
u16 efuse_addr = *pAddr;
2475
u32 PgWriteSuccess = 0;
2476
2477
_rtw_memset((void *)originaldata, 0xff, 8);
2478
2479
if (Efuse_PgPacketRead(pAdapter, pFixPkt->offset, originaldata, bPseudoTest)) {
2480
/* check if data exist */
2481
badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr + 1, pFixPkt->word_en, originaldata, bPseudoTest);
2482
2483
if (badworden != 0xf) { /* write fail */
2484
PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pFixPkt->offset, badworden, originaldata, bPseudoTest);
2485
if (!PgWriteSuccess)
2486
return _FALSE;
2487
else
2488
efuse_addr = Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest);
2489
} else
2490
efuse_addr = efuse_addr + (pFixPkt->word_cnts * 2) + 1;
2491
} else
2492
efuse_addr = efuse_addr + (pFixPkt->word_cnts * 2) + 1;
2493
*pAddr = efuse_addr;
2494
return _TRUE;
2495
}
2496
2497
2498
BOOLEAN
2499
efuse_PgPacketWrite2ByteHeader(
2500
PADAPTER pAdapter,
2501
u8 efuseType,
2502
u16 *pAddr,
2503
PPGPKT_STRUCT pTargetPkt,
2504
BOOLEAN bPseudoTest)
2505
{
2506
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2507
PEFUSE_HAL pEfuseHal = &(pHalData->EfuseHal);
2508
BOOLEAN bRet = _FALSE;
2509
u16 efuse_addr = *pAddr;
2510
u8 pg_header = 0, tmp_header = 0, pg_header_temp = 0;
2511
u8 repeatcnt = 0;
2512
u16 efuse_max_available_len =
2513
(efuseType == EFUSE_WIFI) ? pEfuseHal->TotalAvailBytes_WiFi : pEfuseHal->TotalAvailBytes_BT;
2514
2515
RTW_INFO("Wirte 2byte header\n");
2516
2517
2518
while (efuse_addr < efuse_max_available_len) {
2519
pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F;
2520
RTW_INFO("pg_header = 0x%x\n", pg_header);
2521
efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
2522
2523
if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188E(pAdapter) ||
2524
IS_HARDWARE_TYPE_8192E(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter))
2525
phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 0); /* Use 10K Read, Suggested by Morris & Victor*/
2526
2527
efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
2528
2529
if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188E(pAdapter) ||
2530
IS_HARDWARE_TYPE_8192E(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter))
2531
phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 1); /* Use 10K Read, Suggested by Morris & Victor*/
2532
2533
while (tmp_header == 0xFF || pg_header != tmp_header) {
2534
if (repeatcnt++ > pEfuseHal->DataRetry) {
2535
RTW_INFO("Repeat over limit for pg_header!!\n");
2536
return _FALSE;
2537
}
2538
2539
efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
2540
efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
2541
}
2542
2543
/* to write ext_header */
2544
if (tmp_header == pg_header) {
2545
efuse_addr++;
2546
pg_header_temp = pg_header;
2547
pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en;
2548
2549
efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
2550
2551
if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188E(pAdapter) ||
2552
IS_HARDWARE_TYPE_8192E(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter))
2553
phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 0); /* Use 10K Read, Suggested by Morris & Victor*/
2554
2555
efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
2556
2557
if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188E(pAdapter) ||
2558
IS_HARDWARE_TYPE_8192E(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter))
2559
phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 1); /* Use 10K Read, Suggested by Morris & Victor*/
2560
2561
while (tmp_header == 0xFF || pg_header != tmp_header) {
2562
if (repeatcnt++ > pEfuseHal->DataRetry) {
2563
RTW_INFO("Repeat over limit for ext_header!!\n");
2564
return _FALSE;
2565
}
2566
2567
efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
2568
efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
2569
}
2570
2571
if ((tmp_header & 0x0F) == 0x0F) { /* word_en PG fail */
2572
if (repeatcnt++ > pEfuseHal->DataRetry) {
2573
RTW_INFO("Repeat over limit for word_en!!\n");
2574
return _FALSE;
2575
} else {
2576
efuse_addr++;
2577
continue;
2578
}
2579
} else if (pg_header != tmp_header) { /* offset PG fail */
2580
PGPKT_STRUCT fixPkt;
2581
/* RT_ASSERT(_FALSE, ("Error, efuse_PgPacketWrite2ByteHeader(), offset PG fail, need to cover the existed data!!\n")); */
2582
RTW_INFO("Error condition for offset PG fail, need to cover the existed data\n");
2583
fixPkt.offset = ((pg_header_temp & 0xE0) >> 5) | ((tmp_header & 0xF0) >> 1);
2584
fixPkt.word_en = tmp_header & 0x0F;
2585
fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
2586
if (!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
2587
return _FALSE;
2588
} else {
2589
bRet = _TRUE;
2590
break;
2591
}
2592
} else if ((tmp_header & 0x1F) == 0x0F) { /* wrong extended header */
2593
efuse_addr += 2;
2594
continue;
2595
}
2596
}
2597
2598
*pAddr = efuse_addr;
2599
return bRet;
2600
}
2601
2602
2603
BOOLEAN
2604
efuse_PgPacketWrite1ByteHeader(
2605
PADAPTER pAdapter,
2606
u8 efuseType,
2607
u16 *pAddr,
2608
PPGPKT_STRUCT pTargetPkt,
2609
BOOLEAN bPseudoTest)
2610
{
2611
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2612
PEFUSE_HAL pEfuseHal = &(pHalData->EfuseHal);
2613
BOOLEAN bRet = _FALSE;
2614
u8 pg_header = 0, tmp_header = 0;
2615
u16 efuse_addr = *pAddr;
2616
u8 repeatcnt = 0;
2617
2618
RTW_INFO("Wirte 1byte header\n");
2619
pg_header = ((pTargetPkt->offset << 4) & 0xf0) | pTargetPkt->word_en;
2620
2621
if (IS_HARDWARE_TYPE_8723BE(pAdapter))
2622
efuse_OneByteWrite(pAdapter, 0x1FF, 00, _FALSE); /* increase current */
2623
2624
2625
efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
2626
2627
if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188E(pAdapter) ||
2628
IS_HARDWARE_TYPE_8192E(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter))
2629
phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 0); /* Use 10K Read, Suggested by Morris & Victor */
2630
2631
efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
2632
2633
if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188E(pAdapter) ||
2634
IS_HARDWARE_TYPE_8192E(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter))
2635
phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 1); /* Restored to 1.5K Read, Suggested by Morris & Victor */
2636
2637
2638
while (tmp_header == 0xFF || pg_header != tmp_header) {
2639
if (repeatcnt++ > pEfuseHal->HeaderRetry) {
2640
RTW_INFO("retry %d times fail!!\n", repeatcnt);
2641
return _FALSE;
2642
}
2643
efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
2644
efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
2645
RTW_INFO("===> efuse_PgPacketWrite1ByteHeader: Keep %d-th retrying, tmp_header = 0x%X\n", repeatcnt, tmp_header);
2646
}
2647
2648
if (pg_header == tmp_header)
2649
bRet = _TRUE;
2650
else {
2651
PGPKT_STRUCT fixPkt;
2652
/* RT_ASSERT(_FALSE, ("Error, efuse_PgPacketWrite1ByteHeader(), offset PG fail, need to cover the existed data!!\n")); */
2653
RTW_INFO(" pg_header(0x%X) != tmp_header(0x%X)\n", pg_header, tmp_header);
2654
RTW_INFO("Error condition for fixed PG packet, need to cover the existed data: (Addr, Data) = (0x%X, 0x%X)\n",
2655
efuse_addr, tmp_header);
2656
fixPkt.offset = (tmp_header >> 4) & 0x0F;
2657
fixPkt.word_en = tmp_header & 0x0F;
2658
fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
2659
if (!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
2660
return _FALSE;
2661
}
2662
2663
*pAddr = efuse_addr;
2664
return bRet;
2665
}
2666
2667
2668
2669
BOOLEAN
2670
efuse_PgPacketWriteHeader(
2671
PADAPTER pAdapter,
2672
u8 efuseType,
2673
u16 *pAddr,
2674
PPGPKT_STRUCT pTargetPkt,
2675
BOOLEAN bPseudoTest)
2676
{
2677
BOOLEAN bRet = _FALSE;
2678
2679
if (pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE)
2680
bRet = efuse_PgPacketWrite2ByteHeader(pAdapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
2681
else
2682
bRet = efuse_PgPacketWrite1ByteHeader(pAdapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
2683
2684
return bRet;
2685
}
2686
2687
BOOLEAN
2688
efuse_PgPacketWriteData(
2689
PADAPTER pAdapter,
2690
u8 efuseType,
2691
u16 *pAddr,
2692
PPGPKT_STRUCT pTargetPkt,
2693
BOOLEAN bPseudoTest)
2694
{
2695
BOOLEAN bRet = _FALSE;
2696
u16 efuse_addr = *pAddr;
2697
u8 badworden = 0;
2698
u32 PgWriteSuccess = 0;
2699
2700
badworden = 0x0f;
2701
badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr + 1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest);
2702
if (badworden == 0x0F) {
2703
RTW_INFO("efuse_PgPacketWriteData ok!!\n");
2704
return _TRUE;
2705
} else {
2706
/* Reorganize other pg packet */
2707
/* RT_ASSERT(_FALSE, ("Error, efuse_PgPacketWriteData(), wirte data fail!!\n")); */
2708
RTW_INFO("efuse_PgPacketWriteData Fail!!\n");
2709
2710
PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
2711
if (!PgWriteSuccess)
2712
return _FALSE;
2713
else
2714
return _TRUE;
2715
}
2716
2717
return bRet;
2718
}
2719
2720
2721
int
2722
hal_EfusePgPacketWrite_8814A(PADAPTER pAdapter,
2723
u8 offset,
2724
u8 word_en,
2725
u8 *pData,
2726
BOOLEAN bPseudoTest)
2727
{
2728
u8 efuseType = EFUSE_WIFI;
2729
PGPKT_STRUCT targetPkt;
2730
u16 startAddr = 0;
2731
2732
RTW_INFO("===> efuse_PgPacketWrite[%s], offset: 0x%X\n", (efuseType == EFUSE_WIFI) ? "WIFI" : "BT", offset);
2733
2734
/* 4 [1] Check if the remaining space is available to write. */
2735
if (!efuse_PgPacketCheck(pAdapter, efuseType, bPseudoTest)) {
2736
pAdapter->LastError = ERR_WRITE_PROTECT;
2737
RTW_INFO("efuse_PgPacketCheck(), fail!!\n");
2738
return _FALSE;
2739
}
2740
2741
/* 4 [2] Construct a packet to write: (Data, Offset, and WordEnable) */
2742
efuse_PgPacketConstruct(offset, word_en, pData, &targetPkt);
2743
2744
2745
/* 4 [3] Fix headers without data or fix bad headers, and then return the address where to get started. */
2746
if (!efuse_PgPacketPartialWrite(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) {
2747
pAdapter->LastError = ERR_INVALID_DATA;
2748
RTW_INFO("efuse_PgPacketPartialWrite(), fail!!\n");
2749
return _FALSE;
2750
}
2751
2752
/* 4 [4] Write the (extension) header. */
2753
if (!efuse_PgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) {
2754
pAdapter->LastError = ERR_IO_FAILURE;
2755
RTW_INFO("efuse_PgPacketWriteHeader(), fail!!\n");
2756
return _FALSE;
2757
}
2758
2759
/* 4 [5] Write the data. */
2760
if (!efuse_PgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) {
2761
pAdapter->LastError = ERR_IO_FAILURE;
2762
RTW_INFO("efuse_PgPacketWriteData(), fail!!\n");
2763
return _FALSE;
2764
}
2765
2766
RTW_INFO("<=== efuse_PgPacketWrite\n");
2767
return _TRUE;
2768
}
2769
2770
static int
2771
rtl8814_Efuse_PgPacketWrite(PADAPTER pAdapter,
2772
u8 offset,
2773
u8 word_en,
2774
u8 *data,
2775
BOOLEAN bPseudoTest)
2776
{
2777
int ret;
2778
2779
ret = hal_EfusePgPacketWrite_8814A(pAdapter, offset, word_en, data, bPseudoTest);
2780
2781
return ret;
2782
}
2783
2784
void InitRDGSetting8814A(PADAPTER padapter)
2785
{
2786
rtw_write8(padapter, REG_RD_CTRL, 0xFF);
2787
rtw_write16(padapter, REG_RD_NAV_NXT, 0x200);
2788
rtw_write8(padapter, REG_RD_RESP_PKT_TH, 0x05);
2789
}
2790
2791
void ReadRFType8814A(PADAPTER padapter)
2792
{
2793
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2794
2795
#if DISABLE_BB_RF
2796
pHalData->rf_chip = RF_PSEUDO_11N;
2797
#else
2798
pHalData->rf_chip = RF_6052;
2799
#endif
2800
2801
/* if (pHalData->rf_type == RF_1T1R){ */
2802
/* pHalData->bRFPathRxEnable[0] = _TRUE; */
2803
/* } */
2804
/* else { */ /* Default unknow type is 2T2r */
2805
/* pHalData->bRFPathRxEnable[0] = pHalData->bRFPathRxEnable[1] = _TRUE; */
2806
/* } */
2807
2808
if (IsSupported24G(padapter->registrypriv.wireless_mode) &&
2809
is_supported_5g(padapter->registrypriv.wireless_mode))
2810
pHalData->BandSet = BAND_ON_BOTH;
2811
else if (is_supported_5g(padapter->registrypriv.wireless_mode))
2812
pHalData->BandSet = BAND_ON_5G;
2813
else
2814
pHalData->BandSet = BAND_ON_2_4G;
2815
2816
/* if(padapter->bInHctTest) */
2817
/* pHalData->BandSet = BAND_ON_2_4G; */
2818
}
2819
2820
void rtl8814_start_thread(PADAPTER padapter)
2821
{
2822
}
2823
2824
void rtl8814_stop_thread(PADAPTER padapter)
2825
{
2826
}
2827
2828
void hal_notch_filter_8814(_adapter *adapter, bool enable)
2829
{
2830
if (enable) {
2831
RTW_INFO("Enable notch filter\n");
2832
/* rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) | BIT1); */
2833
} else {
2834
RTW_INFO("Disable notch filter\n");
2835
/* rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1); */
2836
}
2837
}
2838
2839
u8
2840
GetEEPROMSize8814A(
2841
PADAPTER Adapter
2842
)
2843
{
2844
u8 size = 0;
2845
u32 curRCR;
2846
2847
curRCR = rtw_read16(Adapter, REG_SYS_EEPROM_CTRL);
2848
size = (curRCR & EEPROMSEL) ? 6 : 4; /* 6: EEPROM used is 93C46, 4: boot from E-Fuse. */
2849
2850
RTW_INFO("EEPROM type is %s\n", size == 4 ? "E-FUSE" : "93C46");
2851
/* return size; */
2852
return 4; /* <20120713, Kordan> The default value of HW is 6 ?!! */
2853
}
2854
2855
#if 0
2856
void CheckAutoloadState8812A(PADAPTER padapter)
2857
{
2858
2859
u8 val8;
2860
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2861
2862
2863
/* check system boot selection */
2864
val8 = rtw_read8(padapter, REG_9346CR);
2865
pHalData->EepromOrEfuse = (val8 & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
2866
pHalData->bautoload_fail_flag = (val8 & EEPROM_EN) ? _FALSE : _TRUE;
2867
2868
RTW_INFO("%s: 9346CR(%#x)=0x%02x, Boot from %s, Autoload %s!\n",
2869
__FUNCTION__, REG_9346CR, val8,
2870
(pHalData->EepromOrEfuse ? "EEPROM" : "EFUSE"),
2871
(pHalData->bautoload_fail_flag ? "Fail" : "OK"));
2872
}
2873
#endif
2874
2875
void
2876
hal_InitPGData_8814A(
2877
PADAPTER padapter,
2878
u8 *PROMContent
2879
)
2880
{
2881
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
2882
u32 i;
2883
u16 value16;
2884
2885
if (_FALSE == pHalData->bautoload_fail_flag) {
2886
/* autoload OK. */
2887
/* hal_ReadeFuse_8814A is FW offload read efuse, todo */
2888
/* #if (defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)) && (MP_DRIVER != 1) */
2889
/* if(hal_ReadeFuse_8814A(pAdapter) == _FAIL) */
2890
/* #endif */
2891
2892
/* Read EFUSE real map to shadow. */
2893
EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE);
2894
} else {
2895
/* autoload fail */
2896
RTW_INFO("AutoLoad Fail reported from CR9346!!\n");
2897
/* update to default value 0xFF */
2898
EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE);
2899
}
2900
2901
#ifdef CONFIG_EFUSE_CONFIG_FILE
2902
if (check_phy_efuse_tx_power_info_valid(padapter) == _FALSE) {
2903
if (Hal_readPGDataFromConfigFile(padapter) != _SUCCESS)
2904
RTW_ERR("invalid phy efuse and read from file fail, will use driver default!!\n");
2905
}
2906
#endif
2907
}
2908
2909
static void read_chip_version_8814a(PADAPTER Adapter)
2910
{
2911
u32 value32;
2912
PHAL_DATA_TYPE pHalData;
2913
u8 vdr;
2914
2915
pHalData = GET_HAL_DATA(Adapter);
2916
2917
value32 = rtw_read32(Adapter, REG_SYS_CFG);
2918
RTW_INFO("%s SYS_CFG(0x%X)=0x%08x\n", __FUNCTION__, REG_SYS_CFG, value32);
2919
2920
pHalData->version_id.ICType = CHIP_8814A;
2921
2922
pHalData->version_id.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
2923
2924
pHalData->version_id.RFType = RF_TYPE_3T3R;
2925
2926
vdr = (value32 & EXT_VENDOR_ID) >> EXT_VENDOR_ID_SHIFT;
2927
if (vdr == 0x00)
2928
pHalData->version_id.VendorType = CHIP_VENDOR_TSMC;
2929
else if (vdr == 0x01)
2930
pHalData->version_id.VendorType = CHIP_VENDOR_SMIC;
2931
else if (vdr == 0x02)
2932
pHalData->version_id.VendorType = CHIP_VENDOR_UMC;
2933
2934
pHalData->version_id.CUTVersion = (value32 & CHIP_VER_RTL_MASK) >> CHIP_VER_RTL_SHIFT; /* IC version (CUT) */
2935
2936
pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
2937
2938
#if 1
2939
dump_chip_info(pHalData->version_id);
2940
#endif
2941
2942
}
2943
2944
void
2945
hal_PatchwithJaguar_8814(
2946
PADAPTER Adapter,
2947
RT_MEDIA_STATUS MediaStatus
2948
)
2949
{
2950
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2951
struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv);
2952
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
2953
2954
if ((MediaStatus == RT_MEDIA_CONNECT) &&
2955
(pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP)) {
2956
rtw_write8(Adapter, rVhtlen_Use_Lsig_Jaguar, 0x1);
2957
rtw_write8(Adapter, REG_TCR + 3, BIT2);
2958
} else {
2959
rtw_write8(Adapter, rVhtlen_Use_Lsig_Jaguar, 0x3F);
2960
rtw_write8(Adapter, REG_TCR + 3, BIT0 | BIT1 | BIT2);
2961
}
2962
2963
2964
/*if( (MediaStatus == RT_MEDIA_CONNECT) &&
2965
((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP) ||
2966
(pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP)))
2967
{
2968
rtw_write8(Adapter, rBWIndication_Jaguar + 3,
2969
(rtw_read8(Adapter, rBWIndication_Jaguar + 3) | BIT2));
2970
}
2971
else
2972
{
2973
rtw_write8(Adapter, rBWIndication_Jaguar + 3,
2974
(rtw_read8(Adapter, rBWIndication_Jaguar + 3) & (~BIT2)));
2975
}*/
2976
}
2977
2978
void init_hal_spec_8814a(_adapter *adapter)
2979
{
2980
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
2981
2982
hal_spec->ic_name = "rtl8814a";
2983
hal_spec->macid_num = 128;
2984
hal_spec->sec_cam_ent_num = 64;
2985
hal_spec->sec_cap = SEC_CAP_CHK_BMC;
2986
2987
hal_spec->rfpath_num_2g = 4;
2988
hal_spec->rfpath_num_5g = 4;
2989
hal_spec->rf_reg_path_num = 4;
2990
hal_spec->max_tx_cnt = 3;
2991
2992
hal_spec->tx_nss_num = 3;
2993
hal_spec->rx_nss_num = 3;
2994
hal_spec->band_cap = BAND_CAP_2G | BAND_CAP_5G;
2995
hal_spec->bw_cap = BW_CAP_20M | BW_CAP_40M | BW_CAP_80M;
2996
hal_spec->port_num = 5;
2997
hal_spec->proto_cap = PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N | PROTO_CAP_11AC;
2998
2999
hal_spec->txgi_max = 63;
3000
hal_spec->txgi_pdbm = 2;
3001
3002
hal_spec->wl_func = 0
3003
| WL_FUNC_P2P
3004
| WL_FUNC_MIRACAST
3005
| WL_FUNC_TDLS
3006
;
3007
3008
#if CONFIG_TX_AC_LIFETIME
3009
hal_spec->tx_aclt_unit_factor = 8;
3010
#endif
3011
3012
hal_spec->pg_txpwr_saddr = 0x10;
3013
hal_spec->pg_txgi_diff_factor = 1;
3014
3015
rtw_macid_ctl_init_sleep_reg(adapter_to_macidctl(adapter)
3016
, REG_MACID_SLEEP
3017
, REG_MACID_SLEEP_1
3018
, REG_MACID_SLEEP_2
3019
, REG_MACID_SLEEP_3);
3020
}
3021
3022
void InitDefaultValue8814A(PADAPTER padapter)
3023
{
3024
PHAL_DATA_TYPE pHalData;
3025
struct pwrctrl_priv *pwrctrlpriv;
3026
u8 i;
3027
3028
pHalData = GET_HAL_DATA(padapter);
3029
pwrctrlpriv = adapter_to_pwrctl(padapter);
3030
3031
/* init default value */
3032
pHalData->fw_ractrl = _FALSE;
3033
if (!pwrctrlpriv->bkeepfwalive)
3034
pHalData->LastHMEBoxNum = 0;
3035
3036
/* init dm default value */
3037
pHalData->bChnlBWInitialized = _FALSE;
3038
pHalData->bIQKInitialized = _FALSE;
3039
3040
pHalData->EfuseHal.fakeEfuseBank = 0;
3041
pHalData->EfuseHal.fakeEfuseUsedBytes = 0;
3042
_rtw_memset(pHalData->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE);
3043
_rtw_memset(pHalData->EfuseHal.fakeEfuseInitMap, 0xFF, EFUSE_MAX_MAP_LEN);
3044
_rtw_memset(pHalData->EfuseHal.fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);
3045
}
3046
3047
void
3048
_InitBeaconParameters_8814A(
3049
PADAPTER Adapter
3050
)
3051
{
3052
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3053
u16 val16;
3054
u8 val8;
3055
3056
val8 = DIS_TSF_UDT;
3057
val16 = val8 | (val8 << 8); /* port0 and port1 */
3058
#ifdef CONFIG_BT_COEXIST
3059
if (pHalData->EEPROMBluetoothCoexist == 1) {
3060
/* Enable prot0 beacon function for PSTDMA */
3061
val16 |= EN_BCN_FUNCTION;
3062
}
3063
#endif
3064
rtw_write16(Adapter, REG_BCN_CTRL, val16);
3065
3066
/* TBTT setup time */
3067
rtw_write8(Adapter, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME);
3068
3069
/* TBTT hold time: 0x540[19:8] */
3070
rtw_write8(Adapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);
3071
rtw_write8(Adapter, REG_TBTT_PROHIBIT + 2,
3072
(rtw_read8(Adapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8));
3073
3074
rtw_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME_8814);/* 5ms */
3075
rtw_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME_8814); /* 2ms */
3076
3077
/* Suggested by designer timchen. Change beacon AIFS to the largest number */
3078
/* beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */
3079
rtw_write16(Adapter, REG_BCNTCFG, 0x4413);
3080
3081
}
3082
3083
static void
3084
_BeaconFunctionEnable(
3085
PADAPTER Adapter,
3086
BOOLEAN Enable,
3087
BOOLEAN Linked
3088
)
3089
{
3090
rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB));
3091
3092
rtw_write8(Adapter, REG_RD_CTRL + 1, 0x6F);
3093
}
3094
3095
3096
3097
void SetBeaconRelatedRegisters8814A(PADAPTER padapter)
3098
{
3099
u32 value32;
3100
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3101
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
3102
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
3103
u32 bcn_ctrl_reg = REG_BCN_CTRL;
3104
/* reset TSF, enable update TSF, correcting TSF On Beacon */
3105
3106
/* REG_MBSSID_BCN_SPACE */
3107
/* REG_BCNDMATIM */
3108
/* REG_ATIMWND */
3109
/* REG_TBTT_PROHIBIT */
3110
/* REG_DRVERLYINT */
3111
/* REG_BCN_MAX_ERR */
3112
/* REG_BCNTCFG */ /* (0x510) */
3113
/* REG_DUAL_TSF_RST */
3114
/* REG_BCN_CTRL */ /* (0x550) */
3115
3116
#ifdef CONFIG_CONCURRENT_MODE
3117
if (padapter->hw_port == HW_PORT1)
3118
bcn_ctrl_reg = REG_BCN_CTRL_1;
3119
#endif
3120
3121
/* BCN interval */
3122
rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)&pmlmeinfo->bcn_interval);
3123
3124
rtw_write8(padapter, REG_ATIMWND, 0x02);/* 2ms */
3125
3126
_InitBeaconParameters_8814A(padapter);
3127
3128
rtw_write8(padapter, REG_SLOT, 0x09);
3129
3130
value32 = rtw_read32(padapter, REG_TCR);
3131
value32 &= ~TSFRST;
3132
rtw_write32(padapter, REG_TCR, value32);
3133
3134
value32 |= TSFRST;
3135
rtw_write32(padapter, REG_TCR, value32);
3136
3137
/* NOTE: Fix test chip's bug (about contention windows's randomness) */
3138
rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
3139
rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
3140
3141
_BeaconFunctionEnable(padapter, _TRUE, _TRUE);
3142
3143
ResumeTxBeacon(padapter);
3144
3145
/* rtw_write8(padapter, 0x422, rtw_read8(padapter, 0x422)|BIT(6)); */
3146
3147
/* rtw_write8(padapter, 0x541, 0xff); */
3148
3149
/* rtw_write8(padapter, 0x542, rtw_read8(padapter, 0x541)|BIT(0)); */
3150
3151
rtw_write8(padapter, bcn_ctrl_reg, rtw_read8(padapter, bcn_ctrl_reg) | DIS_BCNQ_SUB);
3152
3153
}
3154
3155
static void hw_var_set_monitor(PADAPTER Adapter, u8 variable, u8 *val)
3156
{
3157
u32 rcr_bits;
3158
u16 value_rxfltmap2;
3159
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3160
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
3161
3162
if (*((u8 *)val) == _HW_STATE_MONITOR_) {
3163
3164
#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
3165
rcr_bits = RCR_AAP | RCR_APM | RCR_AM | RCR_AB | RCR_APWRMGT | RCR_ADF | RCR_AMF | RCR_APP_PHYST_RXFF;
3166
#else
3167
/* Receive all type */
3168
rcr_bits = RCR_AAP | RCR_APM | RCR_AM | RCR_AB | RCR_APWRMGT | RCR_ADF | RCR_ACF | RCR_AMF | RCR_APP_PHYST_RXFF;
3169
3170
/* Append FCS */
3171
rcr_bits |= RCR_APPFCS;
3172
#endif
3173
#if 0
3174
/*
3175
CRC and ICV packet will drop in recvbuf2recvframe()
3176
We no turn on it.
3177
*/
3178
rcr_bits |= (RCR_ACRC32 | RCR_AICV);
3179
#endif
3180
3181
rtw_hal_get_hwreg(Adapter, HW_VAR_RCR, (u8 *)&pHalData->rcr_backup);
3182
rtw_hal_set_hwreg(Adapter, HW_VAR_RCR, (u8 *)&rcr_bits);
3183
3184
/* Receive all data frames */
3185
value_rxfltmap2 = 0xFFFF;
3186
rtw_write16(Adapter, REG_RXFLTMAP2, value_rxfltmap2);
3187
3188
#if 0
3189
/* tx pause */
3190
rtw_write8(padapter, REG_TXPAUSE, 0xFF);
3191
#endif
3192
} else {
3193
/* do nothing */
3194
}
3195
3196
}
3197
3198
static void hw_var_set_opmode(PADAPTER Adapter, u8 variable, u8 *val)
3199
{
3200
u8 val8;
3201
u8 mode = *((u8 *)val);
3202
static u8 isMonitor = _FALSE;
3203
3204
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3205
3206
if (isMonitor == _TRUE) {
3207
/* reset RCR from backup */
3208
rtw_hal_set_hwreg(Adapter, HW_VAR_RCR, (u8 *)&pHalData->rcr_backup);
3209
rtw_hal_rcr_set_chk_bssid(Adapter, MLME_ACTION_NONE);
3210
isMonitor = _FALSE;
3211
}
3212
3213
if (mode == _HW_STATE_MONITOR_) {
3214
isMonitor = _TRUE;
3215
/* set net_type */
3216
Set_MSR(Adapter, _HW_STATE_NOLINK_);
3217
3218
hw_var_set_monitor(Adapter, variable, val);
3219
return;
3220
}
3221
3222
rtw_hal_set_hwreg(Adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(Adapter)); /* set mac addr to mac register */
3223
3224
#ifdef CONFIG_CONCURRENT_MODE
3225
if (Adapter->hw_port == HW_PORT1) {
3226
/* disable Port1 TSF update */
3227
rtw_iface_disable_tsf_update(Adapter);
3228
3229
/* set net_type */
3230
Set_MSR(Adapter, mode);
3231
3232
RTW_INFO("%s()-%d mode = %d\n", __FUNCTION__, __LINE__, mode);
3233
3234
if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
3235
if (!rtw_mi_get_ap_num(Adapter) && !rtw_mi_get_mesh_num(Adapter)) {
3236
StopTxBeacon(Adapter);
3237
#ifdef CONFIG_PCI_HCI
3238
UpdateInterruptMask8814AE(Adapter, 0, 0, RT_BCN_INT_MASKS, 0);
3239
#else /* CONFIG_PCI_HCI */
3240
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
3241
3242
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
3243
rtw_write8(Adapter, REG_DRVERLYINT, 0x05);/* restore early int time to 5ms */
3244
UpdateInterruptMask8814AU(Adapter, _TRUE, 0, IMR_BCNDMAINT0_8812);
3245
#endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
3246
3247
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
3248
UpdateInterruptMask8814AU(Adapter, _TRUE , 0, (IMR_TXBCN0ERR_8812 | IMR_TXBCN0OK_8812));
3249
#endif/* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
3250
3251
#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
3252
#endif /* CONFIG_PCI_HCI */
3253
}
3254
3255
rtw_write8(Adapter, REG_BCN_CTRL_1, DIS_TSF_UDT | DIS_ATIM); /* disable atim wnd and disable beacon function */
3256
/* rtw_write8(Adapter,REG_BCN_CTRL_1, DIS_TSF_UDT | EN_BCN_FUNCTION); */
3257
} else if (mode == _HW_STATE_ADHOC_) {
3258
#ifdef RTL8814AE_SW_BCN
3259
/*Beacon is polled to TXBUF*/
3260
rtw_write16(Adapter, REG_CR, rtw_read16(Adapter, REG_CR) | BIT(8));
3261
RTW_INFO("%s-%d: enable SW BCN, REG_CR=0x%x\n", __func__, __LINE__, rtw_read32(Adapter, REG_CR));
3262
#endif
3263
ResumeTxBeacon(Adapter);
3264
rtw_write8(Adapter, REG_BCN_CTRL_1, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
3265
} else if (mode == _HW_STATE_AP_) {
3266
#ifdef CONFIG_PCI_HCI
3267
UpdateInterruptMask8814AE(Adapter, RT_BCN_INT_MASKS, 0, 0, 0);
3268
#else
3269
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
3270
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
3271
UpdateInterruptMask8814AU(Adapter, _TRUE , IMR_BCNDMAINT0_8812, 0);
3272
#endif/* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
3273
3274
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
3275
UpdateInterruptMask8814AU(Adapter, _TRUE , (IMR_TXBCN0ERR_8812 | IMR_TXBCN0OK_8812), 0);
3276
#endif/* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
3277
3278
#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
3279
#endif
3280
3281
rtw_write8(Adapter, REG_BCN_CTRL_1, DIS_TSF_UDT | DIS_BCNQ_SUB);
3282
3283
#ifdef RTL8814AE_SW_BCN
3284
rtw_write16(Adapter, REG_CR, rtw_read16(Adapter, REG_CR) | BIT(8));
3285
RTW_INFO("%s-%d: enable SW BCN, REG_CR=0x%x\n", __func__, __LINE__, rtw_read32(Adapter, REG_CR));
3286
#endif
3287
3288
/* enable to rx data frame */
3289
rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
3290
3291
/* Beacon Control related register for first time */
3292
rtw_write8(Adapter, REG_BCNDMATIM, 0x02); /* 2ms */
3293
3294
/* rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF); */
3295
rtw_write8(Adapter, REG_ATIMWND_1, 0x0c); /* 12ms for port1 */
3296
3297
rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
3298
3299
/* reset TSF2 */
3300
rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1));
3301
3302
/* enable BCN1 Function for if2 */
3303
/* don't enable update TSF1 for if2 (due to TSF update when beacon/probe rsp are received) */
3304
rtw_write8(Adapter, REG_BCN_CTRL_1, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB));
3305
3306
#ifdef CONFIG_CONCURRENT_MODE
3307
if (!rtw_mi_buddy_check_mlmeinfo_state(Adapter, WIFI_FW_ASSOC_SUCCESS))
3308
rtw_write8(Adapter, REG_BCN_CTRL,
3309
rtw_read8(Adapter, REG_BCN_CTRL) & ~EN_BCN_FUNCTION);
3310
#endif
3311
/* BCN1 TSF will sync to BCN0 TSF with offset(0x518) if if1_sta linked */
3312
/* rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(5)); */
3313
/* rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(3)); */
3314
3315
/* dis BCN0 ATIM WND if if1 is station */
3316
rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL) | DIS_ATIM);
3317
3318
#ifdef CONFIG_TSF_RESET_OFFLOAD
3319
/* Reset TSF for STA+AP concurrent mode */
3320
if (DEV_STA_LD_NUM(adapter_to_dvobj(Adapter))) {
3321
if (rtw_hal_reset_tsf(Adapter, HW_PORT1) == _FAIL)
3322
RTW_INFO("ERROR! %s()-%d: Reset port1 TSF fail\n",
3323
__FUNCTION__, __LINE__);
3324
}
3325
#endif /* CONFIG_TSF_RESET_OFFLOAD */
3326
}
3327
} else /* else for port0 */
3328
#endif /* CONFIG_CONCURRENT_MODE */
3329
{
3330
#ifdef CONFIG_MI_WITH_MBSSID_CAM /*For Port0 - MBSS CAM*/
3331
hw_var_set_opmode_mbid(Adapter, mode);
3332
#else
3333
/* disable Port0 TSF update */
3334
rtw_iface_disable_tsf_update(Adapter);
3335
3336
/* set net_type */
3337
Set_MSR(Adapter, mode);
3338
3339
RTW_INFO("%s()-%d mode = %d\n", __FUNCTION__, __LINE__, mode);
3340
3341
if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
3342
#ifdef CONFIG_CONCURRENT_MODE
3343
if (!rtw_mi_get_ap_num(Adapter) && !rtw_mi_get_mesh_num(Adapter))
3344
#endif /* CONFIG_CONCURRENT_MODE */
3345
{
3346
StopTxBeacon(Adapter);
3347
#ifdef CONFIG_PCI_HCI
3348
UpdateInterruptMask8814AE(Adapter, 0, 0, RT_BCN_INT_MASKS, 0);
3349
#else
3350
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
3351
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
3352
rtw_write8(Adapter, REG_DRVERLYINT, 0x05);/* restore early int time to 5ms */
3353
UpdateInterruptMask8814AU(Adapter, _TRUE, 0, IMR_BCNDMAINT0_8812);
3354
#endif/* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
3355
3356
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
3357
UpdateInterruptMask8814AU(Adapter, _TRUE , 0, (IMR_TXBCN0ERR_8812 | IMR_TXBCN0OK_8812));
3358
#endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
3359
3360
#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
3361
#endif
3362
}
3363
3364
rtw_write8(Adapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_ATIM); /* disable atim wnd */
3365
/* rtw_write8(Adapter,REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION); */
3366
} else if (mode == _HW_STATE_ADHOC_) {
3367
#ifdef RTL8814AE_SW_BCN
3368
rtw_write16(Adapter, REG_CR, rtw_read16(Adapter, REG_CR) | BIT(8));
3369
RTW_INFO("%s-%d: enable SW BCN, REG_CR=0x%x\n", __func__, __LINE__, rtw_read32(Adapter, REG_CR));
3370
#endif
3371
ResumeTxBeacon(Adapter);
3372
rtw_write8(Adapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
3373
} else if (mode == _HW_STATE_AP_) {
3374
#ifdef CONFIG_PCI_HCI
3375
UpdateInterruptMask8814AE(Adapter, RT_BCN_INT_MASKS, 0, 0, 0);
3376
#else
3377
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
3378
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
3379
UpdateInterruptMask8814AU(Adapter, _TRUE , IMR_BCNDMAINT0_8812, 0);
3380
#endif/* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
3381
3382
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
3383
UpdateInterruptMask8814AU(Adapter, _TRUE , (IMR_TXBCN0ERR_8812 | IMR_TXBCN0OK_8812), 0);
3384
#endif/* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
3385
3386
#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
3387
#endif
3388
3389
rtw_write8(Adapter, REG_BCN_CTRL, DIS_TSF_UDT | DIS_BCNQ_SUB);
3390
/*Beacon is polled to TXBUF*/
3391
#ifdef RTL8814AE_SW_BCN
3392
rtw_write16(Adapter, REG_CR, rtw_read16(Adapter, REG_CR) | BIT(8));
3393
RTW_INFO("%s-%d: enable SW BCN, REG_CR=0x%x\n", __func__, __LINE__, rtw_read32(Adapter, REG_CR));
3394
#endif
3395
3396
/* enable to rx data frame */
3397
rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
3398
3399
/* Beacon Control related register for first time */
3400
rtw_write8(Adapter, REG_BCNDMATIM, 0x02); /* 2ms */
3401
3402
/* rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF); */
3403
rtw_write8(Adapter, REG_ATIMWND, 0x0c); /* 12ms */
3404
3405
rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
3406
3407
/* reset TSF */
3408
rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
3409
3410
/* enable BCN0 Function for if1 */
3411
/* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */
3412
rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB));
3413
3414
#ifdef CONFIG_CONCURRENT_MODE
3415
if (!rtw_mi_buddy_check_mlmeinfo_state(Adapter, WIFI_FW_ASSOC_SUCCESS))
3416
rtw_write8(Adapter, REG_BCN_CTRL_1,
3417
rtw_read8(Adapter, REG_BCN_CTRL_1) & ~EN_BCN_FUNCTION);
3418
#endif
3419
3420
/* dis BCN1 ATIM WND if if2 is station */
3421
rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1) | DIS_ATIM);
3422
#ifdef CONFIG_TSF_RESET_OFFLOAD
3423
/* Reset TSF for STA+AP concurrent mode */
3424
if (DEV_STA_LD_NUM(adapter_to_dvobj(Adapter))) {
3425
if (rtw_hal_reset_tsf(Adapter, HW_PORT0) == _FAIL)
3426
RTW_INFO("ERROR! %s()-%d: Reset port0 TSF fail\n",
3427
__FUNCTION__, __LINE__);
3428
}
3429
#endif /* CONFIG_TSF_RESET_OFFLOAD */
3430
}
3431
#endif /* #ifdef CONFIG_MI_WITH_MBSSID_CAM*/
3432
}
3433
}
3434
3435
static void rtw_store_all_sta_hwseq(_adapter *padapter)
3436
{
3437
_irqL irqL;
3438
_list *plist, *phead;
3439
u8 index;
3440
u16 hw_seq[NUM_STA];
3441
u32 shcut_addr = 0;
3442
struct sta_info *psta;
3443
struct sta_priv *pstapriv = &padapter->stapriv;
3444
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
3445
struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
3446
3447
_rtw_memset(hw_seq, 0, NUM_STA);
3448
3449
/* save each HW sequence of mac id from report fifo */
3450
for (index = 0; index < macid_ctl->num && index < NUM_STA; index++) {
3451
if (rtw_macid_is_used(macid_ctl, index)) {
3452
rtw_write16(padapter, 0x140, 0x662 | ((index & BIT5) >> 5));
3453
shcut_addr = 0x8000;
3454
shcut_addr = (shcut_addr | ((index & 0x1f) << 7) | (10 << 2)) + 1;
3455
3456
/* 2 byte un-alignment handling */
3457
if (shcut_addr%2)
3458
hw_seq[index] = le16_to_cpu(rtw_read8(padapter, shcut_addr) + (rtw_read8(padapter, shcut_addr + 1) << 8));
3459
else
3460
hw_seq[index] = rtw_read16(padapter, shcut_addr);
3461
/* RTW_INFO("mac_id:%d is used, hw_seq[index]=%d\n", index, hw_seq[index]); */
3462
}
3463
}
3464
3465
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
3466
for (index = 0; index < NUM_STA; index++) {
3467
psta = NULL;
3468
3469
phead = &(pstapriv->sta_hash[index]);
3470
plist = get_next(phead);
3471
3472
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
3473
psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
3474
plist = get_next(plist);
3475
3476
psta->hwseq = hw_seq[psta->cmn.mac_id];
3477
/* RTW_INFO(" psta->mac_id=%d, psta->hwseq=%d\n" , psta->cmn.mac_id, psta->hwseq); */
3478
}
3479
3480
}
3481
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
3482
3483
3484
}
3485
3486
static void rtw_restore_all_sta_hwseq(_adapter *padapter)
3487
{
3488
_irqL irqL;
3489
_list *plist, *phead;
3490
u8 index;
3491
u16 hw_seq[NUM_STA];
3492
u32 shcut_addr = 0;
3493
struct sta_info *psta;
3494
struct sta_priv *pstapriv = &padapter->stapriv;
3495
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
3496
struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
3497
3498
_rtw_memset(hw_seq, 0, NUM_STA);
3499
3500
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
3501
for (index = 0; index < NUM_STA; index++) {
3502
psta = NULL;
3503
3504
phead = &(pstapriv->sta_hash[index]);
3505
plist = get_next(phead);
3506
3507
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
3508
psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
3509
plist = get_next(plist);
3510
3511
hw_seq[psta->cmn.mac_id] = psta->hwseq;
3512
/* RTW_INFO(" psta->mac_id=%d, psta->hwseq=%d\n", psta->mac_id, psta->hwseq); */
3513
}
3514
3515
}
3516
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
3517
3518
/* restore each HW sequence of mac id to report fifo */
3519
for (index = 0; index < macid_ctl->num && index < NUM_STA; index++) {
3520
if (rtw_macid_is_used(macid_ctl, index)) {
3521
rtw_write16(padapter, 0x140, 0x662 | ((index & BIT5) >> 5));
3522
shcut_addr = 0x8000;
3523
shcut_addr = (shcut_addr | ((index & 0x1f) << 7) | (10 << 2)) + 1;
3524
rtw_write16(padapter, shcut_addr, hw_seq[index]);
3525
/* RTW_INFO("mac_id:%d is used, hw_seq[index]=%d\n", index, hw_seq[index]); */
3526
}
3527
}
3528
3529
3530
}
3531
3532
u8 SetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval)
3533
{
3534
PHAL_DATA_TYPE pHalData;
3535
u8 ret = _SUCCESS;
3536
u8 val8;
3537
u16 val16;
3538
u32 val32;
3539
3540
3541
pHalData = GET_HAL_DATA(padapter);
3542
3543
switch (variable) {
3544
case HW_VAR_SET_OPMODE:
3545
hw_var_set_opmode(padapter, variable, pval);
3546
break;
3547
3548
case HW_VAR_BASIC_RATE:
3549
rtw_var_set_basic_rate(padapter, pval);
3550
break;
3551
3552
case HW_VAR_TXPAUSE:
3553
rtw_write8(padapter, REG_TXPAUSE, *pval);
3554
break;
3555
3556
case HW_VAR_SLOT_TIME:
3557
rtw_write8(padapter, REG_SLOT, *pval);
3558
break;
3559
3560
case HW_VAR_RESP_SIFS:
3561
/* SIFS_Timer = 0x0a0a0808; */
3562
/* RESP_SIFS for CCK */
3563
rtw_write8(padapter, REG_RESP_SIFS_CCK, pval[0]); /* SIFS_T2T_CCK (0x08) */
3564
rtw_write8(padapter, REG_RESP_SIFS_CCK + 1, pval[1]); /* SIFS_R2T_CCK(0x08) */
3565
/* RESP_SIFS for OFDM */
3566
rtw_write8(padapter, REG_RESP_SIFS_OFDM, pval[2]); /* SIFS_T2T_OFDM (0x0a) */
3567
rtw_write8(padapter, REG_RESP_SIFS_OFDM + 1, pval[3]); /* SIFS_R2T_OFDM(0x0a) */
3568
break;
3569
3570
case HW_VAR_ACK_PREAMBLE: {
3571
u8 bShortPreamble = *pval;
3572
3573
/* Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */
3574
val8 = (pHalData->nCur40MhzPrimeSC) << 5;
3575
if (bShortPreamble)
3576
val8 |= 0x80;
3577
rtw_write8(padapter, REG_RRSR + 2, val8);
3578
}
3579
break;
3580
3581
case HW_VAR_CAM_INVALID_ALL:
3582
val32 = BIT(31) | BIT(30);
3583
rtw_write32(padapter, REG_CAMCMD, val32);
3584
break;
3585
3586
case HW_VAR_AC_PARAM_VO:
3587
rtw_write32(padapter, REG_EDCA_VO_PARAM, *(u32 *)pval);
3588
break;
3589
3590
case HW_VAR_AC_PARAM_VI:
3591
rtw_write32(padapter, REG_EDCA_VI_PARAM, *(u32 *)pval);
3592
break;
3593
3594
case HW_VAR_AC_PARAM_BE:
3595
pHalData->ac_param_be = *(u32 *)pval;
3596
rtw_write32(padapter, REG_EDCA_BE_PARAM, *(u32 *)pval);
3597
break;
3598
3599
case HW_VAR_AC_PARAM_BK:
3600
rtw_write32(padapter, REG_EDCA_BK_PARAM, *(u32 *)pval);
3601
break;
3602
3603
case HW_VAR_ACM_CTRL: {
3604
u8 acm_ctrl;
3605
u8 AcmCtrl;
3606
3607
acm_ctrl = *(u8 *)pval;
3608
AcmCtrl = rtw_read8(padapter, REG_ACMHWCTRL);
3609
3610
if (acm_ctrl > 1)
3611
AcmCtrl = AcmCtrl | 0x1;
3612
3613
if (acm_ctrl & BIT(1))
3614
AcmCtrl |= AcmHw_VoqEn;
3615
else
3616
AcmCtrl &= (~AcmHw_VoqEn);
3617
3618
if (acm_ctrl & BIT(2))
3619
AcmCtrl |= AcmHw_ViqEn;
3620
else
3621
AcmCtrl &= (~AcmHw_ViqEn);
3622
3623
if (acm_ctrl & BIT(3))
3624
AcmCtrl |= AcmHw_BeqEn;
3625
else
3626
AcmCtrl &= (~AcmHw_BeqEn);
3627
3628
RTW_INFO("[HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
3629
rtw_write8(padapter, REG_ACMHWCTRL, AcmCtrl);
3630
}
3631
break;
3632
#ifdef CONFIG_80211N_HT
3633
case HW_VAR_AMPDU_FACTOR: {
3634
u32 AMPDULen = *(u8 *)pval;
3635
3636
3637
if (AMPDULen < VHT_AGG_SIZE_256K)
3638
AMPDULen = (0x2000 << (*((u8 *)pval))) - 1;
3639
else
3640
AMPDULen = 0x3ffff;
3641
rtw_write32(padapter, REG_AMPDU_MAX_LENGTH_8814A, AMPDULen);
3642
/* RTW_INFO("SetHwReg8814AU(): HW_VAR_AMPDU_FACTOR %x\n" ,AMPDULen); */
3643
}
3644
break;
3645
#endif /* CONFIG_80211N_HT */
3646
case HW_VAR_H2C_FW_PWRMODE: {
3647
u8 psmode = *pval;
3648
rtl8814_set_FwPwrMode_cmd(padapter, psmode);
3649
}
3650
break;
3651
3652
case HW_VAR_H2C_FW_JOINBSSRPT:
3653
rtl8814_set_FwJoinBssReport_cmd(padapter, *pval);
3654
break;
3655
case HW_VAR_DL_RSVD_PAGE:
3656
#ifdef CONFIG_BT_COEXIST
3657
if (pHalData->EEPROMBluetoothCoexist == 1) {
3658
if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
3659
rtl8814a_download_BTCoex_AP_mode_rsvd_page(padapter);
3660
}
3661
#endif /* CONFIG_BT_COEXIST */
3662
break;
3663
3664
#ifdef CONFIG_P2P_PS
3665
case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
3666
rtl8814_set_p2p_ps_offload_cmd(padapter, *pval);
3667
break;
3668
#endif /* CONFIG_P2P_PS */
3669
3670
case HW_VAR_EFUSE_USAGE:
3671
pHalData->EfuseUsedPercentage = *pval;
3672
break;
3673
3674
case HW_VAR_EFUSE_BYTES:
3675
pHalData->EfuseUsedBytes = *(u16 *)pval;
3676
break;
3677
#if 0
3678
case HW_VAR_EFUSE_BT_USAGE:
3679
#ifdef HAL_EFUSE_MEMORY
3680
pHalData->EfuseHal.BTEfuseUsedPercentage = *pval;
3681
#endif /* HAL_EFUSE_MEMORY */
3682
break;
3683
3684
case HW_VAR_EFUSE_BT_BYTES:
3685
#ifdef HAL_EFUSE_MEMORY
3686
pHalData->EfuseHal.BTEfuseUsedBytes = *(u16 *)pval;
3687
#else /* HAL_EFUSE_MEMORY */
3688
BTEfuseUsedBytes = *(u16 *)pval;
3689
#endif /* HAL_EFUSE_MEMORY */
3690
break;
3691
#endif /* 0 */
3692
case HW_VAR_FIFO_CLEARN_UP: {
3693
struct pwrctrl_priv *pwrpriv;
3694
u8 trycnt = 100;
3695
3696
pwrpriv = adapter_to_pwrctl(padapter);
3697
3698
/* pause tx */
3699
rtw_write8(padapter, REG_TXPAUSE, 0xff);
3700
3701
/* keep sn */
3702
rtw_store_all_sta_hwseq(padapter);
3703
3704
if (pwrpriv->bkeepfwalive != _TRUE) {
3705
/* RX DMA stop */
3706
val32 = rtw_read32(padapter, REG_RXPKT_NUM);
3707
val32 |= RW_RELEASE_EN;
3708
rtw_write32(padapter, REG_RXPKT_NUM, val32);
3709
do {
3710
val32 = rtw_read32(padapter, REG_RXPKT_NUM);
3711
val32 &= RXDMA_IDLE;
3712
if (val32)
3713
break;
3714
} while (--trycnt);
3715
if (trycnt == 0)
3716
RTW_INFO("[HW_VAR_FIFO_CLEARN_UP] Stop RX DMA failed......\n");
3717
3718
/* RQPN Load 0 */
3719
rtw_write16(padapter, REG_RQPN_NPQ, 0x0);
3720
rtw_write32(padapter, REG_RQPN, 0x80000000);
3721
rtw_mdelay_os(10);
3722
}
3723
}
3724
break;
3725
3726
case HW_VAR_RESTORE_HW_SEQ:
3727
rtw_restore_all_sta_hwseq(padapter);
3728
break;
3729
3730
case HW_VAR_CHECK_TXBUF: {
3731
u8 retry_limit;
3732
u32 reg_230 = 0, reg_234 = 0, reg_238 = 0, reg_23c = 0, reg_240 = 0;
3733
u32 init_reg_230 = 0, init_reg_234 = 0, init_reg_238 = 0, init_reg_23c = 0, init_reg_240 = 0;
3734
systime start = rtw_get_current_time();
3735
u32 pass_ms;
3736
int i = 0;
3737
3738
retry_limit = 0x01;
3739
3740
val16 = BIT_SRL(retry_limit) | BIT_LRL(retry_limit);
3741
rtw_write16(padapter, REG_RETRY_LIMIT, val16);
3742
3743
while (rtw_get_passing_time_ms(start) < 2000
3744
&& !RTW_CANNOT_RUN(padapter)
3745
) {
3746
reg_230 = rtw_read32(padapter, REG_FIFOPAGE_INFO_1_8814A);
3747
reg_234 = rtw_read32(padapter, REG_FIFOPAGE_INFO_2_8814A);
3748
reg_238 = rtw_read32(padapter, REG_FIFOPAGE_INFO_3_8814A);
3749
reg_23c = rtw_read32(padapter, REG_FIFOPAGE_INFO_4_8814A);
3750
reg_240 = rtw_read32(padapter, REG_FIFOPAGE_INFO_5_8814A);
3751
3752
if (i == 0) {
3753
init_reg_230 = reg_230;
3754
init_reg_234 = reg_234;
3755
init_reg_238 = reg_238;
3756
init_reg_23c = reg_23c;
3757
init_reg_240 = reg_240;
3758
}
3759
3760
i++;
3761
if ((((reg_230 & 0x0c) != ((reg_230 >> 16) & 0x0c)) || ((reg_234 & 0x0c) != ((reg_234 >> 16) & 0x0c))
3762
|| ((reg_238 & 0x0c) != ((reg_238 >> 16) & 0x0c)) || ((reg_23c & 0x0c) != ((reg_23c >> 16) & 0x0c))
3763
|| ((reg_240 & 0x0c) != ((reg_240 >> 16) & 0x0c)))) {
3764
/* RTW_INFO("%s: (HW_VAR_CHECK_TXBUF)TXBUF NOT empty - 0x230=0x%08x, 0x234=0x%08x 0x238=0x%08x,"
3765
" 0x23c=0x%08x, 0x240=0x%08x (%d)\n"
3766
, __FUNCTION__, reg_230, reg_234, reg_238, reg_23c, reg_240, i); */
3767
rtw_msleep_os(10);
3768
} else
3769
break;
3770
}
3771
3772
pass_ms = rtw_get_passing_time_ms(start);
3773
3774
if (RTW_CANNOT_RUN(padapter))
3775
RTW_INFO("bDriverStopped or bSurpriseRemoved\n");
3776
else if (pass_ms >= 2000 || (((reg_230 & 0x0c) != ((reg_230 >> 16) & 0x0c)) || ((reg_234 & 0x0c) != ((reg_234 >> 16) & 0x0c))
3777
|| ((reg_238 & 0x0c) != ((reg_238 >> 16) & 0x0c)) || ((reg_23c & 0x0c) != ((reg_23c >> 16) & 0x0c))
3778
|| ((reg_240 & 0x0c) != ((reg_240 >> 16) & 0x0c)))) {
3779
RTW_PRINT("%s:(HW_VAR_CHECK_TXBUF)NOT empty(%d) in %d ms\n", __func__, i, pass_ms);
3780
RTW_PRINT("%s:(HW_VAR_CHECK_TXBUF) 0x230=0x%08x, 0x234=0x%08x 0x238=0x%08x, 0x23c=0x%08x, 0x240=0x%08x (0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x)\n", __func__,
3781
reg_230, reg_234, reg_238, reg_23c, reg_240
3782
, init_reg_230, init_reg_234, init_reg_238, init_reg_23c, init_reg_240);
3783
/* rtw_warn_on(1); */
3784
} else
3785
RTW_INFO("%s:(HW_VAR_CHECK_TXBUF)TXBUF Empty(%d) in %d ms\n", __FUNCTION__, i, pass_ms);
3786
3787
retry_limit = RL_VAL_STA;
3788
val16 = BIT_SRL(retry_limit) | BIT_LRL(retry_limit);
3789
rtw_write16(padapter, REG_RETRY_LIMIT, val16);
3790
}
3791
3792
break;
3793
3794
case HW_VAR_NAV_UPPER: {
3795
u32 usNavUpper = *((u32 *)pval);
3796
3797
if (usNavUpper > HAL_NAV_UPPER_UNIT * 0xFF) {
3798
RTW_INFO("%s: [HW_VAR_NAV_UPPER] set value(0x%08X us) is larger than (%d * 0xFF)!\n",
3799
__FUNCTION__, usNavUpper, HAL_NAV_UPPER_UNIT);
3800
break;
3801
}
3802
3803
/* The value of ((usNavUpper + HAL_NAV_UPPER_UNIT - 1) / HAL_NAV_UPPER_UNIT) */
3804
/* is getting the upper integer. */
3805
usNavUpper = (usNavUpper + HAL_NAV_UPPER_UNIT - 1) / HAL_NAV_UPPER_UNIT;
3806
rtw_write8(padapter, REG_NAV_UPPER, (u8)usNavUpper);
3807
}
3808
break;
3809
3810
case HW_VAR_BCN_VALID:
3811
#ifdef CONFIG_CONCURRENT_MODE
3812
if (padapter->hw_port == HW_PORT1) {
3813
/* BCN_VALID, BIT31 of REG_FIFOPAGE_CTRL_2_8814A, write 1 to clear, Clear by sw */
3814
val8 = rtw_read8(padapter, REG_FIFOPAGE_CTRL_2_8814A + 3);
3815
val8 |= BIT(7);
3816
rtw_write8(padapter, REG_FIFOPAGE_CTRL_2_8814A + 3, val8);
3817
} else
3818
#endif
3819
{
3820
/* BCN_VALID, BIT15 of REG_FIFOPAGE_CTRL_2_8814A, write 1 to clear, Clear by sw */
3821
val8 = rtw_read8(padapter, REG_FIFOPAGE_CTRL_2_8814A + 1);
3822
val8 |= BIT(7);
3823
rtw_write8(padapter, REG_FIFOPAGE_CTRL_2_8814A + 1, val8);
3824
}
3825
break;
3826
3827
case HW_VAR_DL_BCN_SEL:
3828
#if 0 /* for MBSSID, so far we don't need this */
3829
#ifdef CONFIG_CONCURRENT_MODE
3830
if (IS_HARDWARE_TYPE_8821(padapter) && padapter->hw_port == HW_PORT1) {
3831
/* SW_BCN_SEL - Port1 */
3832
val8 = rtw_read8(padapter, REG_AUTO_LLT_8814A);
3833
val8 |= BIT(2);
3834
rtw_write8(padapter, REG_AUTO_LLT_8814A, val8);
3835
} else
3836
#endif /* CONFIG_CONCURRENT_MODE */
3837
{
3838
/* SW_BCN_SEL - Port0 , BIT_r_EN_BCN_SW_HEAD_SEL */
3839
val8 = rtw_read8(padapter, REG_AUTO_LLT_8814A);
3840
val8 &= ~BIT(2);
3841
rtw_write8(padapter, REG_AUTO_LLT_8814A, val8);
3842
}
3843
#endif /* for MBSSID, so far we don't need this */
3844
break;
3845
3846
case HW_VAR_WIRELESS_MODE: {
3847
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
3848
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
3849
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
3850
u8 R2T_SIFS = 0, SIFS_Timer = 0;
3851
u8 wireless_mode = *pval;
3852
3853
if ((wireless_mode == WIRELESS_11BG) || (wireless_mode == WIRELESS_11G))
3854
SIFS_Timer = 0xa;
3855
else
3856
SIFS_Timer = 0xe;
3857
3858
/* SIFS for OFDM Data ACK */
3859
rtw_write8(padapter, REG_SIFS_CTX + 1, SIFS_Timer);
3860
/* SIFS for OFDM consecutive tx like CTS data! */
3861
rtw_write8(padapter, REG_SIFS_TRX + 1, SIFS_Timer);
3862
3863
rtw_write8(padapter, REG_SPEC_SIFS + 1, SIFS_Timer);
3864
rtw_write8(padapter, REG_MAC_SPEC_SIFS + 1, SIFS_Timer);
3865
3866
/* 20100719 Joseph: Revise SIFS setting due to Hardware register definition change. */
3867
rtw_write8(padapter, REG_RESP_SIFS_OFDM + 1, SIFS_Timer);
3868
rtw_write8(padapter, REG_RESP_SIFS_OFDM, SIFS_Timer);
3869
3870
/* */
3871
/* Adjust R2T SIFS for IOT issue. Add by hpfan 2013.01.25 */
3872
/* Set R2T SIFS to 0x0a for Atheros IOT. Add by hpfan 2013.02.22 */
3873
/* */
3874
/* Mac has 10 us delay so use 0xa value is enough. */
3875
R2T_SIFS = 0xa;
3876
#ifdef CONFIG_80211AC_VHT
3877
if (wireless_mode & WIRELESS_11_5AC &&
3878
/* MgntLinkStatusQuery(Adapter) && */
3879
TEST_FLAG(pmlmepriv->vhtpriv.ldpc_cap, LDPC_VHT_ENABLE_RX) &&
3880
TEST_FLAG(pmlmepriv->vhtpriv.stbc_cap, STBC_VHT_ENABLE_RX)) {
3881
if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)
3882
R2T_SIFS = 0x8;
3883
else
3884
R2T_SIFS = 0xa;
3885
}
3886
#endif /* CONFIG_80211AC_VHT */
3887
3888
rtw_write8(padapter, REG_RESP_SIFS_OFDM + 1, R2T_SIFS);
3889
}
3890
break;
3891
3892
#ifdef CONFIG_BEAMFORMING /*PHYDM_BF - (BEAMFORMING_SUPPORT == 1)*/
3893
/*add by YuChen for PHYDM-TxBF AutoTest HW Timer*/
3894
case HW_VAR_HW_REG_TIMER_INIT: {
3895
HAL_HW_TIMER_TYPE TimerType = (*(PHAL_HW_TIMER_TYPE)pval) >> 16;
3896
3897
rtw_write8(padapter, 0x164, 1);
3898
3899
if (TimerType == HAL_TIMER_TXBF)
3900
rtw_write32(padapter, 0x15C, (*(u16 *)pval));
3901
else if (TimerType == HAL_TIMER_EARLYMODE)
3902
rtw_write32(padapter, 0x160, 0x05000190);
3903
break;
3904
}
3905
case HW_VAR_HW_REG_TIMER_START: {
3906
HAL_HW_TIMER_TYPE TimerType = *(PHAL_HW_TIMER_TYPE)pval;
3907
3908
if (TimerType == HAL_TIMER_TXBF)
3909
rtw_write8(padapter, 0x15F, 0x5);
3910
else if (TimerType == HAL_TIMER_EARLYMODE)
3911
rtw_write8(padapter, 0x163, 0x5);
3912
break;
3913
}
3914
case HW_VAR_HW_REG_TIMER_RESTART: {
3915
HAL_HW_TIMER_TYPE TimerType = *(PHAL_HW_TIMER_TYPE)pval;
3916
3917
if (TimerType == HAL_TIMER_TXBF) {
3918
rtw_write8(padapter, 0x15F, 0x0);
3919
rtw_write8(padapter, 0x15F, 0x5);
3920
} else if (TimerType == HAL_TIMER_EARLYMODE) {
3921
rtw_write8(padapter, 0x163, 0x0);
3922
rtw_write8(padapter, 0x163, 0x5);
3923
}
3924
break;
3925
}
3926
case HW_VAR_HW_REG_TIMER_STOP: {
3927
HAL_HW_TIMER_TYPE TimerType = *(PHAL_HW_TIMER_TYPE)pval;
3928
3929
if (TimerType == HAL_TIMER_TXBF)
3930
rtw_write8(padapter, 0x15F, 0);
3931
else if (TimerType == HAL_TIMER_EARLYMODE)
3932
rtw_write8(padapter, 0x163, 0x0);
3933
break;
3934
}
3935
#endif/*#ifdef CONFIG_BEAMFORMING*/
3936
3937
#ifdef CONFIG_GPIO_WAKEUP
3938
case HW_SET_GPIO_WL_CTRL: {
3939
u8 enable = *pval;
3940
u8 value = rtw_read8(padapter, 0x4e);
3941
if (enable && (value & BIT(6))) {
3942
value &= ~BIT(6);
3943
rtw_write8(padapter, 0x4e, value);
3944
} else if (enable == _FALSE) {
3945
value |= BIT(6);
3946
rtw_write8(padapter, 0x4e, value);
3947
}
3948
RTW_INFO("%s: set WL control, 0x4E=0x%02X\n",
3949
__func__, rtw_read8(padapter, 0x4e));
3950
}
3951
break;
3952
#endif
3953
3954
#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
3955
case HW_VAR_TDLS_BCN_EARLY_C2H_RPT:
3956
rtl8814_set_BcnEarly_C2H_Rpt_cmd(padapter, *pval);
3957
break;
3958
#endif
3959
3960
default:
3961
ret = SetHwReg(padapter, variable, pval);
3962
break;
3963
}
3964
3965
return ret;
3966
}
3967
3968
struct qinfo_8814a {
3969
u32 head:11;
3970
u32 tail:11;
3971
u32 empty:1;
3972
u32 ac:2;
3973
u32 macid:7;
3974
};
3975
3976
struct bcn_qinfo_8814a {
3977
u16 head:12;
3978
u16 rsvd:4;
3979
};
3980
3981
void dump_qinfo_8814a(void *sel, struct qinfo_8814a *info, u32 pkt_num, const char *tag)
3982
{
3983
/* if (info->pkt_num) */
3984
RTW_PRINT_SEL(sel, "%shead:0x%02x, tail:0x%02x, pkt_num:%u, macid:%u, ac:%u\n"
3985
, tag ? tag : "", info->head, info->tail, pkt_num, info->macid, info->ac
3986
);
3987
}
3988
3989
void dump_bcn_qinfo_8814a(void *sel, struct bcn_qinfo_8814a *info, u32 pkt_num, const char *tag)
3990
{
3991
/* if (info->pkt_num) */
3992
RTW_PRINT_SEL(sel, "%shead:0x%02x, pkt_num:%u\n"
3993
, tag ? tag : "", info->head, pkt_num
3994
);
3995
}
3996
3997
void dump_mac_qinfo_8814a(void *sel, _adapter *adapter)
3998
{
3999
u32 q0_info;
4000
u32 q1_info;
4001
u32 q2_info;
4002
u32 q3_info;
4003
u32 q4_info;
4004
u32 q5_info;
4005
u32 q6_info;
4006
u32 q7_info;
4007
u32 mg_q_info;
4008
u32 hi_q_info;
4009
u16 bcn_q_info;
4010
u32 q0_q1_info;
4011
u32 q2_q3_info;
4012
u32 q4_q5_info;
4013
u32 q6_q7_info;
4014
u32 mg_hi_q_info;
4015
u32 cmd_bcn_q_info;
4016
4017
4018
q0_info = rtw_read32(adapter, REG_Q0_INFO);
4019
q1_info = rtw_read32(adapter, REG_Q1_INFO);
4020
q2_info = rtw_read32(adapter, REG_Q2_INFO);
4021
q3_info = rtw_read32(adapter, REG_Q3_INFO);
4022
q4_info = rtw_read32(adapter, REG_Q4_INFO);
4023
q5_info = rtw_read32(adapter, REG_Q5_INFO);
4024
q6_info = rtw_read32(adapter, REG_Q6_INFO);
4025
q7_info = rtw_read32(adapter, REG_Q7_INFO);
4026
mg_q_info = rtw_read32(adapter, REG_MGQ_INFO);
4027
hi_q_info = rtw_read32(adapter, REG_HGQ_INFO);
4028
bcn_q_info = rtw_read16(adapter, REG_BCNQ_INFO);
4029
4030
q0_q1_info = rtw_read32(adapter, REG_Q0_Q1_INFO_8814A);
4031
q2_q3_info = rtw_read32(adapter, REG_Q2_Q3_INFO_8814A);
4032
q4_q5_info = rtw_read32(adapter, REG_Q4_Q5_INFO_8814A);
4033
q6_q7_info = rtw_read32(adapter, REG_Q6_Q7_INFO_8814A);
4034
mg_hi_q_info = rtw_read32(adapter, REG_MGQ_HIQ_INFO_8814A);
4035
cmd_bcn_q_info = rtw_read32(adapter, REG_CMDQ_BCNQ_INFO_8814A);
4036
4037
dump_qinfo_8814a(sel, (struct qinfo_8814a *)&q0_info, q0_q1_info&0xFFF, "Q0 ");
4038
dump_qinfo_8814a(sel, (struct qinfo_8814a *)&q1_info, (q0_q1_info>>15)&0xFFF, "Q1 ");
4039
dump_qinfo_8814a(sel, (struct qinfo_8814a *)&q2_info, q2_q3_info&0xFFF, "Q2 ");
4040
dump_qinfo_8814a(sel, (struct qinfo_8814a *)&q3_info, (q2_q3_info>>15)&0xFFF, "Q3 ");
4041
dump_qinfo_8814a(sel, (struct qinfo_8814a *)&q4_info, q4_q5_info&0xFFF, "Q4 ");
4042
dump_qinfo_8814a(sel, (struct qinfo_8814a *)&q5_info, (q4_q5_info>>15)&0xFFF, "Q5 ");
4043
dump_qinfo_8814a(sel, (struct qinfo_8814a *)&q6_info, q6_q7_info&0xFFF, "Q6 ");
4044
dump_qinfo_8814a(sel, (struct qinfo_8814a *)&q7_info, (q6_q7_info>>15)&0xFFF, "Q7 ");
4045
dump_qinfo_8814a(sel, (struct qinfo_8814a *)&mg_q_info, mg_hi_q_info&0xFFF, "MG ");
4046
dump_qinfo_8814a(sel, (struct qinfo_8814a *)&hi_q_info, (mg_hi_q_info>>15)&0xFFF, "HI ");
4047
dump_bcn_qinfo_8814a(sel, (struct bcn_qinfo_8814a *)&bcn_q_info, cmd_bcn_q_info&0xFFF, "BCN ");
4048
}
4049
4050
static void dump_mac_txfifo_8814a(void *sel, _adapter *adapter)
4051
{
4052
u32 hpq, lpq, npq, epq, pubq;
4053
4054
hpq = rtw_read32(adapter, REG_FIFOPAGE_INFO_1_8814A);
4055
lpq = rtw_read32(adapter, REG_FIFOPAGE_INFO_2_8814A);
4056
npq = rtw_read32(adapter, REG_FIFOPAGE_INFO_3_8814A);
4057
epq = rtw_read32(adapter, REG_FIFOPAGE_INFO_4_8814A);
4058
pubq = rtw_read32(adapter, REG_FIFOPAGE_INFO_5_8814A);
4059
4060
hpq = (hpq & 0xFFF0000)>>16;
4061
lpq = (lpq & 0xFFF0000)>>16;
4062
npq = (npq & 0xFFF0000)>>16;
4063
epq = (epq & 0xFFF0000)>>16;
4064
pubq = (pubq & 0xFFF0000)>>16;
4065
4066
RTW_PRINT_SEL(sel, "Tx: available page num: ");
4067
if ((hpq == 0xAEA) && (hpq == lpq) && (hpq == pubq))
4068
RTW_PRINT_SEL(sel, "N/A (reg val = 0xea)\n");
4069
else
4070
RTW_PRINT_SEL(sel, "HPQ: %d, LPQ: %d, NPQ: %d, EPQ: %d, PUBQ: %d\n"
4071
, hpq, lpq, npq, epq, pubq);
4072
}
4073
4074
void rtl8814a_read_wmmedca_reg(PADAPTER adapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params)
4075
{
4076
u8 vo_reg_params[4];
4077
u8 vi_reg_params[4];
4078
u8 be_reg_params[4];
4079
u8 bk_reg_params[4];
4080
4081
GetHwReg8814A(adapter, HW_VAR_AC_PARAM_VO, vo_reg_params);
4082
GetHwReg8814A(adapter, HW_VAR_AC_PARAM_VI, vi_reg_params);
4083
GetHwReg8814A(adapter, HW_VAR_AC_PARAM_BE, be_reg_params);
4084
GetHwReg8814A(adapter, HW_VAR_AC_PARAM_BK, bk_reg_params);
4085
4086
vo_params[0] = vo_reg_params[0];
4087
vo_params[1] = vo_reg_params[1] & 0x0F;
4088
vo_params[2] = (vo_reg_params[1] & 0xF0) >> 4;
4089
vo_params[3] = ((vo_reg_params[3] << 8) | (vo_reg_params[2])) * 32;
4090
4091
vi_params[0] = vi_reg_params[0];
4092
vi_params[1] = vi_reg_params[1] & 0x0F;
4093
vi_params[2] = (vi_reg_params[1] & 0xF0) >> 4;
4094
vi_params[3] = ((vi_reg_params[3] << 8) | (vi_reg_params[2])) * 32;
4095
4096
be_params[0] = be_reg_params[0];
4097
be_params[1] = be_reg_params[1] & 0x0F;
4098
be_params[2] = (be_reg_params[1] & 0xF0) >> 4;
4099
be_params[3] = ((be_reg_params[3] << 8) | (be_reg_params[2])) * 32;
4100
4101
bk_params[0] = bk_reg_params[0];
4102
bk_params[1] = bk_reg_params[1] & 0x0F;
4103
bk_params[2] = (bk_reg_params[1] & 0xF0) >> 4;
4104
bk_params[3] = ((bk_reg_params[3] << 8) | (bk_reg_params[2])) * 32;
4105
4106
vo_params[1] = (1 << vo_params[1]) - 1;
4107
vo_params[2] = (1 << vo_params[2]) - 1;
4108
vi_params[1] = (1 << vi_params[1]) - 1;
4109
vi_params[2] = (1 << vi_params[2]) - 1;
4110
be_params[1] = (1 << be_params[1]) - 1;
4111
be_params[2] = (1 << be_params[2]) - 1;
4112
bk_params[1] = (1 << bk_params[1]) - 1;
4113
bk_params[2] = (1 << bk_params[2]) - 1;
4114
}
4115
4116
void GetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval)
4117
{
4118
PHAL_DATA_TYPE pHalData;
4119
u8 val8;
4120
u16 val16;
4121
u32 val32;
4122
4123
4124
pHalData = GET_HAL_DATA(padapter);
4125
4126
switch (variable) {
4127
case HW_VAR_TXPAUSE:
4128
*pval = rtw_read8(padapter, REG_TXPAUSE);
4129
break;
4130
4131
case HW_VAR_BCN_VALID:
4132
#ifdef CONFIG_CONCURRENT_MODE
4133
if (padapter->hw_port == HW_PORT1) {
4134
/* BCN_VALID, BIT31 of REG_FIFOPAGE_CTRL_2_8814A, write 1 to clear */
4135
val8 = rtw_read8(padapter, REG_FIFOPAGE_CTRL_2_8814A + 3);
4136
*pval = (BIT(7) & val8) ? _TRUE : _FALSE;
4137
} else
4138
#endif /* CONFIG_CONCURRENT_MODE */
4139
{
4140
/* BCN_VALID, BIT15 of REG_FIFOPAGE_CTRL_2_8814A, write 1 to clear */
4141
val8 = rtw_read8(padapter, REG_FIFOPAGE_CTRL_2_8814A + 1);
4142
*pval = (BIT(7) & val8) ? _TRUE : _FALSE;
4143
}
4144
break;
4145
4146
case HW_VAR_AC_PARAM_VO:
4147
val32 = rtw_read32(padapter, REG_EDCA_VO_PARAM);
4148
pval[0] = val32 & 0xFF;
4149
pval[1] = (val32 >> 8) & 0xFF;
4150
pval[2] = (val32 >> 16) & 0xFF;
4151
pval[3] = (val32 >> 24) & 0x07;
4152
break;
4153
4154
case HW_VAR_AC_PARAM_VI:
4155
val32 = rtw_read32(padapter, REG_EDCA_VI_PARAM);
4156
pval[0] = val32 & 0xFF;
4157
pval[1] = (val32 >> 8) & 0xFF;
4158
pval[2] = (val32 >> 16) & 0xFF;
4159
pval[3] = (val32 >> 24) & 0x07;
4160
break;
4161
4162
case HW_VAR_AC_PARAM_BE:
4163
val32 = rtw_read32(padapter, REG_EDCA_BE_PARAM);
4164
pval[0] = val32 & 0xFF;
4165
pval[1] = (val32 >> 8) & 0xFF;
4166
pval[2] = (val32 >> 16) & 0xFF;
4167
pval[3] = (val32 >> 24) & 0x07;
4168
break;
4169
4170
case HW_VAR_AC_PARAM_BK:
4171
val32 = rtw_read32(padapter, REG_EDCA_BK_PARAM);
4172
pval[0] = val32 & 0xFF;
4173
pval[1] = (val32 >> 8) & 0xFF;
4174
pval[2] = (val32 >> 16) & 0xFF;
4175
pval[3] = (val32 >> 24) & 0x07;
4176
break;
4177
4178
case HW_VAR_EFUSE_BYTES: /* To get EFUE total used bytes, added by Roger, 2008.12.22. */
4179
*(u16 *)pval = pHalData->EfuseUsedBytes;
4180
break;
4181
4182
case HW_VAR_CHK_HI_QUEUE_EMPTY:
4183
val16 = rtw_read16(padapter, REG_TXPKT_EMPTY);
4184
*pval = (val16 & BIT(10)) ? _TRUE : _FALSE;
4185
break;
4186
case HW_VAR_CHK_MGQ_CPU_EMPTY:
4187
val16 = rtw_read16(padapter, REG_TXPKT_EMPTY);
4188
*pval = (val16 & BIT(8)) ? _TRUE : _FALSE;
4189
break;
4190
case HW_VAR_DUMP_MAC_QUEUE_INFO:
4191
dump_mac_qinfo_8814a(pval, padapter);
4192
break;
4193
4194
case HW_VAR_DUMP_MAC_TXFIFO:
4195
dump_mac_txfifo_8814a(pval, padapter);
4196
break;
4197
4198
default:
4199
GetHwReg(padapter, variable, pval);
4200
break;
4201
}
4202
4203
}
4204
4205
/*
4206
* Description:
4207
* Change default setting of specified variable.
4208
*/
4209
u8 SetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval)
4210
{
4211
PHAL_DATA_TYPE pHalData;
4212
u8 bResult;
4213
4214
4215
pHalData = GET_HAL_DATA(padapter);
4216
bResult = _SUCCESS;
4217
4218
switch (variable) {
4219
case HAL_DEF_EFUSE_BYTES:
4220
pHalData->EfuseUsedBytes = *((u16 *)pval);
4221
break;
4222
case HAL_DEF_EFUSE_USAGE:
4223
pHalData->EfuseUsedPercentage = *((u8 *)pval);
4224
break;
4225
default:
4226
bResult = SetHalDefVar(padapter, variable, pval);
4227
break;
4228
}
4229
4230
return bResult;
4231
}
4232
4233
/*
4234
* Description:
4235
* Query setting of specified variable.
4236
*/
4237
u8 GetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval)
4238
{
4239
PHAL_DATA_TYPE pHalData;
4240
u8 bResult;
4241
4242
4243
pHalData = GET_HAL_DATA(padapter);
4244
bResult = _SUCCESS;
4245
4246
switch (variable) {
4247
4248
4249
#ifdef CONFIG_ANTENNA_DIVERSITY
4250
case HAL_DEF_IS_SUPPORT_ANT_DIV:
4251
*((u8 *)pval) = (pHalData->AntDivCfg == 0) ? _FALSE : _TRUE;
4252
break;
4253
#endif /* CONFIG_ANTENNA_DIVERSITY */
4254
4255
case HAL_DEF_DRVINFO_SZ:
4256
*((u32 *)pval) = DRVINFO_SZ;
4257
break;
4258
4259
case HAL_DEF_MAX_RECVBUF_SZ:
4260
*((u32 *)pval) = MAX_RECVBUF_SZ;
4261
break;
4262
4263
case HAL_DEF_RX_PACKET_OFFSET:
4264
*((u32 *)pval) = RXDESC_SIZE + DRVINFO_SZ * 8;
4265
break;
4266
4267
case HW_VAR_MAX_RX_AMPDU_FACTOR:
4268
*((u32 *)pval) = MAX_AMPDU_FACTOR_64K;
4269
break;
4270
4271
case HW_VAR_BEST_AMPDU_DENSITY:
4272
*((u32 *)pval) = AMPDU_DENSITY_VALUE_4;
4273
break;
4274
4275
case HAL_DEF_TX_LDPC:
4276
*(u8 *)pval = _TRUE;
4277
break;
4278
4279
case HAL_DEF_RX_LDPC:
4280
*(u8 *)pval = _TRUE;
4281
break;
4282
4283
case HAL_DEF_RX_STBC:
4284
*(u8 *)pval = 1;
4285
break;
4286
4287
case HAL_DEF_EXPLICIT_BEAMFORMER:
4288
if (pHalData->rf_type != RF_1T2R && pHalData->rf_type != RF_1T1R)/*1T?R not support mer*/
4289
*((PBOOLEAN)pval) = _TRUE;
4290
else
4291
*((PBOOLEAN)pval) = _FALSE;
4292
break;
4293
case HAL_DEF_EXPLICIT_BEAMFORMEE:
4294
*((PBOOLEAN)pval) = _TRUE;
4295
break;
4296
4297
case HW_DEF_RA_INFO_DUMP:
4298
#if 0
4299
{
4300
u8 mac_id = *(u8 *)pval;
4301
u32 cmd ;
4302
u32 ra_info1, ra_info2;
4303
u32 rate_mask1, rate_mask2;
4304
u8 curr_tx_rate, curr_tx_sgi, hight_rate, lowest_rate;
4305
4306
RTW_INFO("============ RA status check Mac_id:%d ===================\n", mac_id);
4307
4308
cmd = 0x40000100 | mac_id;
4309
rtw_write32(padapter, REG_HMEBOX_E2_E3_8812, cmd);
4310
rtw_msleep_os(10);
4311
ra_info1 = rtw_read32(padapter, REG_RSVD5_8812);
4312
curr_tx_rate = ra_info1 & 0x7F;
4313
curr_tx_sgi = (ra_info1 >> 7) & 0x01;
4314
RTW_INFO("[ ra_info1:0x%08x ] =>cur_tx_rate= %s,cur_sgi:%d, PWRSTS = 0x%02x\n",
4315
ra_info1,
4316
HDATA_RATE(curr_tx_rate),
4317
curr_tx_sgi,
4318
(ra_info1 >> 8) & 0x07);
4319
4320
cmd = 0x40000400 | mac_id;
4321
rtw_write32(padapter, REG_HMEBOX_E2_E3_8812, cmd);
4322
rtw_msleep_os(10);
4323
ra_info1 = rtw_read32(padapter, REG_RSVD5_8812);
4324
ra_info2 = rtw_read32(padapter, REG_RSVD6_8812);
4325
rate_mask1 = rtw_read32(padapter, REG_RSVD7_8812);
4326
rate_mask2 = rtw_read32(padapter, REG_RSVD8_8812);
4327
hight_rate = ra_info2 & 0xFF;
4328
lowest_rate = (ra_info2 >> 8) & 0xFF;
4329
RTW_INFO("[ ra_info1:0x%08x ] =>RSSI=%d, BW_setting=0x%02x, DISRA=0x%02x, VHT_EN=0x%02x\n",
4330
ra_info1,
4331
ra_info1 & 0xFF,
4332
(ra_info1 >> 8) & 0xFF,
4333
(ra_info1 >> 16) & 0xFF,
4334
(ra_info1 >> 24) & 0xFF);
4335
4336
RTW_INFO("[ ra_info2:0x%08x ] =>hight_rate=%s, lowest_rate=%s, SGI=0x%02x, RateID=%d\n",
4337
ra_info2,
4338
HDATA_RATE(hight_rate),
4339
HDATA_RATE(lowest_rate),
4340
(ra_info2 >> 16) & 0xFF,
4341
(ra_info2 >> 24) & 0xFF);
4342
RTW_INFO("rate_mask2=0x%08x, rate_mask1=0x%08x\n", rate_mask2, rate_mask1);
4343
}
4344
#else /* 0 */
4345
RTW_INFO("%s,%d, 8814 need to fix\n", __FUNCTION__, __LINE__);
4346
#endif /* 0 */
4347
break;
4348
4349
case HAL_DEF_TX_PAGE_SIZE:
4350
*(u32 *)pval = PAGE_SIZE_128;
4351
break;
4352
4353
case HAL_DEF_TX_PAGE_BOUNDARY:
4354
if (!padapter->registrypriv.wifi_spec)
4355
*(u16 *)pval = TX_PAGE_BOUNDARY_8814A;
4356
else
4357
*(u16 *)pval = WMM_NORMAL_TX_PAGE_BOUNDARY_8814A;
4358
break;
4359
4360
case HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN:
4361
*(u16 *)pval = TX_PAGE_BOUNDARY_WOWLAN_8814A;
4362
break;
4363
case HAL_DEF_EFUSE_BYTES:
4364
*((u16 *)(pval)) = pHalData->EfuseUsedBytes;
4365
break;
4366
case HAL_DEF_EFUSE_USAGE:
4367
*((u32 *)(pval)) = (pHalData->EfuseUsedPercentage << 16) | (pHalData->EfuseUsedBytes);
4368
break;
4369
case HAL_DEF_RX_DMA_SZ_WOW:
4370
*((u32 *)pval) = RX_DMA_BOUNDARY_8814A + 1;
4371
break;
4372
case HAL_DEF_RX_DMA_SZ:
4373
*((u32 *)pval) = RX_DMA_BOUNDARY_8814A + 1;
4374
break;
4375
case HAL_DEF_RX_PAGE_SIZE:
4376
*((u32 *)pval) = 8;
4377
break;
4378
default:
4379
bResult = GetHalDefVar(padapter, variable, pval);
4380
break;
4381
}
4382
4383
return bResult;
4384
}
4385
4386
#ifdef CONFIG_BT_COEXIST
4387
void rtl8814a_combo_card_WifiOnlyHwInit(PADAPTER pdapter)
4388
{
4389
u8 u1Tmp;
4390
RTW_INFO("%s !\n", __FUNCTION__);
4391
if (IS_HARDWARE_TYPE_8812(pdapter)) {
4392
/* 0x790[5:0]=0x5 */
4393
u1Tmp = rtw_read8(pdapter, 0x790);
4394
u1Tmp = (u1Tmp & 0xb0) | 0x05 ;
4395
rtw_write8(pdapter, 0x790, u1Tmp);
4396
/* PTA parameter */
4397
/* pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, 0x0); */
4398
/* pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, 0xffffff); */
4399
/* pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, 0x55555555); */
4400
/* pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, 0x55555555); */
4401
rtw_write8(pdapter, 0x6cc, 0x0);
4402
rtw_write32(pdapter, 0x6c8, 0xffffff);
4403
rtw_write32(pdapter, 0x6c4, 0x55555555);
4404
rtw_write32(pdapter, 0x6c0, 0x55555555);
4405
4406
/* coex parameters */
4407
/* pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x3); */
4408
rtw_write8(pdapter, 0x778, 0x3);
4409
4410
/* enable counter statistics */
4411
/* pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); */
4412
rtw_write8(pdapter, 0x76e, 0xc);
4413
4414
/* enable PTA */
4415
/* pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x20); */
4416
rtw_write8(pdapter, 0x40, 0x20);
4417
4418
/* bt clock related */
4419
/* u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4); */
4420
/* u1Tmp |= BIT7; */
4421
/* pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4, u1Tmp); */
4422
u1Tmp = rtw_read8(pdapter, 0x4);
4423
u1Tmp |= BIT7;
4424
rtw_write8(pdapter, 0x4, u1Tmp);
4425
4426
/* bt clock related */
4427
/* u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x7); */
4428
/* u1Tmp |= BIT1; */
4429
/* pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x7, u1Tmp); */
4430
u1Tmp = rtw_read8(pdapter, 0x7);
4431
u1Tmp |= BIT1;
4432
rtw_write8(pdapter, 0x7, u1Tmp);
4433
}
4434
4435
4436
}
4437
#endif /* CONFIG_BT_COEXIST */
4438
4439
void rtl8814_set_hal_ops(struct hal_ops *pHalFunc)
4440
{
4441
pHalFunc->dm_init = &rtl8814_init_dm_priv;
4442
pHalFunc->dm_deinit = &rtl8814_deinit_dm_priv;
4443
4444
pHalFunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8814A;
4445
4446
pHalFunc->read_chip_version = read_chip_version_8814a;
4447
4448
pHalFunc->set_chnl_bw_handler = &PHY_SetSwChnlBWMode8814;
4449
4450
pHalFunc->set_tx_power_level_handler = &PHY_SetTxPowerLevel8814;
4451
pHalFunc->set_tx_power_index_handler = PHY_SetTxPowerIndex_8814A;
4452
pHalFunc->get_tx_power_index_handler = &PHY_GetTxPowerIndex8814A;
4453
4454
pHalFunc->hal_dm_watchdog = &rtl8814_HalDmWatchDog;
4455
4456
pHalFunc->run_thread = &rtl8814_start_thread;
4457
pHalFunc->cancel_thread = &rtl8814_stop_thread;
4458
4459
pHalFunc->read_bbreg = &PHY_QueryBBReg8814A;
4460
pHalFunc->write_bbreg = &PHY_SetBBReg8814A;
4461
pHalFunc->read_rfreg = &PHY_QueryRFReg8814A;
4462
pHalFunc->write_rfreg = &PHY_SetRFReg8814A;
4463
4464
pHalFunc->read_wmmedca_reg = &rtl8814a_read_wmmedca_reg;
4465
4466
/* Efuse related function */
4467
pHalFunc->EfusePowerSwitch = &rtl8814_EfusePowerSwitch;
4468
pHalFunc->ReadEFuse = &rtl8814_ReadEFuse;
4469
pHalFunc->EFUSEGetEfuseDefinition = &rtl8814_EFUSE_GetEfuseDefinition;
4470
pHalFunc->EfuseGetCurrentSize = &rtl8814_EfuseGetCurrentSize;
4471
pHalFunc->Efuse_PgPacketRead = &rtl8814_Efuse_PgPacketRead;
4472
pHalFunc->Efuse_PgPacketWrite = &rtl8814_Efuse_PgPacketWrite;
4473
pHalFunc->Efuse_WordEnableDataWrite = &rtl8814_Efuse_WordEnableDataWrite;
4474
4475
#ifdef DBG_CONFIG_ERROR_DETECT
4476
pHalFunc->sreset_init_value = &sreset_init_value;
4477
pHalFunc->sreset_reset_value = &sreset_reset_value;
4478
pHalFunc->silentreset = &sreset_reset;
4479
pHalFunc->sreset_xmit_status_check = &rtl8814_sreset_xmit_status_check;
4480
pHalFunc->sreset_linked_status_check = &rtl8814_sreset_linked_status_check;
4481
pHalFunc->sreset_get_wifi_status = &sreset_get_wifi_status;
4482
pHalFunc->sreset_inprogress = &sreset_inprogress;
4483
#endif /* DBG_CONFIG_ERROR_DETECT */
4484
4485
pHalFunc->GetHalODMVarHandler = GetHalODMVar;
4486
pHalFunc->SetHalODMVarHandler = SetHalODMVar;
4487
pHalFunc->hal_notch_filter = &hal_notch_filter_8814;
4488
4489
pHalFunc->c2h_handler = c2h_handler_8814a;
4490
pHalFunc->reqtxrpt = &rtl8814_req_txrpt_cmd;
4491
4492
pHalFunc->fill_h2c_cmd = &FillH2CCmd_8814;
4493
pHalFunc->fill_fake_txdesc = &rtl8814a_fill_fake_txdesc;
4494
pHalFunc->fw_dl = &FirmwareDownload8814A;
4495
pHalFunc->hal_get_tx_buff_rsvd_page_num = &GetTxBufferRsvdPageNum8814;
4496
}
4497
4498