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orangepi-xunlong
GitHub Repository: orangepi-xunlong/orangepi-build
Path: blob/next/external/packages/blobs/espressobin/DDR_TOPOLOGY_7.txt
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#
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# This file is the input for A3700 DDR porting tool,
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# each item is one parameter for DDR topology, which will be parsed by
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# DDR tool and generate DDR register list accordingly.
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# Supported Marvell boards:
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# DDR3 2CS : EspressoBIN (2GB)
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#
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#DDR3
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ddr_type=0
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#2CS
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ddr_cs_mask=3
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#DDR3_1600K
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ddr_speedbin_index=12
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#16BIT
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ddr_bus_width_index=2
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#8Gbits (1024MB)
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ddr_mem_size_index=4
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