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script3r
GitHub Repository: script3r/os161
 Path: blob/master/kern/arch/mips/include/tlb.h
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/*

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 * Copyright (c) 2000, 2001, 2002, 2003, 2004, 2005, 2008, 2009

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 *	The President and Fellows of Harvard College.

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 *

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 * Redistribution and use in source and binary forms, with or without

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 * modification, are permitted provided that the following conditions

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 * are met:

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 * 1. Redistributions of source code must retain the above copyright

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 *    notice, this list of conditions and the following disclaimer.

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 * 2. Redistributions in binary form must reproduce the above copyright

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 *    notice, this list of conditions and the following disclaimer in the

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 *    documentation and/or other materials provided with the distribution.

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 * 3. Neither the name of the University nor the names of its contributors

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 *    may be used to endorse or promote products derived from this software

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 *    without specific prior written permission.

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 *

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 * THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY AND CONTRIBUTORS ``AS IS'' AND

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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

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 * ARE DISCLAIMED.  IN NO EVENT SHALL THE UNIVERSITY OR CONTRIBUTORS BE LIABLE

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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY

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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF

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 * SUCH DAMAGE.

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 */

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#ifndef _MIPS_TLB_H_

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#define _MIPS_TLB_H_

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/*

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 * MIPS-specific TLB access functions.

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 *

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 *   tlb_random: write the TLB entry specified by ENTRYHI and ENTRYLO

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 *        into a "random" TLB slot chosen by the processor.

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 *

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 *        IMPORTANT NOTE: never write more than one TLB entry with the

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 *        same virtual page field.

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 *

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 *   tlb_write: same as tlb_random, but you choose the slot.

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 *

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 *   tlb_read: read a TLB entry out of the TLB into ENTRYHI and ENTRYLO.

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 *        INDEX specifies which one to get.

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 *

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 *   tlb_probe: look for an entry matching the virtual page in ENTRYHI.

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 *        Returns the index, or a negative number if no matching entry

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 *        was found. ENTRYLO is not actually used, but must be set; 0

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 *        should be passed.

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 *

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 *        IMPORTANT NOTE: An entry may be matching even if the valid bit 

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 *        is not set. To completely invalidate the TLB, load it with

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 *        translations for addresses in one of the unmapped address

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 *        ranges - these will never be matched.

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 */

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void tlb_random(uint32_t entryhi, uint32_t entrylo);

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void tlb_write(uint32_t entryhi, uint32_t entrylo, uint32_t index);

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void tlb_read(uint32_t *entryhi, uint32_t *entrylo, uint32_t index);

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int tlb_probe(uint32_t entryhi, uint32_t entrylo);

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void		tlb_unmap( vaddr_t );

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void		tlb_invalidate( int );

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void		tlb_clear(void);

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void		tlb_invalidate_coremap_entry( unsigned );

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int		tlb_get_free_slot(void);

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int		tlb_evict(void);

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void		tlb_shootdown_wait( void );

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/*

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 * TLB entry fields.

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 *

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 * Note that the MIPS has support for a 6-bit address space ID. In the

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 * interests of simplicity, we don't use it. The fields related to it

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 * (TLBLO_GLOBAL and TLBHI_PID) can be left always zero, as can the

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 * bits that aren't assigned a meaning.

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 *

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 * The TLBLO_DIRTY bit is actually a write privilege bit - it is not

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 * ever set by the processor. If you set it, writes are permitted. If

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 * you don't set it, you'll get a "TLB Modify" exception when a write

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 * is attempted.

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 *

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 * There is probably no reason in the course of CS161 to use TLBLO_NOCACHE.

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 */

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/* Fields in the high-order word */

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#define TLBHI_VPAGE   0xfffff000

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/*      TLBHI_PID     0x00000fc0 */

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/* Fields in the low-order word */

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#define TLBLO_PPAGE   0xfffff000

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#define TLBLO_NOCACHE 0x00000800

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#define TLBLO_DIRTY   0x00000400

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#define TLBLO_VALID   0x00000200

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/*      TLBLO_GLOBAL  0x00000100 */

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/*

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 * Values for completely invalid TLB entries. The TLB entry index should

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 * be passed to TLBHI_INVALID; this prevents loading the same invalid

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 * entry into multiple TLB slots.

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 */

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#define TLBHI_INVALID(entryno) ((0x80000+(entryno))<<12)

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#define TLBLO_INVALID()        (0)

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/*

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 * Number of TLB entries in the processor.

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 */

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#define NUM_TLB  64

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#endif /* _MIPS_TLB_H_ */

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