Path: blob/master/dep/riscv-disas/include/riscv-disas.h
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/*1* RISC-V Disassembler2*3* Copyright (c) 2016-2017 Michael Clark <[email protected]>4* Copyright (c) 2017-2018 SiFive, Inc.5*6* Permission is hereby granted, free of charge, to any person obtaining a copy7* of this software and associated documentation files (the "Software"), to deal8* in the Software without restriction, including without limitation the rights9* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell10* copies of the Software, and to permit persons to whom the Software is11* furnished to do so, subject to the following conditions:12*13* The above copyright notice and this permission notice shall be included in14* all copies or substantial portions of the Software.15*16* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR17* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,18* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL19* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER20* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,21* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN22* THE SOFTWARE.23*/2425#ifndef RISCV_DISASSEMBLER_H26#define RISCV_DISASSEMBLER_H2728#include <stdio.h>29#include <stdlib.h>30#include <stdint.h>31#include <stdbool.h>32#include <inttypes.h>33#include <string.h>3435/* types */3637typedef uint64_t rv_inst;38typedef uint16_t rv_opcode;3940/* enums */4142typedef enum {43rv32,44rv64,45rv12846} rv_isa;4748typedef enum {49rv_rm_rne = 0,50rv_rm_rtz = 1,51rv_rm_rdn = 2,52rv_rm_rup = 3,53rv_rm_rmm = 4,54rv_rm_dyn = 7,55} rv_rm;5657typedef enum {58rv_fence_i = 8,59rv_fence_o = 4,60rv_fence_r = 2,61rv_fence_w = 1,62} rv_fence;6364typedef enum {65rv_ireg_zero,66rv_ireg_ra,67rv_ireg_sp,68rv_ireg_gp,69rv_ireg_tp,70rv_ireg_t0,71rv_ireg_t1,72rv_ireg_t2,73rv_ireg_s0,74rv_ireg_s1,75rv_ireg_a0,76rv_ireg_a1,77rv_ireg_a2,78rv_ireg_a3,79rv_ireg_a4,80rv_ireg_a5,81rv_ireg_a6,82rv_ireg_a7,83rv_ireg_s2,84rv_ireg_s3,85rv_ireg_s4,86rv_ireg_s5,87rv_ireg_s6,88rv_ireg_s7,89rv_ireg_s8,90rv_ireg_s9,91rv_ireg_s10,92rv_ireg_s11,93rv_ireg_t3,94rv_ireg_t4,95rv_ireg_t5,96rv_ireg_t6,97} rv_ireg;9899typedef enum {100rvc_end,101rvc_rd_eq_ra,102rvc_rd_eq_x0,103rvc_rs1_eq_x0,104rvc_rs2_eq_x0,105rvc_rs2_eq_rs1,106rvc_rs1_eq_ra,107rvc_imm_eq_zero,108rvc_imm_eq_n1,109rvc_imm_eq_p1,110rvc_csr_eq_0x001,111rvc_csr_eq_0x002,112rvc_csr_eq_0x003,113rvc_csr_eq_0xc00,114rvc_csr_eq_0xc01,115rvc_csr_eq_0xc02,116rvc_csr_eq_0xc80,117rvc_csr_eq_0xc81,118rvc_csr_eq_0xc82,119} rvc_constraint;120121typedef enum {122rv_codec_illegal,123rv_codec_none,124rv_codec_u,125rv_codec_uj,126rv_codec_i,127rv_codec_i_sh5,128rv_codec_i_sh6,129rv_codec_i_sh7,130rv_codec_i_csr,131rv_codec_s,132rv_codec_sb,133rv_codec_r,134rv_codec_r_m,135rv_codec_r4_m,136rv_codec_r_a,137rv_codec_r_l,138rv_codec_r_f,139rv_codec_cb,140rv_codec_cb_imm,141rv_codec_cb_sh5,142rv_codec_cb_sh6,143rv_codec_ci,144rv_codec_ci_sh5,145rv_codec_ci_sh6,146rv_codec_ci_16sp,147rv_codec_ci_lwsp,148rv_codec_ci_ldsp,149rv_codec_ci_lqsp,150rv_codec_ci_li,151rv_codec_ci_lui,152rv_codec_ci_none,153rv_codec_ciw_4spn,154rv_codec_cj,155rv_codec_cj_jal,156rv_codec_cl_lw,157rv_codec_cl_ld,158rv_codec_cl_lq,159rv_codec_cr,160rv_codec_cr_mv,161rv_codec_cr_jalr,162rv_codec_cr_jr,163rv_codec_cs,164rv_codec_cs_sw,165rv_codec_cs_sd,166rv_codec_cs_sq,167rv_codec_css_swsp,168rv_codec_css_sdsp,169rv_codec_css_sqsp,170} rv_codec;171172typedef enum {173rv_op_illegal,174rv_op_lui,175rv_op_auipc,176rv_op_jal,177rv_op_jalr,178rv_op_beq,179rv_op_bne,180rv_op_blt,181rv_op_bge,182rv_op_bltu,183rv_op_bgeu,184rv_op_lb,185rv_op_lh,186rv_op_lw,187rv_op_lbu,188rv_op_lhu,189rv_op_sb,190rv_op_sh,191rv_op_sw,192rv_op_addi,193rv_op_slti,194rv_op_sltiu,195rv_op_xori,196rv_op_ori,197rv_op_andi,198rv_op_slli,199rv_op_srli,200rv_op_srai,201rv_op_add,202rv_op_sub,203rv_op_sll,204rv_op_slt,205rv_op_sltu,206rv_op_xor,207rv_op_srl,208rv_op_sra,209rv_op_or,210rv_op_and,211rv_op_fence,212rv_op_fence_i,213rv_op_lwu,214rv_op_ld,215rv_op_sd,216rv_op_addiw,217rv_op_slliw,218rv_op_srliw,219rv_op_sraiw,220rv_op_addw,221rv_op_subw,222rv_op_sllw,223rv_op_srlw,224rv_op_sraw,225rv_op_ldu,226rv_op_lq,227rv_op_sq,228rv_op_addid,229rv_op_sllid,230rv_op_srlid,231rv_op_sraid,232rv_op_addd,233rv_op_subd,234rv_op_slld,235rv_op_srld,236rv_op_srad,237rv_op_mul,238rv_op_mulh,239rv_op_mulhsu,240rv_op_mulhu,241rv_op_div,242rv_op_divu,243rv_op_rem,244rv_op_remu,245rv_op_mulw,246rv_op_divw,247rv_op_divuw,248rv_op_remw,249rv_op_remuw,250rv_op_muld,251rv_op_divd,252rv_op_divud,253rv_op_remd,254rv_op_remud,255rv_op_lr_w,256rv_op_sc_w,257rv_op_amoswap_w,258rv_op_amoadd_w,259rv_op_amoxor_w,260rv_op_amoor_w,261rv_op_amoand_w,262rv_op_amomin_w,263rv_op_amomax_w,264rv_op_amominu_w,265rv_op_amomaxu_w,266rv_op_lr_d,267rv_op_sc_d,268rv_op_amoswap_d,269rv_op_amoadd_d,270rv_op_amoxor_d,271rv_op_amoor_d,272rv_op_amoand_d,273rv_op_amomin_d,274rv_op_amomax_d,275rv_op_amominu_d,276rv_op_amomaxu_d,277rv_op_lr_q,278rv_op_sc_q,279rv_op_amoswap_q,280rv_op_amoadd_q,281rv_op_amoxor_q,282rv_op_amoor_q,283rv_op_amoand_q,284rv_op_amomin_q,285rv_op_amomax_q,286rv_op_amominu_q,287rv_op_amomaxu_q,288rv_op_ecall,289rv_op_ebreak,290rv_op_uret,291rv_op_sret,292rv_op_hret,293rv_op_mret,294rv_op_dret,295rv_op_sfence_vm,296rv_op_sfence_vma,297rv_op_wfi,298rv_op_csrrw,299rv_op_csrrs,300rv_op_csrrc,301rv_op_csrrwi,302rv_op_csrrsi,303rv_op_csrrci,304rv_op_flw,305rv_op_fsw,306rv_op_fmadd_s,307rv_op_fmsub_s,308rv_op_fnmsub_s,309rv_op_fnmadd_s,310rv_op_fadd_s,311rv_op_fsub_s,312rv_op_fmul_s,313rv_op_fdiv_s,314rv_op_fsgnj_s,315rv_op_fsgnjn_s,316rv_op_fsgnjx_s,317rv_op_fmin_s,318rv_op_fmax_s,319rv_op_fsqrt_s,320rv_op_fle_s,321rv_op_flt_s,322rv_op_feq_s,323rv_op_fcvt_w_s,324rv_op_fcvt_wu_s,325rv_op_fcvt_s_w,326rv_op_fcvt_s_wu,327rv_op_fmv_x_s,328rv_op_fclass_s,329rv_op_fmv_s_x,330rv_op_fcvt_l_s,331rv_op_fcvt_lu_s,332rv_op_fcvt_s_l,333rv_op_fcvt_s_lu,334rv_op_fld,335rv_op_fsd,336rv_op_fmadd_d,337rv_op_fmsub_d,338rv_op_fnmsub_d,339rv_op_fnmadd_d,340rv_op_fadd_d,341rv_op_fsub_d,342rv_op_fmul_d,343rv_op_fdiv_d,344rv_op_fsgnj_d,345rv_op_fsgnjn_d,346rv_op_fsgnjx_d,347rv_op_fmin_d,348rv_op_fmax_d,349rv_op_fcvt_s_d,350rv_op_fcvt_d_s,351rv_op_fsqrt_d,352rv_op_fle_d,353rv_op_flt_d,354rv_op_feq_d,355rv_op_fcvt_w_d,356rv_op_fcvt_wu_d,357rv_op_fcvt_d_w,358rv_op_fcvt_d_wu,359rv_op_fclass_d,360rv_op_fcvt_l_d,361rv_op_fcvt_lu_d,362rv_op_fmv_x_d,363rv_op_fcvt_d_l,364rv_op_fcvt_d_lu,365rv_op_fmv_d_x,366rv_op_flq,367rv_op_fsq,368rv_op_fmadd_q,369rv_op_fmsub_q,370rv_op_fnmsub_q,371rv_op_fnmadd_q,372rv_op_fadd_q,373rv_op_fsub_q,374rv_op_fmul_q,375rv_op_fdiv_q,376rv_op_fsgnj_q,377rv_op_fsgnjn_q,378rv_op_fsgnjx_q,379rv_op_fmin_q,380rv_op_fmax_q,381rv_op_fcvt_s_q,382rv_op_fcvt_q_s,383rv_op_fcvt_d_q,384rv_op_fcvt_q_d,385rv_op_fsqrt_q,386rv_op_fle_q,387rv_op_flt_q,388rv_op_feq_q,389rv_op_fcvt_w_q,390rv_op_fcvt_wu_q,391rv_op_fcvt_q_w,392rv_op_fcvt_q_wu,393rv_op_fclass_q,394rv_op_fcvt_l_q,395rv_op_fcvt_lu_q,396rv_op_fcvt_q_l,397rv_op_fcvt_q_lu,398rv_op_fmv_x_q,399rv_op_fmv_q_x,400rv_op_c_addi4spn,401rv_op_c_fld,402rv_op_c_lw,403rv_op_c_flw,404rv_op_c_fsd,405rv_op_c_sw,406rv_op_c_fsw,407rv_op_c_nop,408rv_op_c_addi,409rv_op_c_jal,410rv_op_c_li,411rv_op_c_addi16sp,412rv_op_c_lui,413rv_op_c_srli,414rv_op_c_srai,415rv_op_c_andi,416rv_op_c_sub,417rv_op_c_xor,418rv_op_c_or,419rv_op_c_and,420rv_op_c_subw,421rv_op_c_addw,422rv_op_c_j,423rv_op_c_beqz,424rv_op_c_bnez,425rv_op_c_slli,426rv_op_c_fldsp,427rv_op_c_lwsp,428rv_op_c_flwsp,429rv_op_c_jr,430rv_op_c_mv,431rv_op_c_ebreak,432rv_op_c_jalr,433rv_op_c_add,434rv_op_c_fsdsp,435rv_op_c_swsp,436rv_op_c_fswsp,437rv_op_c_ld,438rv_op_c_sd,439rv_op_c_addiw,440rv_op_c_ldsp,441rv_op_c_sdsp,442rv_op_c_lq,443rv_op_c_sq,444rv_op_c_lqsp,445rv_op_c_sqsp,446rv_op_nop,447rv_op_mv,448rv_op_not,449rv_op_neg,450rv_op_negw,451rv_op_sext_w,452rv_op_seqz,453rv_op_snez,454rv_op_sltz,455rv_op_sgtz,456rv_op_fmv_s,457rv_op_fabs_s,458rv_op_fneg_s,459rv_op_fmv_d,460rv_op_fabs_d,461rv_op_fneg_d,462rv_op_fmv_q,463rv_op_fabs_q,464rv_op_fneg_q,465rv_op_beqz,466rv_op_bnez,467rv_op_blez,468rv_op_bgez,469rv_op_bltz,470rv_op_bgtz,471rv_op_ble,472rv_op_bleu,473rv_op_bgt,474rv_op_bgtu,475rv_op_j,476rv_op_ret,477rv_op_jr,478rv_op_rdcycle,479rv_op_rdtime,480rv_op_rdinstret,481rv_op_rdcycleh,482rv_op_rdtimeh,483rv_op_rdinstreth,484rv_op_frcsr,485rv_op_frrm,486rv_op_frflags,487rv_op_fscsr,488rv_op_fsrm,489rv_op_fsflags,490rv_op_fsrmi,491rv_op_fsflagsi,492} rv_op;493494/* structures */495496typedef struct {497uint64_t pc;498uint64_t inst;499int32_t imm;500uint16_t op;501uint8_t codec;502uint8_t rd;503uint8_t rs1;504uint8_t rs2;505uint8_t rs3;506uint8_t rm;507uint8_t pred;508uint8_t succ;509uint8_t aq;510uint8_t rl;511} rv_decode;512513/* functions */514515size_t inst_length(rv_inst inst);516void inst_fetch(const uint8_t *data, rv_inst *instp, size_t *length);517void disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst);518519#endif520521522