Path: blob/master/dep/riscv-disas/src/riscv-disas.c
4253 views
/*1* RISC-V Disassembler2*3* Copyright (c) 2016-2017 Michael Clark <[email protected]>4* Copyright (c) 2017-2018 SiFive, Inc.5*6* Permission is hereby granted, free of charge, to any person obtaining a copy7* of this software and associated documentation files (the "Software"), to deal8* in the Software without restriction, including without limitation the rights9* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell10* copies of the Software, and to permit persons to whom the Software is11* furnished to do so, subject to the following conditions:12*13* The above copyright notice and this permission notice shall be included in14* all copies or substantial portions of the Software.15*16* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR17* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,18* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL19* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER20* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,21* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN22* THE SOFTWARE.23*/2425#include "riscv-disas.h"2627typedef struct {28const int op;29const rvc_constraint *constraints;30} rv_comp_data;3132enum {33rvcd_imm_nz = 0x1,34rvcd_imm_nz_hint = 0x235};3637typedef struct {38const char * const name;39const rv_codec codec;40const char * const format;41const rv_comp_data *pseudo;42const short decomp_rv32;43const short decomp_rv64;44const short decomp_rv128;45const short decomp_data;46} rv_opcode_data;4748/* register names */4950static const char rv_ireg_name_sym[32][5] = {51"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",52"s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",53"a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",54"s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",55};5657static const char rv_freg_name_sym[32][5] = {58"ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",59"fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",60"fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",61"fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11",62};6364/* instruction formats */6566static const char rv_fmt_none[] = "O\t";67static const char rv_fmt_rs1[] = "O\t1";68static const char rv_fmt_offset[] = "O\to";69static const char rv_fmt_pred_succ[] = "O\tp,s";70static const char rv_fmt_rs1_rs2[] = "O\t1,2";71static const char rv_fmt_rd_imm[] = "O\t0,i";72static const char rv_fmt_rd_offset[] = "O\t0,o";73static const char rv_fmt_rd_rs1_rs2[] = "O\t0,1,2";74static const char rv_fmt_frd_rs1[] = "O\t3,1";75static const char rv_fmt_rd_frs1[] = "O\t0,4";76static const char rv_fmt_rd_frs1_frs2[] = "O\t0,4,5";77static const char rv_fmt_frd_frs1_frs2[] = "O\t3,4,5";78static const char rv_fmt_rm_frd_frs1[] = "O\tr,3,4";79static const char rv_fmt_rm_frd_rs1[] = "O\tr,3,1";80static const char rv_fmt_rm_rd_frs1[] = "O\tr,0,4";81static const char rv_fmt_rm_frd_frs1_frs2[] = "O\tr,3,4,5";82static const char rv_fmt_rm_frd_frs1_frs2_frs3[] = "O\tr,3,4,5,6";83static const char rv_fmt_rd_rs1_imm[] = "O\t0,1,i";84static const char rv_fmt_rd_rs1_offset[] = "O\t0,1,i";85static const char rv_fmt_rd_offset_rs1[] = "O\t0,i(1)";86static const char rv_fmt_frd_offset_rs1[] = "O\t3,i(1)";87static const char rv_fmt_rd_csr_rs1[] = "O\t0,c,1";88static const char rv_fmt_rd_csr_zimm[] = "O\t0,c,7";89static const char rv_fmt_rs2_offset_rs1[] = "O\t2,i(1)";90static const char rv_fmt_frs2_offset_rs1[] = "O\t5,i(1)";91static const char rv_fmt_rs1_rs2_offset[] = "O\t1,2,o";92static const char rv_fmt_rs2_rs1_offset[] = "O\t2,1,o";93static const char rv_fmt_aqrl_rd_rs2_rs1[] = "OAR\t0,2,(1)";94static const char rv_fmt_aqrl_rd_rs1[] = "OAR\t0,(1)";95static const char rv_fmt_rd[] = "O\t0";96static const char rv_fmt_rd_zimm[] = "O\t0,7";97static const char rv_fmt_rd_rs1[] = "O\t0,1";98static const char rv_fmt_rd_rs2[] = "O\t0,2";99static const char rv_fmt_rs1_offset[] = "O\t1,o";100static const char rv_fmt_rs2_offset[] = "O\t2,o";101102/* pseudo-instruction constraints */103104static const rvc_constraint rvcc_last[] = { rvc_end };105static const rvc_constraint rvcc_imm_eq_zero[] = { rvc_imm_eq_zero, rvc_end };106static const rvc_constraint rvcc_imm_eq_n1[] = { rvc_imm_eq_n1, rvc_end };107static const rvc_constraint rvcc_imm_eq_p1[] = { rvc_imm_eq_p1, rvc_end };108static const rvc_constraint rvcc_rs1_eq_x0[] = { rvc_rs1_eq_x0, rvc_end };109static const rvc_constraint rvcc_rs2_eq_x0[] = { rvc_rs2_eq_x0, rvc_end };110static const rvc_constraint rvcc_rs2_eq_rs1[] = { rvc_rs2_eq_rs1, rvc_end };111static const rvc_constraint rvcc_jal_j[] = { rvc_rd_eq_x0, rvc_end };112static const rvc_constraint rvcc_jal_jal[] = { rvc_rd_eq_ra, rvc_end };113static const rvc_constraint rvcc_jalr_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, rvc_end };114static const rvc_constraint rvcc_jalr_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, rvc_end };115static const rvc_constraint rvcc_jalr_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, rvc_end };116static const rvc_constraint rvcc_addi_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, rvc_imm_eq_zero, rvc_end };117static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, rvc_end };118static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, rvc_end };119static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end };120static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end };121static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end };122static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc82, rvc_end };123static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end };124static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end };125static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end };126static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end };127static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end };128static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end };129static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end };130static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end };131132/* pseudo-instruction metadata */133134static const rv_comp_data rvcp_jal[] = {135{ rv_op_j, rvcc_jal_j },136{ rv_op_jal, rvcc_jal_jal },137{ rv_op_illegal, NULL }138};139140static const rv_comp_data rvcp_jalr[] = {141{ rv_op_ret, rvcc_jalr_ret },142{ rv_op_jr, rvcc_jalr_jr },143{ rv_op_jalr, rvcc_jalr_jalr },144{ rv_op_illegal, NULL }145};146147static const rv_comp_data rvcp_beq[] = {148{ rv_op_beqz, rvcc_rs2_eq_x0 },149{ rv_op_illegal, NULL }150};151152static const rv_comp_data rvcp_bne[] = {153{ rv_op_bnez, rvcc_rs2_eq_x0 },154{ rv_op_illegal, NULL }155};156157static const rv_comp_data rvcp_blt[] = {158{ rv_op_bltz, rvcc_rs2_eq_x0 },159{ rv_op_bgtz, rvcc_rs1_eq_x0 },160{ rv_op_bgt, rvcc_last },161{ rv_op_illegal, NULL }162};163164static const rv_comp_data rvcp_bge[] = {165{ rv_op_blez, rvcc_rs1_eq_x0 },166{ rv_op_bgez, rvcc_rs2_eq_x0 },167{ rv_op_ble, rvcc_last },168{ rv_op_illegal, NULL }169};170171static const rv_comp_data rvcp_bltu[] = {172{ rv_op_bgtu, rvcc_last },173{ rv_op_illegal, NULL }174};175176static const rv_comp_data rvcp_bgeu[] = {177{ rv_op_bleu, rvcc_last },178{ rv_op_illegal, NULL }179};180181static const rv_comp_data rvcp_addi[] = {182{ rv_op_nop, rvcc_addi_nop },183{ rv_op_mv, rvcc_imm_eq_zero },184{ rv_op_illegal, NULL }185};186187static const rv_comp_data rvcp_sltiu[] = {188{ rv_op_seqz, rvcc_imm_eq_p1 },189{ rv_op_illegal, NULL }190};191192static const rv_comp_data rvcp_xori[] = {193{ rv_op_not, rvcc_imm_eq_n1 },194{ rv_op_illegal, NULL }195};196197static const rv_comp_data rvcp_sub[] = {198{ rv_op_neg, rvcc_rs1_eq_x0 },199{ rv_op_illegal, NULL }200};201202static const rv_comp_data rvcp_slt[] = {203{ rv_op_sltz, rvcc_rs2_eq_x0 },204{ rv_op_sgtz, rvcc_rs1_eq_x0 },205{ rv_op_illegal, NULL }206};207208static const rv_comp_data rvcp_sltu[] = {209{ rv_op_snez, rvcc_rs1_eq_x0 },210{ rv_op_illegal, NULL }211};212213static const rv_comp_data rvcp_addiw[] = {214{ rv_op_sext_w, rvcc_imm_eq_zero },215{ rv_op_illegal, NULL }216};217218static const rv_comp_data rvcp_subw[] = {219{ rv_op_negw, rvcc_rs1_eq_x0 },220{ rv_op_illegal, NULL }221};222223static const rv_comp_data rvcp_csrrw[] = {224{ rv_op_fscsr, rvcc_fscsr },225{ rv_op_fsrm, rvcc_fsrm },226{ rv_op_fsflags, rvcc_fsflags },227{ rv_op_illegal, NULL }228};229230static const rv_comp_data rvcp_csrrs[] = {231{ rv_op_rdcycle, rvcc_rdcycle },232{ rv_op_rdtime, rvcc_rdtime },233{ rv_op_rdinstret, rvcc_rdinstret },234{ rv_op_rdcycleh, rvcc_rdcycleh },235{ rv_op_rdtimeh, rvcc_rdtimeh },236{ rv_op_rdinstreth, rvcc_rdinstreth },237{ rv_op_frcsr, rvcc_frcsr },238{ rv_op_frrm, rvcc_frrm },239{ rv_op_frflags, rvcc_frflags },240{ rv_op_illegal, NULL }241};242243static const rv_comp_data rvcp_csrrwi[] = {244{ rv_op_fsrmi, rvcc_fsrmi },245{ rv_op_fsflagsi, rvcc_fsflagsi },246{ rv_op_illegal, NULL }247};248249static const rv_comp_data rvcp_fsgnj_s[] = {250{ rv_op_fmv_s, rvcc_rs2_eq_rs1 },251{ rv_op_illegal, NULL }252};253254static const rv_comp_data rvcp_fsgnjn_s[] = {255{ rv_op_fneg_s, rvcc_rs2_eq_rs1 },256{ rv_op_illegal, NULL }257};258259static const rv_comp_data rvcp_fsgnjx_s[] = {260{ rv_op_fabs_s, rvcc_rs2_eq_rs1 },261{ rv_op_illegal, NULL }262};263264static const rv_comp_data rvcp_fsgnj_d[] = {265{ rv_op_fmv_d, rvcc_rs2_eq_rs1 },266{ rv_op_illegal, NULL }267};268269static const rv_comp_data rvcp_fsgnjn_d[] = {270{ rv_op_fneg_d, rvcc_rs2_eq_rs1 },271{ rv_op_illegal, NULL }272};273274static const rv_comp_data rvcp_fsgnjx_d[] = {275{ rv_op_fabs_d, rvcc_rs2_eq_rs1 },276{ rv_op_illegal, NULL }277};278279static const rv_comp_data rvcp_fsgnj_q[] = {280{ rv_op_fmv_q, rvcc_rs2_eq_rs1 },281{ rv_op_illegal, NULL }282};283284static const rv_comp_data rvcp_fsgnjn_q[] = {285{ rv_op_fneg_q, rvcc_rs2_eq_rs1 },286{ rv_op_illegal, NULL }287};288289static const rv_comp_data rvcp_fsgnjx_q[] = {290{ rv_op_fabs_q, rvcc_rs2_eq_rs1 },291{ rv_op_illegal, NULL }292};293294/* instruction metadata */295296const rv_opcode_data opcode_data[] = {297{ "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },298{ "lui", rv_codec_u, rv_fmt_rd_imm, NULL, 0, 0, 0 },299{ "auipc", rv_codec_u, rv_fmt_rd_offset, NULL, 0, 0, 0 },300{ "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 },301{ "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 },302{ "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 },303{ "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 },304{ "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 },305{ "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 },306{ "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 },307{ "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 },308{ "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },309{ "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },310{ "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },311{ "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },312{ "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },313{ "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },314{ "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },315{ "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },316{ "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 },317{ "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },318{ "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 },319{ "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 },320{ "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },321{ "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },322{ "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },323{ "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },324{ "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },325{ "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },326{ "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 },327{ "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },328{ "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 },329{ "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 },330{ "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },331{ "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },332{ "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },333{ "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },334{ "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },335{ "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 },336{ "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },337{ "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },338{ "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },339{ "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },340{ "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 },341{ "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },342{ "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },343{ "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },344{ "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },345{ "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 },346{ "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },347{ "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },348{ "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },349{ "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },350{ "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },351{ "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },352{ "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },353{ "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },354{ "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },355{ "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },356{ "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },357{ "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },358{ "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },359{ "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },360{ "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },361{ "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },362{ "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },363{ "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },364{ "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },365{ "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },366{ "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },367{ "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },368{ "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },369{ "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },370{ "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },371{ "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },372{ "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },373{ "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },374{ "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },375{ "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },376{ "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },377{ "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },378{ "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },379{ "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },380{ "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },381{ "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },382{ "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },383{ "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },384{ "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },385{ "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },386{ "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },387{ "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },388{ "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },389{ "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },390{ "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },391{ "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },392{ "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },393{ "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },394{ "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },395{ "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },396{ "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },397{ "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },398{ "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },399{ "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },400{ "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },401{ "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },402{ "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },403{ "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },404{ "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },405{ "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },406{ "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },407{ "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },408{ "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },409{ "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },410{ "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },411{ "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },412{ "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },413{ "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },414{ "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },415{ "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },416{ "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },417{ "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },418{ "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },419{ "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },420{ "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 },421{ "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },422{ "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 },423{ "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 },424{ "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 },425{ "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 },426{ "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },427{ "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },428{ "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },429{ "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },430{ "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },431{ "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },432{ "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },433{ "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },434{ "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },435{ "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },436{ "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },437{ "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },438{ "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 },439{ "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 },440{ "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 },441{ "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },442{ "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },443{ "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },444{ "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },445{ "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },446{ "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },447{ "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },448{ "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },449{ "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },450{ "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },451{ "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },452{ "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },453{ "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },454{ "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },455{ "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },456{ "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },457{ "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },458{ "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },459{ "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },460{ "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },461{ "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },462{ "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },463{ "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },464{ "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },465{ "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },466{ "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },467{ "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },468{ "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 },469{ "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 },470{ "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 },471{ "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },472{ "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },473{ "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },474{ "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },475{ "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },476{ "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },477{ "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },478{ "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },479{ "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },480{ "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },481{ "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },482{ "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },483{ "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },484{ "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },485{ "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },486{ "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },487{ "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },488{ "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },489{ "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },490{ "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },491{ "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },492{ "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },493{ "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },494{ "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },495{ "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },496{ "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },497{ "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },498{ "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },499{ "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },500{ "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 },501{ "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 },502{ "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 },503{ "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },504{ "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },505{ "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },506{ "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },507{ "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },508{ "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },509{ "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },510{ "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },511{ "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },512{ "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },513{ "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },514{ "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },515{ "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },516{ "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },517{ "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },518{ "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },519{ "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },520{ "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },521{ "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },522{ "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },523{ "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },524{ "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi, rvcd_imm_nz },525{ "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, 0 },526{ "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },527{ "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },528{ "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, 0 },529{ "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },530{ "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },531{ "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, rv_op_addi },532{ "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi, rvcd_imm_nz_hint },533{ "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 },534{ "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },535{ "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi, rvcd_imm_nz },536{ "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui, rv_op_lui, rvcd_imm_nz },537{ "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, rv_op_srli, rv_op_srli, rvcd_imm_nz },538{ "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, rv_op_srai, rv_op_srai, rvcd_imm_nz },539{ "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, rv_op_andi, rv_op_andi, rvcd_imm_nz },540{ "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub },541{ "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor },542{ "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or },543{ "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, rv_op_and },544{ "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, rv_op_subw },545{ "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, rv_op_addw },546{ "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, rv_op_jal },547{ "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, rv_op_beq },548{ "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, rv_op_bne },549{ "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, rv_op_slli, rv_op_slli, rvcd_imm_nz },550{ "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, rv_op_fld },551{ "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },552{ "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },553{ "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },554{ "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, rv_op_addi },555{ "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, rv_op_ebreak, rv_op_ebreak },556{ "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },557{ "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, rv_op_add },558{ "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, rv_op_fsd },559{ "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },560{ "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },561{ "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },562{ "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },563{ "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, rv_op_addiw },564{ "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },565{ "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },566{ "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },567{ "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },568{ "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },569{ "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },570{ "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },571{ "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },572{ "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },573{ "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },574{ "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },575{ "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },576{ "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },577{ "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },578{ "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },579{ "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },580{ "fmv.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },581{ "fabs.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },582{ "fneg.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },583{ "fmv.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },584{ "fabs.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },585{ "fneg.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },586{ "fmv.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },587{ "fabs.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },588{ "fneg.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },589{ "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },590{ "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },591{ "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },592{ "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },593{ "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },594{ "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },595{ "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },596{ "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },597{ "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },598{ "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },599{ "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 },600{ "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },601{ "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 },602{ "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },603{ "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },604{ "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },605{ "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },606{ "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },607{ "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },608{ "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },609{ "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },610{ "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },611{ "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },612{ "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },613{ "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },614{ "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },615{ "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },616};617618/* CSR names */619620static const char *csr_name(int csrno)621{622switch (csrno) {623case 0x0000: return "ustatus";624case 0x0001: return "fflags";625case 0x0002: return "frm";626case 0x0003: return "fcsr";627case 0x0004: return "uie";628case 0x0005: return "utvec";629case 0x0007: return "utvt";630case 0x0008: return "vstart";631case 0x0009: return "vxsat";632case 0x000a: return "vxrm";633case 0x000f: return "vcsr";634case 0x0040: return "uscratch";635case 0x0041: return "uepc";636case 0x0042: return "ucause";637case 0x0043: return "utval";638case 0x0044: return "uip";639case 0x0045: return "unxti";640case 0x0046: return "uintstatus";641case 0x0048: return "uscratchcsw";642case 0x0049: return "uscratchcswl";643case 0x0100: return "sstatus";644case 0x0102: return "sedeleg";645case 0x0103: return "sideleg";646case 0x0104: return "sie";647case 0x0105: return "stvec";648case 0x0106: return "scounteren";649case 0x0107: return "stvt";650case 0x0140: return "sscratch";651case 0x0141: return "sepc";652case 0x0142: return "scause";653case 0x0143: return "stval";654case 0x0144: return "sip";655case 0x0145: return "snxti";656case 0x0146: return "sintstatus";657case 0x0148: return "sscratchcsw";658case 0x0149: return "sscratchcswl";659case 0x0180: return "satp";660case 0x0200: return "vsstatus";661case 0x0204: return "vsie";662case 0x0205: return "vstvec";663case 0x0240: return "vsscratch";664case 0x0241: return "vsepc";665case 0x0242: return "vscause";666case 0x0243: return "vstval";667case 0x0244: return "vsip";668case 0x0280: return "vsatp";669case 0x0300: return "mstatus";670case 0x0301: return "misa";671case 0x0302: return "medeleg";672case 0x0303: return "mideleg";673case 0x0304: return "mie";674case 0x0305: return "mtvec";675case 0x0306: return "mcounteren";676case 0x0307: return "mtvt";677case 0x0310: return "mstatush";678case 0x0320: return "mcountinhibit";679case 0x0323: return "mhpmevent3";680case 0x0324: return "mhpmevent4";681case 0x0325: return "mhpmevent5";682case 0x0326: return "mhpmevent6";683case 0x0327: return "mhpmevent7";684case 0x0328: return "mhpmevent8";685case 0x0329: return "mhpmevent9";686case 0x032a: return "mhpmevent10";687case 0x032b: return "mhpmevent11";688case 0x032c: return "mhpmevent12";689case 0x032d: return "mhpmevent13";690case 0x032e: return "mhpmevent14";691case 0x032f: return "mhpmevent15";692case 0x0330: return "mhpmevent16";693case 0x0331: return "mhpmevent17";694case 0x0332: return "mhpmevent18";695case 0x0333: return "mhpmevent19";696case 0x0334: return "mhpmevent20";697case 0x0335: return "mhpmevent21";698case 0x0336: return "mhpmevent22";699case 0x0337: return "mhpmevent23";700case 0x0338: return "mhpmevent24";701case 0x0339: return "mhpmevent25";702case 0x033a: return "mhpmevent26";703case 0x033b: return "mhpmevent27";704case 0x033c: return "mhpmevent28";705case 0x033d: return "mhpmevent29";706case 0x033e: return "mhpmevent30";707case 0x033f: return "mhpmevent31";708case 0x0340: return "mscratch";709case 0x0341: return "mepc";710case 0x0342: return "mcause";711case 0x0343: return "mtval";712case 0x0344: return "mip";713case 0x0345: return "mnxti";714case 0x0346: return "mintstatus";715case 0x0348: return "mscratchcsw";716case 0x0349: return "mscratchcswl";717case 0x034a: return "mtinst";718case 0x034b: return "mtval2";719case 0x03a0: return "pmpcfg0";720case 0x03a1: return "pmpcfg1";721case 0x03a2: return "pmpcfg2";722case 0x03a3: return "pmpcfg3";723case 0x03b0: return "pmpaddr0";724case 0x03b1: return "pmpaddr1";725case 0x03b2: return "pmpaddr2";726case 0x03b3: return "pmpaddr3";727case 0x03b4: return "pmpaddr4";728case 0x03b5: return "pmpaddr5";729case 0x03b6: return "pmpaddr6";730case 0x03b7: return "pmpaddr7";731case 0x03b8: return "pmpaddr8";732case 0x03b9: return "pmpaddr9";733case 0x03ba: return "pmpaddr10";734case 0x03bb: return "pmpaddr11";735case 0x03bc: return "pmpaddr12";736case 0x03bd: return "pmpaddr13";737case 0x03be: return "pmpaddr14";738case 0x03bf: return "pmpaddr15";739case 0x0600: return "hstatus";740case 0x0602: return "hedeleg";741case 0x0603: return "hideleg";742case 0x0604: return "hie";743case 0x0605: return "htimedelta";744case 0x0606: return "hcounteren";745case 0x0607: return "hgeie";746case 0x0615: return "htimedeltah";747case 0x0643: return "htval";748case 0x0644: return "hip";749case 0x0645: return "hvip";750case 0x064a: return "htinst";751case 0x0680: return "hgatp";752case 0x07a0: return "tselect";753case 0x07a1: return "tdata1";754case 0x07a2: return "tdata2";755case 0x07a3: return "tdata3";756case 0x07a4: return "tinfo";757case 0x07a5: return "tcontrol";758case 0x07a8: return "mcontext";759case 0x07a9: return "mnoise";760case 0x07aa: return "scontext";761case 0x07b0: return "dcsr";762case 0x07b1: return "dpc";763case 0x07b2: return "dscratch0";764case 0x07b3: return "dscratch1";765case 0x0b00: return "mcycle";766case 0x0b02: return "minstret";767case 0x0b03: return "mhpmcounter3";768case 0x0b04: return "mhpmcounter4";769case 0x0b05: return "mhpmcounter5";770case 0x0b06: return "mhpmcounter6";771case 0x0b07: return "mhpmcounter7";772case 0x0b08: return "mhpmcounter8";773case 0x0b09: return "mhpmcounter9";774case 0x0b0a: return "mhpmcounter10";775case 0x0b0b: return "mhpmcounter11";776case 0x0b0c: return "mhpmcounter12";777case 0x0b0d: return "mhpmcounter13";778case 0x0b0e: return "mhpmcounter14";779case 0x0b0f: return "mhpmcounter15";780case 0x0b10: return "mhpmcounter16";781case 0x0b11: return "mhpmcounter17";782case 0x0b12: return "mhpmcounter18";783case 0x0b13: return "mhpmcounter19";784case 0x0b14: return "mhpmcounter20";785case 0x0b15: return "mhpmcounter21";786case 0x0b16: return "mhpmcounter22";787case 0x0b17: return "mhpmcounter23";788case 0x0b18: return "mhpmcounter24";789case 0x0b19: return "mhpmcounter25";790case 0x0b1a: return "mhpmcounter26";791case 0x0b1b: return "mhpmcounter27";792case 0x0b1c: return "mhpmcounter28";793case 0x0b1d: return "mhpmcounter29";794case 0x0b1e: return "mhpmcounter30";795case 0x0b1f: return "mhpmcounter31";796case 0x0b80: return "mcycleh";797case 0x0b82: return "minstreth";798case 0x0b83: return "mhpmcounter3h";799case 0x0b84: return "mhpmcounter4h";800case 0x0b85: return "mhpmcounter5h";801case 0x0b86: return "mhpmcounter6h";802case 0x0b87: return "mhpmcounter7h";803case 0x0b88: return "mhpmcounter8h";804case 0x0b89: return "mhpmcounter9h";805case 0x0b8a: return "mhpmcounter10h";806case 0x0b8b: return "mhpmcounter11h";807case 0x0b8c: return "mhpmcounter12h";808case 0x0b8d: return "mhpmcounter13h";809case 0x0b8e: return "mhpmcounter14h";810case 0x0b8f: return "mhpmcounter15h";811case 0x0b90: return "mhpmcounter16h";812case 0x0b91: return "mhpmcounter17h";813case 0x0b92: return "mhpmcounter18h";814case 0x0b93: return "mhpmcounter19h";815case 0x0b94: return "mhpmcounter20h";816case 0x0b95: return "mhpmcounter21h";817case 0x0b96: return "mhpmcounter22h";818case 0x0b97: return "mhpmcounter23h";819case 0x0b98: return "mhpmcounter24h";820case 0x0b99: return "mhpmcounter25h";821case 0x0b9a: return "mhpmcounter26h";822case 0x0b9b: return "mhpmcounter27h";823case 0x0b9c: return "mhpmcounter28h";824case 0x0b9d: return "mhpmcounter29h";825case 0x0b9e: return "mhpmcounter30h";826case 0x0b9f: return "mhpmcounter31h";827case 0x0c00: return "cycle";828case 0x0c01: return "time";829case 0x0c02: return "instret";830case 0x0c03: return "hpmcounter3";831case 0x0c04: return "hpmcounter4";832case 0x0c05: return "hpmcounter5";833case 0x0c06: return "hpmcounter6";834case 0x0c07: return "hpmcounter7";835case 0x0c08: return "hpmcounter8";836case 0x0c09: return "hpmcounter9";837case 0x0c0a: return "hpmcounter10";838case 0x0c0b: return "hpmcounter11";839case 0x0c0c: return "hpmcounter12";840case 0x0c0d: return "hpmcounter13";841case 0x0c0e: return "hpmcounter14";842case 0x0c0f: return "hpmcounter15";843case 0x0c10: return "hpmcounter16";844case 0x0c11: return "hpmcounter17";845case 0x0c12: return "hpmcounter18";846case 0x0c13: return "hpmcounter19";847case 0x0c14: return "hpmcounter20";848case 0x0c15: return "hpmcounter21";849case 0x0c16: return "hpmcounter22";850case 0x0c17: return "hpmcounter23";851case 0x0c18: return "hpmcounter24";852case 0x0c19: return "hpmcounter25";853case 0x0c1a: return "hpmcounter26";854case 0x0c1b: return "hpmcounter27";855case 0x0c1c: return "hpmcounter28";856case 0x0c1d: return "hpmcounter29";857case 0x0c1e: return "hpmcounter30";858case 0x0c1f: return "hpmcounter31";859case 0x0c20: return "vl";860case 0x0c21: return "vtype";861case 0x0c22: return "vlenb";862case 0x0c80: return "cycleh";863case 0x0c81: return "timeh";864case 0x0c82: return "instreth";865case 0x0c83: return "hpmcounter3h";866case 0x0c84: return "hpmcounter4h";867case 0x0c85: return "hpmcounter5h";868case 0x0c86: return "hpmcounter6h";869case 0x0c87: return "hpmcounter7h";870case 0x0c88: return "hpmcounter8h";871case 0x0c89: return "hpmcounter9h";872case 0x0c8a: return "hpmcounter10h";873case 0x0c8b: return "hpmcounter11h";874case 0x0c8c: return "hpmcounter12h";875case 0x0c8d: return "hpmcounter13h";876case 0x0c8e: return "hpmcounter14h";877case 0x0c8f: return "hpmcounter15h";878case 0x0c90: return "hpmcounter16h";879case 0x0c91: return "hpmcounter17h";880case 0x0c92: return "hpmcounter18h";881case 0x0c93: return "hpmcounter19h";882case 0x0c94: return "hpmcounter20h";883case 0x0c95: return "hpmcounter21h";884case 0x0c96: return "hpmcounter22h";885case 0x0c97: return "hpmcounter23h";886case 0x0c98: return "hpmcounter24h";887case 0x0c99: return "hpmcounter25h";888case 0x0c9a: return "hpmcounter26h";889case 0x0c9b: return "hpmcounter27h";890case 0x0c9c: return "hpmcounter28h";891case 0x0c9d: return "hpmcounter29h";892case 0x0c9e: return "hpmcounter30h";893case 0x0c9f: return "hpmcounter31h";894case 0x0e12: return "hgeip";895case 0x0f11: return "mvendorid";896case 0x0f12: return "marchid";897case 0x0f13: return "mimpid";898case 0x0f14: return "mhartid";899case 0x0f15: return "mentropy";900default: return NULL;901}902}903904/* decode opcode */905906static void decode_inst_opcode(rv_decode *dec, rv_isa isa)907{908rv_inst inst = dec->inst;909rv_opcode op = rv_op_illegal;910switch (((inst >> 0) & 0b11)) {911case 0:912switch (((inst >> 13) & 0b111)) {913case 0: op = rv_op_c_addi4spn; break;914case 1: op = (isa == rv128) ? rv_op_c_lq : rv_op_c_fld; break;915case 2: op = rv_op_c_lw; break;916case 3: op = (isa == rv32) ? rv_op_c_flw : rv_op_c_ld; break;917case 5: op = (isa == rv128) ? rv_op_c_sq : rv_op_c_fsd; break;918case 6: op = rv_op_c_sw; break;919case 7: op = (isa == rv32) ? rv_op_c_fsw : rv_op_c_sd; break;920}921break;922case 1:923switch (((inst >> 13) & 0b111)) {924case 0:925switch (((inst >> 2) & 0b11111111111)) {926case 0: op = rv_op_c_nop; break;927default: op = rv_op_c_addi; break;928}929break;930case 1: op = (isa == rv32) ? rv_op_c_jal : rv_op_c_addiw; break;931case 2: op = rv_op_c_li; break;932case 3:933switch (((inst >> 7) & 0b11111)) {934case 2: op = rv_op_c_addi16sp; break;935default: op = rv_op_c_lui; break;936}937break;938case 4:939switch (((inst >> 10) & 0b11)) {940case 0:941op = rv_op_c_srli;942break;943case 1:944op = rv_op_c_srai;945break;946case 2: op = rv_op_c_andi; break;947case 3:948switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) {949case 0: op = rv_op_c_sub; break;950case 1: op = rv_op_c_xor; break;951case 2: op = rv_op_c_or; break;952case 3: op = rv_op_c_and; break;953case 4: op = rv_op_c_subw; break;954case 5: op = rv_op_c_addw; break;955}956break;957}958break;959case 5: op = rv_op_c_j; break;960case 6: op = rv_op_c_beqz; break;961case 7: op = rv_op_c_bnez; break;962}963break;964case 2:965switch (((inst >> 13) & 0b111)) {966case 0:967op = rv_op_c_slli;968break;969case 1: op = (isa == rv128) ? rv_op_c_lqsp : rv_op_c_fldsp; break;970case 2: op = rv_op_c_lwsp; break;971case 3: op = (isa == rv32) ? rv_op_c_flwsp : rv_op_c_ldsp; break;972case 4:973switch (((inst >> 12) & 0b1)) {974case 0:975switch (((inst >> 2) & 0b11111)) {976case 0: op = rv_op_c_jr; break;977default: op = rv_op_c_mv; break;978}979break;980case 1:981switch (((inst >> 2) & 0b11111)) {982case 0:983switch (((inst >> 7) & 0b11111)) {984case 0: op = rv_op_c_ebreak; break;985default: op = rv_op_c_jalr; break;986}987break;988default: op = rv_op_c_add; break;989}990break;991}992break;993case 5: op = (isa == rv128) ? rv_op_c_sqsp : rv_op_c_fsdsp; break;994case 6: op = rv_op_c_swsp; break;995case 7: op = (isa == rv32) ? rv_op_c_fswsp : rv_op_c_sdsp; break;996}997break;998case 3:999switch (((inst >> 2) & 0b11111)) {1000case 0:1001switch (((inst >> 12) & 0b111)) {1002case 0: op = rv_op_lb; break;1003case 1: op = rv_op_lh; break;1004case 2: op = rv_op_lw; break;1005case 3: op = rv_op_ld; break;1006case 4: op = rv_op_lbu; break;1007case 5: op = rv_op_lhu; break;1008case 6: op = rv_op_lwu; break;1009case 7: op = rv_op_ldu; break;1010}1011break;1012case 1:1013switch (((inst >> 12) & 0b111)) {1014case 2: op = rv_op_flw; break;1015case 3: op = rv_op_fld; break;1016case 4: op = rv_op_flq; break;1017}1018break;1019case 3:1020switch (((inst >> 12) & 0b111)) {1021case 0: op = rv_op_fence; break;1022case 1: op = rv_op_fence_i; break;1023case 2: op = rv_op_lq; break;1024}1025break;1026case 4:1027switch (((inst >> 12) & 0b111)) {1028case 0: op = rv_op_addi; break;1029case 1:1030switch (((inst >> 27) & 0b11111)) {1031case 0: op = rv_op_slli; break;1032}1033break;1034case 2: op = rv_op_slti; break;1035case 3: op = rv_op_sltiu; break;1036case 4: op = rv_op_xori; break;1037case 5:1038switch (((inst >> 27) & 0b11111)) {1039case 0: op = rv_op_srli; break;1040case 8: op = rv_op_srai; break;1041}1042break;1043case 6: op = rv_op_ori; break;1044case 7: op = rv_op_andi; break;1045}1046break;1047case 5: op = rv_op_auipc; break;1048case 6:1049switch (((inst >> 12) & 0b111)) {1050case 0: op = rv_op_addiw; break;1051case 1:1052switch (((inst >> 25) & 0b1111111)) {1053case 0: op = rv_op_slliw; break;1054}1055break;1056case 5:1057switch (((inst >> 25) & 0b1111111)) {1058case 0: op = rv_op_srliw; break;1059case 32: op = rv_op_sraiw; break;1060}1061break;1062}1063break;1064case 8:1065switch (((inst >> 12) & 0b111)) {1066case 0: op = rv_op_sb; break;1067case 1: op = rv_op_sh; break;1068case 2: op = rv_op_sw; break;1069case 3: op = rv_op_sd; break;1070case 4: op = rv_op_sq; break;1071}1072break;1073case 9:1074switch (((inst >> 12) & 0b111)) {1075case 2: op = rv_op_fsw; break;1076case 3: op = rv_op_fsd; break;1077case 4: op = rv_op_fsq; break;1078}1079break;1080case 11:1081switch (((inst >> 24) & 0b11111000) | ((inst >> 12) & 0b00000111)) {1082case 2: op = rv_op_amoadd_w; break;1083case 3: op = rv_op_amoadd_d; break;1084case 4: op = rv_op_amoadd_q; break;1085case 10: op = rv_op_amoswap_w; break;1086case 11: op = rv_op_amoswap_d; break;1087case 12: op = rv_op_amoswap_q; break;1088case 18:1089switch (((inst >> 20) & 0b11111)) {1090case 0: op = rv_op_lr_w; break;1091}1092break;1093case 19:1094switch (((inst >> 20) & 0b11111)) {1095case 0: op = rv_op_lr_d; break;1096}1097break;1098case 20:1099switch (((inst >> 20) & 0b11111)) {1100case 0: op = rv_op_lr_q; break;1101}1102break;1103case 26: op = rv_op_sc_w; break;1104case 27: op = rv_op_sc_d; break;1105case 28: op = rv_op_sc_q; break;1106case 34: op = rv_op_amoxor_w; break;1107case 35: op = rv_op_amoxor_d; break;1108case 36: op = rv_op_amoxor_q; break;1109case 66: op = rv_op_amoor_w; break;1110case 67: op = rv_op_amoor_d; break;1111case 68: op = rv_op_amoor_q; break;1112case 98: op = rv_op_amoand_w; break;1113case 99: op = rv_op_amoand_d; break;1114case 100: op = rv_op_amoand_q; break;1115case 130: op = rv_op_amomin_w; break;1116case 131: op = rv_op_amomin_d; break;1117case 132: op = rv_op_amomin_q; break;1118case 162: op = rv_op_amomax_w; break;1119case 163: op = rv_op_amomax_d; break;1120case 164: op = rv_op_amomax_q; break;1121case 194: op = rv_op_amominu_w; break;1122case 195: op = rv_op_amominu_d; break;1123case 196: op = rv_op_amominu_q; break;1124case 226: op = rv_op_amomaxu_w; break;1125case 227: op = rv_op_amomaxu_d; break;1126case 228: op = rv_op_amomaxu_q; break;1127}1128break;1129case 12:1130switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {1131case 0: op = rv_op_add; break;1132case 1: op = rv_op_sll; break;1133case 2: op = rv_op_slt; break;1134case 3: op = rv_op_sltu; break;1135case 4: op = rv_op_xor; break;1136case 5: op = rv_op_srl; break;1137case 6: op = rv_op_or; break;1138case 7: op = rv_op_and; break;1139case 8: op = rv_op_mul; break;1140case 9: op = rv_op_mulh; break;1141case 10: op = rv_op_mulhsu; break;1142case 11: op = rv_op_mulhu; break;1143case 12: op = rv_op_div; break;1144case 13: op = rv_op_divu; break;1145case 14: op = rv_op_rem; break;1146case 15: op = rv_op_remu; break;1147case 256: op = rv_op_sub; break;1148case 261: op = rv_op_sra; break;1149}1150break;1151case 13: op = rv_op_lui; break;1152case 14:1153switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {1154case 0: op = rv_op_addw; break;1155case 1: op = rv_op_sllw; break;1156case 5: op = rv_op_srlw; break;1157case 8: op = rv_op_mulw; break;1158case 12: op = rv_op_divw; break;1159case 13: op = rv_op_divuw; break;1160case 14: op = rv_op_remw; break;1161case 15: op = rv_op_remuw; break;1162case 256: op = rv_op_subw; break;1163case 261: op = rv_op_sraw; break;1164}1165break;1166case 16:1167switch (((inst >> 25) & 0b11)) {1168case 0: op = rv_op_fmadd_s; break;1169case 1: op = rv_op_fmadd_d; break;1170case 3: op = rv_op_fmadd_q; break;1171}1172break;1173case 17:1174switch (((inst >> 25) & 0b11)) {1175case 0: op = rv_op_fmsub_s; break;1176case 1: op = rv_op_fmsub_d; break;1177case 3: op = rv_op_fmsub_q; break;1178}1179break;1180case 18:1181switch (((inst >> 25) & 0b11)) {1182case 0: op = rv_op_fnmsub_s; break;1183case 1: op = rv_op_fnmsub_d; break;1184case 3: op = rv_op_fnmsub_q; break;1185}1186break;1187case 19:1188switch (((inst >> 25) & 0b11)) {1189case 0: op = rv_op_fnmadd_s; break;1190case 1: op = rv_op_fnmadd_d; break;1191case 3: op = rv_op_fnmadd_q; break;1192}1193break;1194case 20:1195switch (((inst >> 25) & 0b1111111)) {1196case 0: op = rv_op_fadd_s; break;1197case 1: op = rv_op_fadd_d; break;1198case 3: op = rv_op_fadd_q; break;1199case 4: op = rv_op_fsub_s; break;1200case 5: op = rv_op_fsub_d; break;1201case 7: op = rv_op_fsub_q; break;1202case 8: op = rv_op_fmul_s; break;1203case 9: op = rv_op_fmul_d; break;1204case 11: op = rv_op_fmul_q; break;1205case 12: op = rv_op_fdiv_s; break;1206case 13: op = rv_op_fdiv_d; break;1207case 15: op = rv_op_fdiv_q; break;1208case 16:1209switch (((inst >> 12) & 0b111)) {1210case 0: op = rv_op_fsgnj_s; break;1211case 1: op = rv_op_fsgnjn_s; break;1212case 2: op = rv_op_fsgnjx_s; break;1213}1214break;1215case 17:1216switch (((inst >> 12) & 0b111)) {1217case 0: op = rv_op_fsgnj_d; break;1218case 1: op = rv_op_fsgnjn_d; break;1219case 2: op = rv_op_fsgnjx_d; break;1220}1221break;1222case 19:1223switch (((inst >> 12) & 0b111)) {1224case 0: op = rv_op_fsgnj_q; break;1225case 1: op = rv_op_fsgnjn_q; break;1226case 2: op = rv_op_fsgnjx_q; break;1227}1228break;1229case 20:1230switch (((inst >> 12) & 0b111)) {1231case 0: op = rv_op_fmin_s; break;1232case 1: op = rv_op_fmax_s; break;1233}1234break;1235case 21:1236switch (((inst >> 12) & 0b111)) {1237case 0: op = rv_op_fmin_d; break;1238case 1: op = rv_op_fmax_d; break;1239}1240break;1241case 23:1242switch (((inst >> 12) & 0b111)) {1243case 0: op = rv_op_fmin_q; break;1244case 1: op = rv_op_fmax_q; break;1245}1246break;1247case 32:1248switch (((inst >> 20) & 0b11111)) {1249case 1: op = rv_op_fcvt_s_d; break;1250case 3: op = rv_op_fcvt_s_q; break;1251}1252break;1253case 33:1254switch (((inst >> 20) & 0b11111)) {1255case 0: op = rv_op_fcvt_d_s; break;1256case 3: op = rv_op_fcvt_d_q; break;1257}1258break;1259case 35:1260switch (((inst >> 20) & 0b11111)) {1261case 0: op = rv_op_fcvt_q_s; break;1262case 1: op = rv_op_fcvt_q_d; break;1263}1264break;1265case 44:1266switch (((inst >> 20) & 0b11111)) {1267case 0: op = rv_op_fsqrt_s; break;1268}1269break;1270case 45:1271switch (((inst >> 20) & 0b11111)) {1272case 0: op = rv_op_fsqrt_d; break;1273}1274break;1275case 47:1276switch (((inst >> 20) & 0b11111)) {1277case 0: op = rv_op_fsqrt_q; break;1278}1279break;1280case 80:1281switch (((inst >> 12) & 0b111)) {1282case 0: op = rv_op_fle_s; break;1283case 1: op = rv_op_flt_s; break;1284case 2: op = rv_op_feq_s; break;1285}1286break;1287case 81:1288switch (((inst >> 12) & 0b111)) {1289case 0: op = rv_op_fle_d; break;1290case 1: op = rv_op_flt_d; break;1291case 2: op = rv_op_feq_d; break;1292}1293break;1294case 83:1295switch (((inst >> 12) & 0b111)) {1296case 0: op = rv_op_fle_q; break;1297case 1: op = rv_op_flt_q; break;1298case 2: op = rv_op_feq_q; break;1299}1300break;1301case 96:1302switch (((inst >> 20) & 0b11111)) {1303case 0: op = rv_op_fcvt_w_s; break;1304case 1: op = rv_op_fcvt_wu_s; break;1305case 2: op = rv_op_fcvt_l_s; break;1306case 3: op = rv_op_fcvt_lu_s; break;1307}1308break;1309case 97:1310switch (((inst >> 20) & 0b11111)) {1311case 0: op = rv_op_fcvt_w_d; break;1312case 1: op = rv_op_fcvt_wu_d; break;1313case 2: op = rv_op_fcvt_l_d; break;1314case 3: op = rv_op_fcvt_lu_d; break;1315}1316break;1317case 99:1318switch (((inst >> 20) & 0b11111)) {1319case 0: op = rv_op_fcvt_w_q; break;1320case 1: op = rv_op_fcvt_wu_q; break;1321case 2: op = rv_op_fcvt_l_q; break;1322case 3: op = rv_op_fcvt_lu_q; break;1323}1324break;1325case 104:1326switch (((inst >> 20) & 0b11111)) {1327case 0: op = rv_op_fcvt_s_w; break;1328case 1: op = rv_op_fcvt_s_wu; break;1329case 2: op = rv_op_fcvt_s_l; break;1330case 3: op = rv_op_fcvt_s_lu; break;1331}1332break;1333case 105:1334switch (((inst >> 20) & 0b11111)) {1335case 0: op = rv_op_fcvt_d_w; break;1336case 1: op = rv_op_fcvt_d_wu; break;1337case 2: op = rv_op_fcvt_d_l; break;1338case 3: op = rv_op_fcvt_d_lu; break;1339}1340break;1341case 107:1342switch (((inst >> 20) & 0b11111)) {1343case 0: op = rv_op_fcvt_q_w; break;1344case 1: op = rv_op_fcvt_q_wu; break;1345case 2: op = rv_op_fcvt_q_l; break;1346case 3: op = rv_op_fcvt_q_lu; break;1347}1348break;1349case 112:1350switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {1351case 0: op = rv_op_fmv_x_s; break;1352case 1: op = rv_op_fclass_s; break;1353}1354break;1355case 113:1356switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {1357case 0: op = rv_op_fmv_x_d; break;1358case 1: op = rv_op_fclass_d; break;1359}1360break;1361case 115:1362switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {1363case 0: op = rv_op_fmv_x_q; break;1364case 1: op = rv_op_fclass_q; break;1365}1366break;1367case 120:1368switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {1369case 0: op = rv_op_fmv_s_x; break;1370}1371break;1372case 121:1373switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {1374case 0: op = rv_op_fmv_d_x; break;1375}1376break;1377case 123:1378switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {1379case 0: op = rv_op_fmv_q_x; break;1380}1381break;1382}1383break;1384case 22:1385switch (((inst >> 12) & 0b111)) {1386case 0: op = rv_op_addid; break;1387case 1:1388switch (((inst >> 26) & 0b111111)) {1389case 0: op = rv_op_sllid; break;1390}1391break;1392case 5:1393switch (((inst >> 26) & 0b111111)) {1394case 0: op = rv_op_srlid; break;1395case 16: op = rv_op_sraid; break;1396}1397break;1398}1399break;1400case 24:1401switch (((inst >> 12) & 0b111)) {1402case 0: op = rv_op_beq; break;1403case 1: op = rv_op_bne; break;1404case 4: op = rv_op_blt; break;1405case 5: op = rv_op_bge; break;1406case 6: op = rv_op_bltu; break;1407case 7: op = rv_op_bgeu; break;1408}1409break;1410case 25:1411switch (((inst >> 12) & 0b111)) {1412case 0: op = rv_op_jalr; break;1413}1414break;1415case 27: op = rv_op_jal; break;1416case 28:1417switch (((inst >> 12) & 0b111)) {1418case 0:1419switch (((inst >> 20) & 0b111111100000) | ((inst >> 7) & 0b000000011111)) {1420case 0:1421switch (((inst >> 15) & 0b1111111111)) {1422case 0: op = rv_op_ecall; break;1423case 32: op = rv_op_ebreak; break;1424case 64: op = rv_op_uret; break;1425}1426break;1427case 256:1428switch (((inst >> 20) & 0b11111)) {1429case 2:1430switch (((inst >> 15) & 0b11111)) {1431case 0: op = rv_op_sret; break;1432}1433break;1434case 4: op = rv_op_sfence_vm; break;1435case 5:1436switch (((inst >> 15) & 0b11111)) {1437case 0: op = rv_op_wfi; break;1438}1439break;1440}1441break;1442case 288: op = rv_op_sfence_vma; break;1443case 512:1444switch (((inst >> 15) & 0b1111111111)) {1445case 64: op = rv_op_hret; break;1446}1447break;1448case 768:1449switch (((inst >> 15) & 0b1111111111)) {1450case 64: op = rv_op_mret; break;1451}1452break;1453case 1952:1454switch (((inst >> 15) & 0b1111111111)) {1455case 576: op = rv_op_dret; break;1456}1457break;1458}1459break;1460case 1: op = rv_op_csrrw; break;1461case 2: op = rv_op_csrrs; break;1462case 3: op = rv_op_csrrc; break;1463case 5: op = rv_op_csrrwi; break;1464case 6: op = rv_op_csrrsi; break;1465case 7: op = rv_op_csrrci; break;1466}1467break;1468case 30:1469switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {1470case 0: op = rv_op_addd; break;1471case 1: op = rv_op_slld; break;1472case 5: op = rv_op_srld; break;1473case 8: op = rv_op_muld; break;1474case 12: op = rv_op_divd; break;1475case 13: op = rv_op_divud; break;1476case 14: op = rv_op_remd; break;1477case 15: op = rv_op_remud; break;1478case 256: op = rv_op_subd; break;1479case 261: op = rv_op_srad; break;1480}1481break;1482}1483break;1484}1485dec->op = op;1486}14871488/* operand extractors */14891490static uint32_t operand_rd(rv_inst inst) {1491return (inst << 52) >> 59;1492}14931494static uint32_t operand_rs1(rv_inst inst) {1495return (inst << 44) >> 59;1496}14971498static uint32_t operand_rs2(rv_inst inst) {1499return (inst << 39) >> 59;1500}15011502static uint32_t operand_rs3(rv_inst inst) {1503return (inst << 32) >> 59;1504}15051506static uint32_t operand_aq(rv_inst inst) {1507return (inst << 37) >> 63;1508}15091510static uint32_t operand_rl(rv_inst inst) {1511return (inst << 38) >> 63;1512}15131514static uint32_t operand_pred(rv_inst inst) {1515return (inst << 36) >> 60;1516}15171518static uint32_t operand_succ(rv_inst inst) {1519return (inst << 40) >> 60;1520}15211522static uint32_t operand_rm(rv_inst inst) {1523return (inst << 49) >> 61;1524}15251526static uint32_t operand_shamt5(rv_inst inst) {1527return (inst << 39) >> 59;1528}15291530static uint32_t operand_shamt6(rv_inst inst) {1531return (inst << 38) >> 58;1532}15331534static uint32_t operand_shamt7(rv_inst inst) {1535return (inst << 37) >> 57;1536}15371538static uint32_t operand_crdq(rv_inst inst) {1539return (inst << 59) >> 61;1540}15411542static uint32_t operand_crs1q(rv_inst inst) {1543return (inst << 54) >> 61;1544}15451546static uint32_t operand_crs1rdq(rv_inst inst) {1547return (inst << 54) >> 61;1548}15491550static uint32_t operand_crs2q(rv_inst inst) {1551return (inst << 59) >> 61;1552}15531554static uint32_t operand_crd(rv_inst inst) {1555return (inst << 52) >> 59;1556}15571558static uint32_t operand_crs1(rv_inst inst) {1559return (inst << 52) >> 59;1560}15611562static uint32_t operand_crs1rd(rv_inst inst) {1563return (inst << 52) >> 59;1564}15651566static uint32_t operand_crs2(rv_inst inst) {1567return (inst << 57) >> 59;1568}15691570static uint32_t operand_cimmsh5(rv_inst inst) {1571return (inst << 57) >> 59;1572}15731574static uint32_t operand_csr12(rv_inst inst) {1575return (inst << 32) >> 52;1576}15771578static int32_t operand_imm12(rv_inst inst) {1579return ((int64_t)inst << 32) >> 52;1580}15811582static int32_t operand_imm20(rv_inst inst) {1583return (((int64_t)inst << 32) >> 44) << 12;1584}15851586static int32_t operand_jimm20(rv_inst inst) {1587return (((int64_t)inst << 32) >> 63) << 20 |1588((inst << 33) >> 54) << 1 |1589((inst << 43) >> 63) << 11 |1590((inst << 44) >> 56) << 12;1591}15921593static int32_t operand_simm12(rv_inst inst) {1594return (((int64_t)inst << 32) >> 57) << 5 |1595(inst << 52) >> 59;1596}15971598static int32_t operand_sbimm12(rv_inst inst) {1599return (((int64_t)inst << 32) >> 63) << 12 |1600((inst << 33) >> 58) << 5 |1601((inst << 52) >> 60) << 1 |1602((inst << 56) >> 63) << 11;1603}16041605static uint32_t operand_cimmsh6(rv_inst inst) {1606return ((inst << 51) >> 63) << 5 |1607(inst << 57) >> 59;1608}16091610static int32_t operand_cimmi(rv_inst inst) {1611return (((int64_t)inst << 51) >> 63) << 5 |1612(inst << 57) >> 59;1613}16141615static int32_t operand_cimmui(rv_inst inst) {1616return (((int64_t)inst << 51) >> 63) << 17 |1617((inst << 57) >> 59) << 12;1618}16191620static uint32_t operand_cimmlwsp(rv_inst inst) {1621return ((inst << 51) >> 63) << 5 |1622((inst << 57) >> 61) << 2 |1623((inst << 60) >> 62) << 6;1624}16251626static uint32_t operand_cimmldsp(rv_inst inst) {1627return ((inst << 51) >> 63) << 5 |1628((inst << 57) >> 62) << 3 |1629((inst << 59) >> 61) << 6;1630}16311632static uint32_t operand_cimmlqsp(rv_inst inst) {1633return ((inst << 51) >> 63) << 5 |1634((inst << 57) >> 63) << 4 |1635((inst << 58) >> 60) << 6;1636}16371638static int32_t operand_cimm16sp(rv_inst inst) {1639return (((int64_t)inst << 51) >> 63) << 9 |1640((inst << 57) >> 63) << 4 |1641((inst << 58) >> 63) << 6 |1642((inst << 59) >> 62) << 7 |1643((inst << 61) >> 63) << 5;1644}16451646static int32_t operand_cimmj(rv_inst inst) {1647return (((int64_t)inst << 51) >> 63) << 11 |1648((inst << 52) >> 63) << 4 |1649((inst << 53) >> 62) << 8 |1650((inst << 55) >> 63) << 10 |1651((inst << 56) >> 63) << 6 |1652((inst << 57) >> 63) << 7 |1653((inst << 58) >> 61) << 1 |1654((inst << 61) >> 63) << 5;1655}16561657static int32_t operand_cimmb(rv_inst inst) {1658return (((int64_t)inst << 51) >> 63) << 8 |1659((inst << 52) >> 62) << 3 |1660((inst << 57) >> 62) << 6 |1661((inst << 59) >> 62) << 1 |1662((inst << 61) >> 63) << 5;1663}16641665static uint32_t operand_cimmswsp(rv_inst inst) {1666return ((inst << 51) >> 60) << 2 |1667((inst << 55) >> 62) << 6;1668}16691670static uint32_t operand_cimmsdsp(rv_inst inst) {1671return ((inst << 51) >> 61) << 3 |1672((inst << 54) >> 61) << 6;1673}16741675static uint32_t operand_cimmsqsp(rv_inst inst) {1676return ((inst << 51) >> 62) << 4 |1677((inst << 53) >> 60) << 6;1678}16791680static uint32_t operand_cimm4spn(rv_inst inst) {1681return ((inst << 51) >> 62) << 4 |1682((inst << 53) >> 60) << 6 |1683((inst << 57) >> 63) << 2 |1684((inst << 58) >> 63) << 3;1685}16861687static uint32_t operand_cimmw(rv_inst inst) {1688return ((inst << 51) >> 61) << 3 |1689((inst << 57) >> 63) << 2 |1690((inst << 58) >> 63) << 6;1691}16921693static uint32_t operand_cimmd(rv_inst inst) {1694return ((inst << 51) >> 61) << 3 |1695((inst << 57) >> 62) << 6;1696}16971698static uint32_t operand_cimmq(rv_inst inst) {1699return ((inst << 51) >> 62) << 4 |1700((inst << 53) >> 63) << 8 |1701((inst << 57) >> 62) << 6;1702}17031704/* decode operands */17051706static void decode_inst_operands(rv_decode *dec)1707{1708rv_inst inst = dec->inst;1709dec->codec = opcode_data[dec->op].codec;1710switch (dec->codec) {1711case rv_codec_none:1712dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;1713dec->imm = 0;1714break;1715case rv_codec_u:1716dec->rd = operand_rd(inst);1717dec->rs1 = dec->rs2 = rv_ireg_zero;1718dec->imm = operand_imm20(inst);1719break;1720case rv_codec_uj:1721dec->rd = operand_rd(inst);1722dec->rs1 = dec->rs2 = rv_ireg_zero;1723dec->imm = operand_jimm20(inst);1724break;1725case rv_codec_i:1726dec->rd = operand_rd(inst);1727dec->rs1 = operand_rs1(inst);1728dec->rs2 = rv_ireg_zero;1729dec->imm = operand_imm12(inst);1730break;1731case rv_codec_i_sh5:1732dec->rd = operand_rd(inst);1733dec->rs1 = operand_rs1(inst);1734dec->rs2 = rv_ireg_zero;1735dec->imm = operand_shamt5(inst);1736break;1737case rv_codec_i_sh6:1738dec->rd = operand_rd(inst);1739dec->rs1 = operand_rs1(inst);1740dec->rs2 = rv_ireg_zero;1741dec->imm = operand_shamt6(inst);1742break;1743case rv_codec_i_sh7:1744dec->rd = operand_rd(inst);1745dec->rs1 = operand_rs1(inst);1746dec->rs2 = rv_ireg_zero;1747dec->imm = operand_shamt7(inst);1748break;1749case rv_codec_i_csr:1750dec->rd = operand_rd(inst);1751dec->rs1 = operand_rs1(inst);1752dec->rs2 = rv_ireg_zero;1753dec->imm = operand_csr12(inst);1754break;1755case rv_codec_s:1756dec->rd = rv_ireg_zero;1757dec->rs1 = operand_rs1(inst);1758dec->rs2 = operand_rs2(inst);1759dec->imm = operand_simm12(inst);1760break;1761case rv_codec_sb:1762dec->rd = rv_ireg_zero;1763dec->rs1 = operand_rs1(inst);1764dec->rs2 = operand_rs2(inst);1765dec->imm = operand_sbimm12(inst);1766break;1767case rv_codec_r:1768dec->rd = operand_rd(inst);1769dec->rs1 = operand_rs1(inst);1770dec->rs2 = operand_rs2(inst);1771dec->imm = 0;1772break;1773case rv_codec_r_m:1774dec->rd = operand_rd(inst);1775dec->rs1 = operand_rs1(inst);1776dec->rs2 = operand_rs2(inst);1777dec->imm = 0;1778dec->rm = operand_rm(inst);1779break;1780case rv_codec_r4_m:1781dec->rd = operand_rd(inst);1782dec->rs1 = operand_rs1(inst);1783dec->rs2 = operand_rs2(inst);1784dec->rs3 = operand_rs3(inst);1785dec->imm = 0;1786dec->rm = operand_rm(inst);1787break;1788case rv_codec_r_a:1789dec->rd = operand_rd(inst);1790dec->rs1 = operand_rs1(inst);1791dec->rs2 = operand_rs2(inst);1792dec->imm = 0;1793dec->aq = operand_aq(inst);1794dec->rl = operand_rl(inst);1795break;1796case rv_codec_r_l:1797dec->rd = operand_rd(inst);1798dec->rs1 = operand_rs1(inst);1799dec->rs2 = rv_ireg_zero;1800dec->imm = 0;1801dec->aq = operand_aq(inst);1802dec->rl = operand_rl(inst);1803break;1804case rv_codec_r_f:1805dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;1806dec->pred = operand_pred(inst);1807dec->succ = operand_succ(inst);1808dec->imm = 0;1809break;1810case rv_codec_cb:1811dec->rd = rv_ireg_zero;1812dec->rs1 = operand_crs1q(inst) + 8;1813dec->rs2 = rv_ireg_zero;1814dec->imm = operand_cimmb(inst);1815break;1816case rv_codec_cb_imm:1817dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;1818dec->rs2 = rv_ireg_zero;1819dec->imm = operand_cimmi(inst);1820break;1821case rv_codec_cb_sh5:1822dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;1823dec->rs2 = rv_ireg_zero;1824dec->imm = operand_cimmsh5(inst);1825break;1826case rv_codec_cb_sh6:1827dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;1828dec->rs2 = rv_ireg_zero;1829dec->imm = operand_cimmsh6(inst);1830break;1831case rv_codec_ci:1832dec->rd = dec->rs1 = operand_crs1rd(inst);1833dec->rs2 = rv_ireg_zero;1834dec->imm = operand_cimmi(inst);1835break;1836case rv_codec_ci_sh5:1837dec->rd = dec->rs1 = operand_crs1rd(inst);1838dec->rs2 = rv_ireg_zero;1839dec->imm = operand_cimmsh5(inst);1840break;1841case rv_codec_ci_sh6:1842dec->rd = dec->rs1 = operand_crs1rd(inst);1843dec->rs2 = rv_ireg_zero;1844dec->imm = operand_cimmsh6(inst);1845break;1846case rv_codec_ci_16sp:1847dec->rd = rv_ireg_sp;1848dec->rs1 = rv_ireg_sp;1849dec->rs2 = rv_ireg_zero;1850dec->imm = operand_cimm16sp(inst);1851break;1852case rv_codec_ci_lwsp:1853dec->rd = operand_crd(inst);1854dec->rs1 = rv_ireg_sp;1855dec->rs2 = rv_ireg_zero;1856dec->imm = operand_cimmlwsp(inst);1857break;1858case rv_codec_ci_ldsp:1859dec->rd = operand_crd(inst);1860dec->rs1 = rv_ireg_sp;1861dec->rs2 = rv_ireg_zero;1862dec->imm = operand_cimmldsp(inst);1863break;1864case rv_codec_ci_lqsp:1865dec->rd = operand_crd(inst);1866dec->rs1 = rv_ireg_sp;1867dec->rs2 = rv_ireg_zero;1868dec->imm = operand_cimmlqsp(inst);1869break;1870case rv_codec_ci_li:1871dec->rd = operand_crd(inst);1872dec->rs1 = rv_ireg_zero;1873dec->rs2 = rv_ireg_zero;1874dec->imm = operand_cimmi(inst);1875break;1876case rv_codec_ci_lui:1877dec->rd = operand_crd(inst);1878dec->rs1 = rv_ireg_zero;1879dec->rs2 = rv_ireg_zero;1880dec->imm = operand_cimmui(inst);1881break;1882case rv_codec_ci_none:1883dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;1884dec->imm = 0;1885break;1886case rv_codec_ciw_4spn:1887dec->rd = operand_crdq(inst) + 8;1888dec->rs1 = rv_ireg_sp;1889dec->rs2 = rv_ireg_zero;1890dec->imm = operand_cimm4spn(inst);1891break;1892case rv_codec_cj:1893dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;1894dec->imm = operand_cimmj(inst);1895break;1896case rv_codec_cj_jal:1897dec->rd = rv_ireg_ra;1898dec->rs1 = dec->rs2 = rv_ireg_zero;1899dec->imm = operand_cimmj(inst);1900break;1901case rv_codec_cl_lw:1902dec->rd = operand_crdq(inst) + 8;1903dec->rs1 = operand_crs1q(inst) + 8;1904dec->rs2 = rv_ireg_zero;1905dec->imm = operand_cimmw(inst);1906break;1907case rv_codec_cl_ld:1908dec->rd = operand_crdq(inst) + 8;1909dec->rs1 = operand_crs1q(inst) + 8;1910dec->rs2 = rv_ireg_zero;1911dec->imm = operand_cimmd(inst);1912break;1913case rv_codec_cl_lq:1914dec->rd = operand_crdq(inst) + 8;1915dec->rs1 = operand_crs1q(inst) + 8;1916dec->rs2 = rv_ireg_zero;1917dec->imm = operand_cimmq(inst);1918break;1919case rv_codec_cr:1920dec->rd = dec->rs1 = operand_crs1rd(inst);1921dec->rs2 = operand_crs2(inst);1922dec->imm = 0;1923break;1924case rv_codec_cr_mv:1925dec->rd = operand_crd(inst);1926dec->rs1 = operand_crs2(inst);1927dec->rs2 = rv_ireg_zero;1928dec->imm = 0;1929break;1930case rv_codec_cr_jalr:1931dec->rd = rv_ireg_ra;1932dec->rs1 = operand_crs1(inst);1933dec->rs2 = rv_ireg_zero;1934dec->imm = 0;1935break;1936case rv_codec_cr_jr:1937dec->rd = rv_ireg_zero;1938dec->rs1 = operand_crs1(inst);1939dec->rs2 = rv_ireg_zero;1940dec->imm = 0;1941break;1942case rv_codec_cs:1943dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;1944dec->rs2 = operand_crs2q(inst) + 8;1945dec->imm = 0;1946break;1947case rv_codec_cs_sw:1948dec->rd = rv_ireg_zero;1949dec->rs1 = operand_crs1q(inst) + 8;1950dec->rs2 = operand_crs2q(inst) + 8;1951dec->imm = operand_cimmw(inst);1952break;1953case rv_codec_cs_sd:1954dec->rd = rv_ireg_zero;1955dec->rs1 = operand_crs1q(inst) + 8;1956dec->rs2 = operand_crs2q(inst) + 8;1957dec->imm = operand_cimmd(inst);1958break;1959case rv_codec_cs_sq:1960dec->rd = rv_ireg_zero;1961dec->rs1 = operand_crs1q(inst) + 8;1962dec->rs2 = operand_crs2q(inst) + 8;1963dec->imm = operand_cimmq(inst);1964break;1965case rv_codec_css_swsp:1966dec->rd = rv_ireg_zero;1967dec->rs1 = rv_ireg_sp;1968dec->rs2 = operand_crs2(inst);1969dec->imm = operand_cimmswsp(inst);1970break;1971case rv_codec_css_sdsp:1972dec->rd = rv_ireg_zero;1973dec->rs1 = rv_ireg_sp;1974dec->rs2 = operand_crs2(inst);1975dec->imm = operand_cimmsdsp(inst);1976break;1977case rv_codec_css_sqsp:1978dec->rd = rv_ireg_zero;1979dec->rs1 = rv_ireg_sp;1980dec->rs2 = operand_crs2(inst);1981dec->imm = operand_cimmsqsp(inst);1982break;1983};1984}19851986/* decompress instruction */19871988static void decode_inst_decompress(rv_decode *dec, rv_isa isa)1989{1990int decomp_op;1991switch (isa) {1992case rv32: decomp_op = opcode_data[dec->op].decomp_rv32; break;1993case rv64: decomp_op = opcode_data[dec->op].decomp_rv64; break;1994case rv128: decomp_op = opcode_data[dec->op].decomp_rv128; break;1995}1996if (decomp_op != rv_op_illegal) {1997if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) && dec->imm == 0) {1998dec->op = rv_op_illegal;1999} else {2000dec->op = decomp_op;2001dec->codec = opcode_data[decomp_op].codec;2002}2003}2004}20052006/* check constraint */20072008static bool check_constraints(rv_decode *dec, const rvc_constraint *c)2009{2010int32_t imm = dec->imm;2011uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2;2012while (*c != rvc_end) {2013switch (*c) {2014case rvc_rd_eq_ra: if (!(rd == 1)) return false; break;2015case rvc_rd_eq_x0: if (!(rd == 0)) return false; break;2016case rvc_rs1_eq_x0: if (!(rs1 == 0)) return false; break;2017case rvc_rs2_eq_x0: if (!(rs2 == 0)) return false; break;2018case rvc_rs2_eq_rs1: if (!(rs2 == rs1)) return false; break;2019case rvc_rs1_eq_ra: if (!(rs1 == 1)) return false; break;2020case rvc_imm_eq_zero: if (!(imm == 0)) return false; break;2021case rvc_imm_eq_n1: if (!(imm == -1)) return false; break;2022case rvc_imm_eq_p1: if (!(imm == 1)) return false; break;2023case rvc_csr_eq_0x001: if (!(imm == 0x001)) return false; break;2024case rvc_csr_eq_0x002: if (!(imm == 0x002)) return false; break;2025case rvc_csr_eq_0x003: if (!(imm == 0x003)) return false; break;2026case rvc_csr_eq_0xc00: if (!(imm == 0xc00)) return false; break;2027case rvc_csr_eq_0xc01: if (!(imm == 0xc01)) return false; break;2028case rvc_csr_eq_0xc02: if (!(imm == 0xc02)) return false; break;2029case rvc_csr_eq_0xc80: if (!(imm == 0xc80)) return false; break;2030case rvc_csr_eq_0xc81: if (!(imm == 0xc81)) return false; break;2031case rvc_csr_eq_0xc82: if (!(imm == 0xc82)) return false; break;2032default: break;2033}2034c++;2035}2036return true;2037}20382039/* lift instruction to pseudo-instruction */20402041static void decode_inst_lift_pseudo(rv_decode *dec)2042{2043const rv_comp_data *comp_data = opcode_data[dec->op].pseudo;2044if (!comp_data) {2045return;2046}2047while (comp_data->constraints) {2048if (check_constraints(dec, comp_data->constraints)) {2049dec->op = comp_data->op;2050dec->codec = opcode_data[dec->op].codec;2051return;2052}2053comp_data++;2054}2055}20562057/* format instruction */20582059static void append(char *s1, const char *s2, ssize_t n)2060{2061ssize_t l1 = strlen(s1);2062if (n - l1 - 1 > 0) {2063strncat(s1, s2, n - l1);2064}2065}20662067#define INST_FMT_2 "%04" PRIx64 " "2068#define INST_FMT_4 "%08" PRIx64 " "2069#define INST_FMT_6 "%012" PRIx64 " "2070#define INST_FMT_8 "%016" PRIx64 " "20712072static void decode_inst_format(char *buf, size_t buflen, size_t tab, rv_decode *dec)2073{2074char tmp[64];2075const char *fmt;20762077size_t len = inst_length(dec->inst);2078switch (len) {2079case 2:2080snprintf(buf, buflen, INST_FMT_2, dec->inst);2081break;2082case 4:2083snprintf(buf, buflen, INST_FMT_4, dec->inst);2084break;2085case 6:2086snprintf(buf, buflen, INST_FMT_6, dec->inst);2087break;2088default:2089snprintf(buf, buflen, INST_FMT_8, dec->inst);2090break;2091}20922093fmt = opcode_data[dec->op].format;2094while (*fmt) {2095switch (*fmt) {2096case 'O':2097append(buf, opcode_data[dec->op].name, buflen);2098break;2099case '(':2100append(buf, "(", buflen);2101break;2102case ',':2103append(buf, ",", buflen);2104break;2105case ')':2106append(buf, ")", buflen);2107break;2108case '0':2109append(buf, rv_ireg_name_sym[dec->rd], buflen);2110break;2111case '1':2112append(buf, rv_ireg_name_sym[dec->rs1], buflen);2113break;2114case '2':2115append(buf, rv_ireg_name_sym[dec->rs2], buflen);2116break;2117case '3':2118append(buf, rv_freg_name_sym[dec->rd], buflen);2119break;2120case '4':2121append(buf, rv_freg_name_sym[dec->rs1], buflen);2122break;2123case '5':2124append(buf, rv_freg_name_sym[dec->rs2], buflen);2125break;2126case '6':2127append(buf, rv_freg_name_sym[dec->rs3], buflen);2128break;2129case '7':2130snprintf(tmp, sizeof(tmp), "%d", dec->rs1);2131append(buf, tmp, buflen);2132break;2133case 'i':2134snprintf(tmp, sizeof(tmp), "%d", dec->imm);2135append(buf, tmp, buflen);2136break;2137case 'o':2138snprintf(tmp, sizeof(tmp), "%d", dec->imm);2139append(buf, tmp, buflen);2140while (strlen(buf) < tab * 2) {2141append(buf, " ", buflen);2142}2143snprintf(tmp, sizeof(tmp), "# 0x%" PRIx64,2144dec->pc + dec->imm);2145append(buf, tmp, buflen);2146break;2147case 'c': {2148const char *name = csr_name(dec->imm & 0xfff);2149if (name) {2150append(buf, name, buflen);2151} else {2152snprintf(tmp, sizeof(tmp), "0x%03x", dec->imm & 0xfff);2153append(buf, tmp, buflen);2154}2155break;2156}2157case 'r':2158switch (dec->rm) {2159case rv_rm_rne:2160append(buf, "rne", buflen);2161break;2162case rv_rm_rtz:2163append(buf, "rtz", buflen);2164break;2165case rv_rm_rdn:2166append(buf, "rdn", buflen);2167break;2168case rv_rm_rup:2169append(buf, "rup", buflen);2170break;2171case rv_rm_rmm:2172append(buf, "rmm", buflen);2173break;2174case rv_rm_dyn:2175append(buf, "dyn", buflen);2176break;2177default:2178append(buf, "inv", buflen);2179break;2180}2181break;2182case 'p':2183if (dec->pred & rv_fence_i) {2184append(buf, "i", buflen);2185}2186if (dec->pred & rv_fence_o) {2187append(buf, "o", buflen);2188}2189if (dec->pred & rv_fence_r) {2190append(buf, "r", buflen);2191}2192if (dec->pred & rv_fence_w) {2193append(buf, "w", buflen);2194}2195break;2196case 's':2197if (dec->succ & rv_fence_i) {2198append(buf, "i", buflen);2199}2200if (dec->succ & rv_fence_o) {2201append(buf, "o", buflen);2202}2203if (dec->succ & rv_fence_r) {2204append(buf, "r", buflen);2205}2206if (dec->succ & rv_fence_w) {2207append(buf, "w", buflen);2208}2209break;2210case '\t':2211while (strlen(buf) < tab) {2212append(buf, " ", buflen);2213}2214break;2215case 'A':2216if (dec->aq) {2217append(buf, ".aq", buflen);2218}2219break;2220case 'R':2221if (dec->rl) {2222append(buf, ".rl", buflen);2223}2224break;2225default:2226break;2227}2228fmt++;2229}2230}22312232/* instruction length */22332234size_t inst_length(rv_inst inst)2235{2236/* NOTE: supports maximum instruction size of 64-bits */22372238/* instruction length coding2239*2240* aa - 16 bit aa != 112241* bbb11 - 32 bit bbb != 1112242* 011111 - 48 bit2243* 0111111 - 64 bit2244*/22452246return (inst & 0b11) != 0b11 ? 22247: (inst & 0b11100) != 0b11100 ? 42248: (inst & 0b111111) == 0b011111 ? 62249: (inst & 0b1111111) == 0b0111111 ? 82250: 0;2251}22522253/* instruction fetch */22542255void inst_fetch(const uint8_t *data, rv_inst *instp, size_t *length)2256{2257rv_inst inst = ((rv_inst)data[1] << 8) | ((rv_inst)data[0]);2258size_t len = *length = inst_length(inst);2259if (len >= 8) inst |= ((rv_inst)data[7] << 56) | ((rv_inst)data[6] << 48);2260if (len >= 6) inst |= ((rv_inst)data[5] << 40) | ((rv_inst)data[4] << 32);2261if (len >= 4) inst |= ((rv_inst)data[3] << 24) | ((rv_inst)data[2] << 16);2262*instp = inst;2263}22642265/* disassemble instruction */22662267void disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst)2268{2269rv_decode dec = { .pc = pc, .inst = inst };2270decode_inst_opcode(&dec, isa);2271decode_inst_operands(&dec);2272decode_inst_decompress(&dec, isa);2273decode_inst_lift_pseudo(&dec);2274decode_inst_format(buf, buflen, 32, &dec);2275}227622772278