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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

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%YAML 1.2

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---

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$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-sdramc.yaml#

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$schema: http://devicetree.org/meta-schemas/core.yaml#

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title: Microchip (Atmel) SDRAM / DDR Controller (RAMC / DDRAMC / UDDRC)

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maintainers:

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  - Nicolas Ferre <nicolas.ferre@microchip.com>

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  - Claudiu Beznea <claudiu.beznea@tuxon.dev>

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description:

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  The SDRAM/DDR Controller (often called RAMC or DDRAMC) in various

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  Atmel/Microchip ARM9 and Cortex-A5/A7 SoCs  manages external

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  SDRAM / DDR memory. It is typically exposed as a syscon node for

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  register access from other drivers (e.g. for initialization or mode

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  configuration). No interrupts or clocks are usually required in the

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  binding.

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properties:

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  compatible:

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    oneOf:

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      - items:

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          - const: atmel,at91rm9200-sdramc

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          - const: syscon

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      - items:

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          - const: microchip,sama7d65-uddrc

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          - const: microchip,sama7g5-uddrc

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      - enum:

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          - atmel,at91sam9260-sdramc

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          - atmel,at91sam9g45-ddramc

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          - atmel,sama5d3-ddramc

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          - microchip,sam9x60-ddramc

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          - microchip,sam9x7-ddramc

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          - microchip,sama7g5-uddrc

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  reg:

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    maxItems: 1

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  clocks:

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    minItems: 1

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    maxItems: 2

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  clock-names:

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    minItems: 1

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    items:

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      - const: ddrck

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      - const: mpddr

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required:

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  - compatible

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  - reg

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unevaluatedProperties: false

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examples:

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  - |

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    #include <dt-bindings/clock/at91.h>

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    ramc@ffffe400 {

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        compatible = "atmel,at91sam9g45-ddramc";

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        reg = <0xffffe400 0x200>;

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        clocks = <&pmc PMC_TYPE_SYSTEM 2>;

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        clock-names = "ddrck";

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    };

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...

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