Path: blob/master/Documentation/devicetree/bindings/ata/ahci-platform.yaml
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# SPDX-License-Identifier: GPL-2.01%YAML 1.22---3$id: http://devicetree.org/schemas/ata/ahci-platform.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: AHCI SATA Controller78description: |9SATA nodes are defined to describe on-chip Serial ATA controllers.10Each SATA controller should have its own node.1112It is possible, but not required, to represent each port as a sub-node.13It allows to enable each port independently when dealing with multiple14PHYs.1516maintainers:17- Hans de Goede <hdegoede@redhat.com>18- Jens Axboe <axboe@kernel.dk>1920select:21properties:22compatible:23contains:24enum:25- brcm,iproc-ahci26- cavium,octeon-7130-ahci27- hisilicon,hisi-ahci28- ibm,476gtr-ahci29- marvell,armada-3700-ahci30- marvell,armada-8k-ahci31- marvell,berlin2q-ahci32- qcom,apq8064-ahci33- qcom,ipq806x-ahci34- socionext,uniphier-pro4-ahci35- socionext,uniphier-pxs2-ahci36- socionext,uniphier-pxs3-ahci37required:38- compatible3940properties:41compatible:42oneOf:43- items:44- enum:45- brcm,iproc-ahci46- marvell,armada-8k-ahci47- marvell,berlin2-ahci48- marvell,berlin2q-ahci49- qcom,apq8064-ahci50- qcom,ipq806x-ahci51- socionext,uniphier-pro4-ahci52- socionext,uniphier-pxs2-ahci53- socionext,uniphier-pxs3-ahci54- const: generic-ahci55- enum:56- cavium,octeon-7130-ahci57- hisilicon,hisi-ahci58- ibm,476gtr-ahci59- marvell,armada-3700-ahci6061reg:62minItems: 163maxItems: 26465reg-names:66maxItems: 16768clocks:69minItems: 170maxItems: 57172clock-names:73minItems: 174maxItems: 57576interrupts:77maxItems: 17879power-domains:80maxItems: 18182resets:83minItems: 184maxItems: 38586iommus:87maxItems: 18889patternProperties:90"^sata-port@[0-9a-f]+$":91$ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port9293anyOf:94- required: [ phys ]95- required: [ target-supply ]9697unevaluatedProperties: false9899required:100- compatible101- reg102- interrupts103104allOf:105- $ref: ahci-common.yaml#106107- if:108properties:109compatible:110contains:111enum:112- qcom,apq8064-ahci113- qcom,ipq806x-ahci114then:115properties:116clocks:117minItems: 5118clock-names:119items:120- const: slave_iface121- const: iface122- const: core123- const: rxoob124- const: pmalive125required:126- phys127- phy-names128- clocks129- clock-names130131- if:132properties:133compatible:134contains:135const: socionext,uniphier-pro4-ahci136then:137properties:138resets:139items:140- description: reset line for the parent141- description: reset line for the glue logic142- description: reset line for the controller143required:144- resets145else:146if:147properties:148compatible:149contains:150enum:151- socionext,uniphier-pxs2-ahci152- socionext,uniphier-pxs3-ahci153then:154properties:155resets:156items:157- description: reset for the glue logic158- description: reset for the controller159required:160- resets161else:162properties:163resets:164maxItems: 1165166unevaluatedProperties: false167168examples:169- |170sata@ffe08000 {171compatible = "snps,spear-ahci";172reg = <0xffe08000 0x1000>;173interrupts = <115>;174};175- |176#include <dt-bindings/interrupt-controller/arm-gic.h>177#include <dt-bindings/clock/berlin2q.h>178#include <dt-bindings/ata/ahci.h>179180sata@f7e90000 {181compatible = "marvell,berlin2q-ahci", "generic-ahci";182reg = <0xf7e90000 0x1000>;183interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;184clocks = <&chip CLKID_SATA>;185#address-cells = <1>;186#size-cells = <0>;187188hba-cap = <HBA_SMPS>;189190sata0: sata-port@0 {191reg = <0>;192193phys = <&sata_phy 0>;194target-supply = <®_sata0>;195196hba-port-cap = <(HBA_PORT_FBSCP | HBA_PORT_ESP)>;197};198199sata1: sata-port@1 {200reg = <1>;201202phys = <&sata_phy 1>;203target-supply = <®_sata1>;204205hba-port-cap = <(HBA_PORT_HPCP | HBA_PORT_MPSP | HBA_PORT_FBSCP)>;206};207};208209210