Path: blob/master/Documentation/devicetree/bindings/ata/allwinner,sun8i-r40-ahci.yaml
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# SPDX-License-Identifier: GPL-2.01%YAML 1.22---3$id: http://devicetree.org/schemas/ata/allwinner,sun8i-r40-ahci.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Allwinner R40 AHCI SATA Controller78maintainers:9- Chen-Yu Tsai <wens@csie.org>10- Maxime Ripard <mripard@kernel.org>1112properties:13compatible:14const: allwinner,sun8i-r40-ahci1516reg:17maxItems: 11819clocks:20items:21- description: AHCI Bus Clock22- description: AHCI Module Clock2324interrupts:25maxItems: 12627resets:28maxItems: 12930reset-names:31const: ahci3233ahci-supply:34description: Regulator for the AHCI controller3536phy-supply:37description: Regulator for the SATA PHY power3839required:40- compatible41- reg42- clocks43- interrupts44- resets45- reset-names4647additionalProperties: false4849examples:50- |51#include <dt-bindings/interrupt-controller/arm-gic.h>52#include <dt-bindings/clock/sun8i-r40-ccu.h>53#include <dt-bindings/reset/sun8i-r40-ccu.h>5455ahci: sata@1c18000 {56compatible = "allwinner,sun8i-r40-ahci";57reg = <0x01c18000 0x1000>;58interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;59clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;60resets = <&ccu RST_BUS_SATA>;61reset-names = "ahci";62ahci-supply = <®_dldo4>;63phy-supply = <®_eldo3>;64};6566...676869