Path: blob/master/Documentation/devicetree/bindings/ata/faraday,ftide010.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/ata/faraday,ftide010.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Faraday Technology FTIDE010 PATA controller78maintainers:9- Linus Walleij <linus.walleij@linaro.org>1011description: |12This controller is the first Faraday IDE interface block, used in the13StorLink SL3512 and SL3516, later known as the Cortina Systems Gemini14platform. The controller can do PIO modes 0 through 4, Multi-word DMA15(MWDM) modes 0 through 2 and Ultra DMA modes 0 through 6.1617On the Gemini platform, this PATA block is accompanied by a PATA to18SATA bridge in order to support SATA. This is why a phandle to that19controller is compulsory on that platform.2021The timing properties are unique per-SoC, not per-board.2223properties:24compatible:25oneOf:26- const: faraday,ftide01027- items:28- const: cortina,gemini-pata29- const: faraday,ftide0103031reg:32maxItems: 13334interrupts:35maxItems: 13637clocks:38minItems: 13940clock-names:41const: PCLK4243sata:44description:45phandle to the Gemini PATA to SATA bridge, if available46$ref: /schemas/types.yaml#/definitions/phandle4748required:49- compatible50- reg51- interrupts5253allOf:54- $ref: pata-common.yaml#5556- if:57properties:58compatible:59contains:60const: cortina,gemini-pata6162then:63required:64- sata6566unevaluatedProperties: false6768examples:69- |70#include <dt-bindings/interrupt-controller/irq.h>71#include <dt-bindings/clock/cortina,gemini-clock.h>7273ide@63000000 {74compatible = "cortina,gemini-pata", "faraday,ftide010";75reg = <0x63000000 0x100>;76interrupts = <4 IRQ_TYPE_EDGE_RISING>;77clocks = <&gcc GEMINI_CLK_GATE_IDE>;78clock-names = "PCLK";79sata = <&sata>;80#address-cells = <1>;81#size-cells = <0>;82ide-port@0 {83reg = <0>;84};85ide-port@1 {86reg = <1>;87};88};8990...919293