Path: blob/master/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Synopsys DWC AHCI SATA controller for Rockchip devices78maintainers:9- Serge Semin <fancer.lancer@gmail.com>1011description:12This document defines device tree bindings for the Synopsys DWC13implementation of the AHCI SATA controller found in Rockchip14devices.1516select:17properties:18compatible:19contains:20enum:21- rockchip,rk3568-dwc-ahci22- rockchip,rk3576-dwc-ahci23- rockchip,rk3588-dwc-ahci24required:25- compatible2627properties:28compatible:29items:30- enum:31- rockchip,rk3568-dwc-ahci32- rockchip,rk3576-dwc-ahci33- rockchip,rk3588-dwc-ahci34- const: snps,dwc-ahci3536ports-implemented:37const: 13839power-domains:40maxItems: 14142sata-port@0:43$ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port4445properties:46reg:47const: 04849unevaluatedProperties: false5051patternProperties:52"^sata-port@[1-9a-e]$": false5354required:55- compatible56- reg57- interrupts58- clocks59- clock-names60- ports-implemented6162allOf:63- $ref: snps,dwc-ahci-common.yaml#64- if:65properties:66compatible:67contains:68enum:69- rockchip,rk3588-dwc-ahci70then:71properties:72clocks:73maxItems: 574clock-names:75items:76- const: sata77- const: pmalive78- const: rxoob79- const: ref80- const: asic81- if:82properties:83compatible:84contains:85enum:86- rockchip,rk3568-dwc-ahci87- rockchip,rk3576-dwc-ahci88then:89properties:90clocks:91maxItems: 392clock-names:93items:94- const: sata95- const: pmalive96- const: rxoob9798unevaluatedProperties: false99100examples:101- |102#include <dt-bindings/clock/rockchip,rk3588-cru.h>103#include <dt-bindings/interrupt-controller/arm-gic.h>104#include <dt-bindings/ata/ahci.h>105#include <dt-bindings/phy/phy.h>106107sata@fe210000 {108compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";109reg = <0xfe210000 0x1000>;110clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,111<&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,112<&cru CLK_PIPEPHY0_PIPE_ASIC_G>;113clock-names = "sata", "pmalive", "rxoob", "ref", "asic";114interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;115ports-implemented = <0x1>;116#address-cells = <1>;117#size-cells = <0>;118119sata-port@0 {120reg = <0>;121hba-port-cap = <HBA_PORT_FBSCP>;122phys = <&combphy0_ps PHY_TYPE_SATA>;123phy-names = "sata-phy";124snps,rx-ts-max = <32>;125snps,tx-ts-max = <32>;126};127};128129...130131132