Path: blob/master/Documentation/devicetree/bindings/ata/sata_highbank.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/ata/sata_highbank.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Calxeda AHCI SATA Controller78description: |9The Calxeda SATA controller mostly conforms to the AHCI interface10with some special extensions to add functionality, to map GPIOs for11activity LEDs and for mapping the ComboPHYs.1213maintainers:14- Andre Przywara <andre.przywara@arm.com>1516properties:17compatible:18const: calxeda,hb-ahci1920reg:21maxItems: 12223interrupts:24maxItems: 12526dma-coherent: true2728calxeda,pre-clocks:29$ref: /schemas/types.yaml#/definitions/uint3230description: |31Indicates the number of additional clock cycles to transmit before32sending an SGPIO pattern.3334calxeda,post-clocks:35$ref: /schemas/types.yaml#/definitions/uint3236description: |37Indicates the number of additional clock cycles to transmit after38sending an SGPIO pattern.3940calxeda,led-order:41description: Maps port numbers to offsets within the SGPIO bitstream.42$ref: /schemas/types.yaml#/definitions/uint32-array43minItems: 144maxItems: 84546calxeda,port-phys:47description: |48phandle-combophy and lane assignment, which maps each SATA port to a49combophy and a lane within that combophy50$ref: /schemas/types.yaml#/definitions/phandle-array51minItems: 152maxItems: 853items:54maxItems: 25556calxeda,tx-atten:57description: |58Contains TX attenuation override codes, one per port.59The upper 24 bits of each entry are always 0 and thus ignored.60$ref: /schemas/types.yaml#/definitions/uint32-array61minItems: 162maxItems: 86364calxeda,sgpio-gpio:65maxItems: 366description: |67phandle-gpio bank, bit offset, and default on or off, which indicates68that the driver supports SGPIO indicator lights using the indicated69GPIOs.7071required:72- compatible73- reg74- interrupts7576additionalProperties: false7778examples:79- |80sata@ffe08000 {81compatible = "calxeda,hb-ahci";82reg = <0xffe08000 0x1000>;83interrupts = <115>;84dma-coherent;85calxeda,port-phys = <&combophy5 0>, <&combophy0 0>, <&combophy0 1>,86<&combophy0 2>, <&combophy0 3>;87calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, <&gpioh 7 1>;88calxeda,led-order = <4 0 1 2 3>;89calxeda,tx-atten = <0xff 22 0xff 0xff 23>;90calxeda,pre-clocks = <10>;91calxeda,post-clocks = <0>;92};9394...959697