Path: blob/master/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Synopsys DWC AHCI SATA controller78maintainers:9- Serge Semin <fancer.lancer@gmail.com>1011description:12This document defines device tree bindings for the generic Synopsys DWC13implementation of the AHCI SATA controller.1415select:16properties:17compatible:18enum:19- snps,dwc-ahci20- snps,spear-ahci21required:22- compatible2324allOf:25- $ref: snps,dwc-ahci-common.yaml#2627properties:28compatible:29oneOf:30- description: Synopsys AHCI SATA-compatible devices31const: snps,dwc-ahci32- description: SPEAr1340 AHCI SATA device33const: snps,spear-ahci3435patternProperties:36"^sata-port@[0-9a-e]$":37$ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port3839unevaluatedProperties: false4041required:42- compatible43- reg44- interrupts4546unevaluatedProperties: false4748examples:49- |50#include <dt-bindings/interrupt-controller/arm-gic.h>51#include <dt-bindings/ata/ahci.h>5253sata@122f0000 {54compatible = "snps,dwc-ahci";55reg = <0x122F0000 0x1ff>;56#address-cells = <1>;57#size-cells = <0>;5859interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;6061clocks = <&clock1>, <&clock2>;62clock-names = "aclk", "ref";6364phys = <&sata_phy>;65phy-names = "sata-phy";6667ports-implemented = <0x1>;6869sata-port@0 {70reg = <0>;7172hba-port-cap = <HBA_PORT_FBSCP>;7374snps,tx-ts-max = <512>;75snps,rx-ts-max = <512>;76};77};7879...808182