Path: blob/master/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/bus/brcm,gisb-arb.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Broadcom GISB bus Arbiter controller78maintainers:9- Florian Fainelli <f.fainelli@gmail.com>1011properties:12compatible:13oneOf:14- items:15- enum:16- brcm,bcm7445-gisb-arb # for other 28nm chips17- const: brcm,gisb-arb18- items:19- enum:20- brcm,bcm74165-gisb-arb # for V7 new style 16nm chips21- brcm,bcm7278-gisb-arb # for V7 28nm chips22- brcm,bcm7435-gisb-arb # for newer 40nm chips23- brcm,bcm7400-gisb-arb # for older 40nm chips and all 65nm chips24- brcm,bcm7038-gisb-arb # for 130nm chips25- brcm,gisb-arb # fallback compatible2627reg:28maxItems: 12930interrupts:31minItems: 232items:33- description: timeout interrupt line34- description: target abort interrupt line35- description: breakpoint interrupt line3637brcm,gisb-arb-master-mask:38$ref: /schemas/types.yaml#/definitions/uint3239description: >4032-bits wide bitmask used to specify which GISB masters are valid at the41system level4243brcm,gisb-arb-master-names:44$ref: /schemas/types.yaml#/definitions/string-array45description: >46String list of the literal name of the GISB masters. Should match the47number of bits set in brcm,gisb-master-mask and the order in which they48appear from MSB to LSB.4950required:51- compatible52- reg53- interrupts5455additionalProperties: false5657examples:58- |59gisb-arb@f0400000 {60compatible = "brcm,gisb-arb";61reg = <0xf0400000 0x800>;62interrupts = <0>, <2>;63interrupt-parent = <&sun_l2_intc>;64brcm,gisb-arb-master-mask = <0x7>;65brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";66};676869