Path: blob/master/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/bus/nvidia,tegra210-aconnect.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: NVIDIA Tegra ACONNECT Bus78description: |9The Tegra ACONNECT bus is an AXI switch which is used to connect various10components inside the Audio Processing Engine (APE). All CPU accesses to11the APE subsystem go through the ACONNECT via an APB to AXI wrapper. All12devices accessed via the ACONNECT are described by child-nodes.1314maintainers:15- Jon Hunter <jonathanh@nvidia.com>1617properties:18compatible:19oneOf:20- const: nvidia,tegra210-aconnect21- items:22- enum:23- nvidia,tegra264-aconnect24- nvidia,tegra234-aconnect25- nvidia,tegra186-aconnect26- nvidia,tegra194-aconnect27- const: nvidia,tegra210-aconnect2829clocks:30items:31- description: Must contain the entry for APE clock32- description: Must contain the entry for APE interface clock3334clock-names:35items:36- const: ape37- const: apb2ape3839power-domains:40maxItems: 14142"#address-cells":43enum: [ 1, 2 ]4445"#size-cells":46enum: [ 1, 2 ]4748ranges: true4950patternProperties:51"@[0-9a-f]+$":52type: object5354required:55- compatible56- clocks57- clock-names58- power-domains59- "#address-cells"60- "#size-cells"61- ranges6263additionalProperties: false6465examples:66- |67#include<dt-bindings/clock/tegra210-car.h>6869aconnect@702c0000 {70compatible = "nvidia,tegra210-aconnect";71clocks = <&tegra_car TEGRA210_CLK_APE>,72<&tegra_car TEGRA210_CLK_APB2APE>;73clock-names = "ape", "apb2ape";74power-domains = <&pd_audio>;7576#address-cells = <1>;77#size-cells = <1>;78ranges = <0x702c0000 0x702c0000 0x00040000>;7980// Child device nodes follow ...81};8283...848586