Path: blob/master/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml
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# SPDX-License-Identifier: GPL-2.01%YAML 1.22---3$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Allwinner A10 TCON Channel 0 Clock78maintainers:9- Chen-Yu Tsai <wens@csie.org>10- Maxime Ripard <mripard@kernel.org>1112deprecated: true1314properties:15"#clock-cells":16const: 01718"#reset-cells":19const: 12021compatible:22enum:23- allwinner,sun4i-a10-tcon-ch0-clk24- allwinner,sun4i-a10-tcon-ch1-clk2526reg:27maxItems: 12829clocks:30maxItems: 431description: >32The parent order must match the hardware programming order.3334clock-output-names:35maxItems: 13637required:38- "#clock-cells"39- compatible40- reg41- clocks42- clock-output-names4344if:45properties:46compatible:47contains:48const: allwinner,sun4i-a10-tcon-ch0-clk4950then:51required:52- "#reset-cells"5354additionalProperties: false5556examples:57- |58clk@1c20118 {59#clock-cells = <0>;60#reset-cells = <1>;61compatible = "allwinner,sun4i-a10-tcon-ch0-clk";62reg = <0x01c20118 0x4>;63clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;64clock-output-names = "tcon-ch0-sclk";65};6667- |68clk@1c2012c {69#clock-cells = <0>;70compatible = "allwinner,sun4i-a10-tcon-ch1-clk";71reg = <0x01c2012c 0x4>;72clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;73clock-output-names = "tcon-ch1-sclk";74};7576...777879