Path: blob/master/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml
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# SPDX-License-Identifier: GPL-2.0+1%YAML 1.22---3$id: http://devicetree.org/schemas/clock/allwinner,sun8i-a83t-de2-clk.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Allwinner A83t Display Engine 2/3 Clock Controller78maintainers:9- Chen-Yu Tsai <wens@csie.org>10- Maxime Ripard <mripard@kernel.org>1112properties:13"#clock-cells":14const: 11516"#reset-cells":17const: 11819compatible:20oneOf:21- const: allwinner,sun8i-a83t-de2-clk22- const: allwinner,sun8i-h3-de2-clk23- const: allwinner,sun8i-v3s-de2-clk24- const: allwinner,sun50i-a64-de2-clk25- const: allwinner,sun50i-h5-de2-clk26- const: allwinner,sun50i-h6-de3-clk27- const: allwinner,sun50i-h616-de33-clk28- items:29- const: allwinner,sun8i-r40-de2-clk30- const: allwinner,sun8i-h3-de2-clk31- items:32- const: allwinner,sun20i-d1-de2-clk33- const: allwinner,sun50i-h5-de2-clk3435reg:36maxItems: 13738clocks:39items:40- description: Bus Clock41- description: Module Clock4243clock-names:44items:45- const: bus46- const: mod4748resets:49maxItems: 15051required:52- "#clock-cells"53- "#reset-cells"54- compatible55- reg56- clocks57- clock-names58- resets5960additionalProperties: false6162examples:63- |64#include <dt-bindings/clock/sun8i-h3-ccu.h>65#include <dt-bindings/reset/sun8i-h3-ccu.h>6667de2_clocks: clock@1000000 {68compatible = "allwinner,sun8i-h3-de2-clk";69reg = <0x01000000 0x100000>;70clocks = <&ccu CLK_BUS_DE>,71<&ccu CLK_DE>;72clock-names = "bus",73"mod";74resets = <&ccu RST_BUS_DE>;75#clock-cells = <1>;76#reset-cells = <1>;77};7879...808182