Path: blob/master/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-de-clks.yaml
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# SPDX-License-Identifier: GPL-2.0+1%YAML 1.22---3$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-de-clks.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Allwinner A80 Display Engine Clock Controller78maintainers:9- Chen-Yu Tsai <wens@csie.org>10- Maxime Ripard <mripard@kernel.org>1112properties:13"#clock-cells":14const: 11516"#reset-cells":17const: 11819compatible:20const: allwinner,sun9i-a80-de-clks2122reg:23maxItems: 12425clocks:26items:27- description: Bus Clock28- description: RAM Bus Clock29- description: Module Clock3031clock-names:32items:33- const: mod34- const: dram35- const: bus3637resets:38maxItems: 13940required:41- "#clock-cells"42- "#reset-cells"43- compatible44- reg45- clocks46- clock-names47- resets4849additionalProperties: false5051examples:52- |53#include <dt-bindings/clock/sun9i-a80-ccu.h>54#include <dt-bindings/reset/sun9i-a80-ccu.h>5556de_clocks: clock@3000000 {57compatible = "allwinner,sun9i-a80-de-clks";58reg = <0x03000000 0x30>;59clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;60clock-names = "mod", "dram", "bus";61resets = <&ccu RST_BUS_DE>;62#clock-cells = <1>;63#reset-cells = <1>;64};6566...676869