Path: blob/master/Documentation/devicetree/bindings/clock/amlogic,c3-peripherals-clkc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/amlogic,c3-peripherals-clkc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#67title: Amlogic C3 series Peripheral Clock Controller89maintainers:10- Neil Armstrong <neil.armstrong@linaro.org>11- Jerome Brunet <jbrunet@baylibre.com>12- Xianwei Zhao <xianwei.zhao@amlogic.com>13- Chuan Liu <chuan.liu@amlogic.com>1415properties:16compatible:17const: amlogic,c3-peripherals-clkc1819reg:20maxItems: 12122clocks:23minItems: 1624items:25- description: input oscillator (usually at 24MHz)26- description: input oscillators multiplexer27- description: input fix pll28- description: input fclk div 229- description: input fclk div 2p530- description: input fclk div 331- description: input fclk div 432- description: input fclk div 533- description: input fclk div 734- description: input gp0 pll35- description: input gp1 pll36- description: input hifi pll37- description: input sys clk38- description: input axi clk39- description: input sys pll div 1640- description: input cpu clk div 1641- description: input pad clock for rtc clk (optional)4243clock-names:44minItems: 1645items:46- const: xtal_24m47- const: oscin48- const: fix49- const: fdiv250- const: fdiv2p551- const: fdiv352- const: fdiv453- const: fdiv554- const: fdiv755- const: gp056- const: gp157- const: hifi58- const: sysclk59- const: axiclk60- const: sysplldiv1661- const: cpudiv1662- const: pad_osc6364"#clock-cells":65const: 16667required:68- compatible69- reg70- clocks71- clock-names72- "#clock-cells"7374additionalProperties: false7576examples:77- |78apb {79#address-cells = <2>;80#size-cells = <2>;8182clock-controller@0 {83compatible = "amlogic,c3-peripherals-clkc";84reg = <0x0 0x0 0x0 0x49c>;85#clock-cells = <1>;86clocks = <&xtal_24m>,87<&scmi_clk 8>,88<&scmi_clk 12>,89<&clkc_pll 3>,90<&clkc_pll 5>,91<&clkc_pll 7>,92<&clkc_pll 9>,93<&clkc_pll 11>,94<&clkc_pll 13>,95<&clkc_pll 15>,96<&scmi_clk 13>,97<&clkc_pll 17>,98<&scmi_clk 9>,99<&scmi_clk 10>,100<&scmi_clk 14>,101<&scmi_clk 15>;102clock-names = "xtal_24m",103"oscin",104"fix",105"fdiv2",106"fdiv2p5",107"fdiv3",108"fdiv4",109"fdiv5",110"fdiv7",111"gp0",112"gp1",113"hifi",114"sysclk",115"axiclk",116"sysplldiv16",117"cpudiv16";118};119};120121122