Book a Demo!
CoCalc Logo Icon
StoreFeaturesDocsShareSupportNewsAboutPoliciesSign UpSign In
torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml
26308 views
1
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

2
%YAML 1.2

3
---

4
$id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#

5
$schema: http://devicetree.org/meta-schemas/core.yaml#

6


7
title: Apple SoC cluster cpufreq device

8


9
maintainers:

10
  - Hector Martin <marcan@marcan.st>

11


12
description: |

13
  Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of

14
  the cluster management register block. This binding uses the standard

15
  operating-points-v2 table to define the CPU performance states, with the

16
  opp-level property specifying the hardware p-state index for that level.

17


18
properties:

19
  compatible:

20
    oneOf:

21
      - items:

22
          - enum:

23
              - apple,t8103-cluster-cpufreq

24
              - apple,t8112-cluster-cpufreq

25
          - const: apple,cluster-cpufreq

26
      - items:

27
          - enum:

28
              - apple,s8000-cluster-cpufreq

29
              - apple,t8010-cluster-cpufreq

30
              - apple,t8015-cluster-cpufreq

31
              - apple,t6000-cluster-cpufreq

32
          - const: apple,t8103-cluster-cpufreq

33
          - const: apple,cluster-cpufreq

34
      - items:

35
          - const: apple,t7000-cluster-cpufreq

36
          - const: apple,s5l8960x-cluster-cpufreq

37
      - const: apple,s5l8960x-cluster-cpufreq

38


39
  reg:

40
    maxItems: 1

41


42
  '#performance-domain-cells':

43
    const: 0

44


45
required:

46
  - compatible

47
  - reg

48
  - '#performance-domain-cells'

49


50
additionalProperties: false

51


52
examples:

53
  - |

54
    // This example shows a single CPU per domain and 2 domains,

55
    // with two p-states per domain.

56
    // Shipping hardware has 2-4 CPUs per domain and 2-6 domains.

57
    cpus {

58
      #address-cells = <2>;

59
      #size-cells = <0>;

60


61
      cpu@0 {

62
        compatible = "apple,icestorm";

63
        device_type = "cpu";

64
        reg = <0x0 0x0>;

65
        operating-points-v2 = <&ecluster_opp>;

66
        performance-domains = <&cpufreq_e>;

67
      };

68


69
      cpu@10100 {

70
        compatible = "apple,firestorm";

71
        device_type = "cpu";

72
        reg = <0x0 0x10100>;

73
        operating-points-v2 = <&pcluster_opp>;

74
        performance-domains = <&cpufreq_p>;

75
      };

76
    };

77


78
    ecluster_opp: opp-table-0 {

79
      compatible = "operating-points-v2";

80
      opp-shared;

81


82
      opp01 {

83
        opp-hz = /bits/ 64 <600000000>;

84
        opp-level = <1>;

85
        clock-latency-ns = <7500>;

86
      };

87
      opp02 {

88
        opp-hz = /bits/ 64 <972000000>;

89
        opp-level = <2>;

90
        clock-latency-ns = <22000>;

91
      };

92
    };

93


94
    pcluster_opp: opp-table-1 {

95
      compatible = "operating-points-v2";

96
      opp-shared;

97


98
      opp01 {

99
        opp-hz = /bits/ 64 <600000000>;

100
        opp-level = <1>;

101
        clock-latency-ns = <8000>;

102
      };

103
      opp02 {

104
        opp-hz = /bits/ 64 <828000000>;

105
        opp-level = <2>;

106
        clock-latency-ns = <19000>;

107
      };

108
    };

109


110
    soc {

111
      #address-cells = <2>;

112
      #size-cells = <2>;

113


114
      cpufreq_e: performance-controller@210e20000 {

115
        compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";

116
        reg = <0x2 0x10e20000 0 0x1000>;

117
        #performance-domain-cells = <0>;

118
      };

119


120
      cpufreq_p: performance-controller@211e20000 {

121
        compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";

122
        reg = <0x2 0x11e20000 0 0x1000>;

123
        #performance-domain-cells = <0>;

124
      };

125
    };

126


127