Path: blob/master/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: MediaTek's CPUFREQ78maintainers:9- Hector Yuan <hector.yuan@mediatek.com>1011description:12CPUFREQ HW is a hardware engine used by MediaTek SoCs to13manage frequency in hardware. It is capable of controlling14frequency for multiple clusters.1516properties:17compatible:18const: mediatek,cpufreq-hw1920reg:21minItems: 122maxItems: 223description:24Addresses and sizes for the memory of the HW bases in25each frequency domain. Each entry corresponds to26a register bank for each frequency domain present.2728"#performance-domain-cells":29description:30Number of cells in a performance domain specifier.31Set const to 1 here for nodes providing multiple32performance domains.33const: 13435required:36- compatible37- reg38- "#performance-domain-cells"3940additionalProperties: false4142examples:43- |44cpus {45#address-cells = <1>;46#size-cells = <0>;4748cpu0: cpu@0 {49device_type = "cpu";50compatible = "arm,cortex-a55";51enable-method = "psci";52performance-domains = <&performance 0>;53reg = <0x000>;54};55};5657/* ... */5859soc {60#address-cells = <2>;61#size-cells = <2>;6263performance: performance-controller@11bc00 {64compatible = "mediatek,cpufreq-hw";65reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;6667#performance-domain-cells = <1>;68};69};707172