Path: blob/master/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries2%YAML 1.23---4$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-aes.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#67title: Atmel Advanced Encryption Standard (AES) HW cryptographic accelerator89maintainers:10- Tudor Ambarus <tudor.ambarus@linaro.org>1112properties:13compatible:14oneOf:15- const: atmel,at91sam9g46-aes16- items:17- enum:18- microchip,sam9x7-aes19- microchip,sama7d65-aes20- const: atmel,at91sam9g46-aes2122reg:23maxItems: 12425interrupts:26maxItems: 12728clocks:29maxItems: 13031clock-names:32const: aes_clk3334dmas:35items:36- description: TX DMA Channel37- description: RX DMA Channel3839dma-names:40items:41- const: tx42- const: rx4344required:45- compatible46- reg47- interrupts48- clocks49- clock-names50- dmas51- dma-names5253additionalProperties: false5455examples:56- |57#include <dt-bindings/interrupt-controller/irq.h>58#include <dt-bindings/interrupt-controller/arm-gic.h>59#include <dt-bindings/clock/at91.h>60#include <dt-bindings/dma/at91.h>6162aes: crypto@e1810000 {63compatible = "atmel,at91sam9g46-aes";64reg = <0xe1810000 0x100>;65interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;66clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;67clock-names = "aes_clk";68dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,69<&dma0 AT91_XDMAC_DT_PERID(2)>;70dma-names = "tx", "rx";71};727374