Path: blob/master/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries2%YAML 1.23---4$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-sha.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#67title: Atmel Secure Hash Algorithm (SHA) HW cryptographic accelerator89maintainers:10- Tudor Ambarus <tudor.ambarus@linaro.org>1112properties:13compatible:14oneOf:15- const: atmel,at91sam9g46-sha16- items:17- enum:18- microchip,lan9691-sha19- microchip,sam9x7-sha20- microchip,sama7d65-sha21- const: atmel,at91sam9g46-sha2223reg:24maxItems: 12526interrupts:27maxItems: 12829clocks:30maxItems: 13132clock-names:33const: sha_clk3435dmas:36maxItems: 137description: TX DMA Channel3839dma-names:40const: tx4142required:43- compatible44- reg45- interrupts46- clocks47- clock-names4849additionalProperties: false5051examples:52- |53#include <dt-bindings/interrupt-controller/irq.h>54#include <dt-bindings/interrupt-controller/arm-gic.h>55#include <dt-bindings/clock/at91.h>56#include <dt-bindings/dma/at91.h>5758sha: crypto@e1814000 {59compatible = "atmel,at91sam9g46-sha";60reg = <0xe1814000 0x100>;61interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;62clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;63clock-names = "sha_clk";64dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;65dma-names = "tx";66};676869