Path: blob/master/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries2%YAML 1.23---4$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-sha.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#67title: Atmel Secure Hash Algorithm (SHA) HW cryptographic accelerator89maintainers:10- Tudor Ambarus <tudor.ambarus@linaro.org>1112properties:13compatible:14oneOf:15- const: atmel,at91sam9g46-sha16- items:17- enum:18- microchip,sam9x7-sha19- microchip,sama7d65-sha20- const: atmel,at91sam9g46-sha2122reg:23maxItems: 12425interrupts:26maxItems: 12728clocks:29maxItems: 13031clock-names:32const: sha_clk3334dmas:35maxItems: 136description: TX DMA Channel3738dma-names:39const: tx4041required:42- compatible43- reg44- interrupts45- clocks46- clock-names4748additionalProperties: false4950examples:51- |52#include <dt-bindings/interrupt-controller/irq.h>53#include <dt-bindings/interrupt-controller/arm-gic.h>54#include <dt-bindings/clock/at91.h>55#include <dt-bindings/dma/at91.h>5657sha: crypto@e1814000 {58compatible = "atmel,at91sam9g46-sha";59reg = <0xe1814000 0x100>;60interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;61clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;62clock-names = "sha_clk";63dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;64dma-names = "tx";65};666768