Path: blob/master/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Qualcomm crypto engine driver78maintainers:9- Bjorn Andersson <andersson@kernel.org>10- Konrad Dybcio <konradybcio@kernel.org>1112description:13This document defines the binding for the QCE crypto14controller found on Qualcomm parts.1516properties:17compatible:18oneOf:19- const: qcom,crypto-v5.120deprecated: true21description: Kept only for ABI backward compatibility2223- const: qcom,crypto-v5.424deprecated: true25description: Kept only for ABI backward compatibility2627- items:28- enum:29- qcom,ipq4019-qce30- qcom,sm8150-qce31- const: qcom,qce3233- items:34- enum:35- qcom,ipq6018-qce36- qcom,ipq8074-qce37- qcom,ipq9574-qce38- qcom,msm8996-qce39- qcom,qcm2290-qce40- qcom,sdm845-qce41- qcom,sm6115-qce42- const: qcom,ipq4019-qce43- const: qcom,qce4445- items:46- enum:47- qcom,qcs615-qce48- qcom,qcs8300-qce49- qcom,sa8775p-qce50- qcom,sc7280-qce51- qcom,sm6350-qce52- qcom,sm8250-qce53- qcom,sm8350-qce54- qcom,sm8450-qce55- qcom,sm8550-qce56- qcom,sm8650-qce57- qcom,sm8750-qce58- qcom,x1e80100-qce59- const: qcom,sm8150-qce60- const: qcom,qce6162reg:63maxItems: 16465clocks:66minItems: 167maxItems: 36869clock-names:70minItems: 171maxItems: 37273iommus:74minItems: 175maxItems: 876description:77phandle to apps_smmu node with sid mask.7879interconnects:80maxItems: 181description:82Interconnect path between qce crypto and main memory.8384interconnect-names:85const: memory8687dmas:88items:89- description: DMA specifiers for rx dma channel.90- description: DMA specifiers for tx dma channel.9192dma-names:93items:94- const: rx95- const: tx9697allOf:98- if:99properties:100compatible:101contains:102enum:103- qcom,crypto-v5.1104- qcom,crypto-v5.4105- qcom,ipq6018-qce106- qcom,ipq8074-qce107- qcom,ipq9574-qce108- qcom,msm8996-qce109- qcom,sdm845-qce110then:111properties:112clocks:113maxItems: 3114clock-names:115items:116- const: iface117- const: bus118- const: core119required:120- clocks121- clock-names122123- if:124properties:125compatible:126contains:127enum:128- qcom,qcm2290-qce129- qcom,sm6115-qce130then:131properties:132clocks:133maxItems: 1134clock-names:135items:136- const: core137required:138- clocks139- clock-names140141- if:142properties:143compatible:144contains:145enum:146- qcom,sm8150-qce147then:148properties:149clocks: false150clock-names: false151152required:153- compatible154- reg155- dmas156- dma-names157158additionalProperties: false159160examples:161- |162#include <dt-bindings/clock/qcom,gcc-apq8084.h>163crypto-engine@fd45a000 {164compatible = "qcom,ipq6018-qce", "qcom,ipq4019-qce", "qcom,qce";165reg = <0xfd45a000 0x6000>;166clocks = <&gcc GCC_CE2_AHB_CLK>,167<&gcc GCC_CE2_AXI_CLK>,168<&gcc GCC_CE2_CLK>;169clock-names = "iface", "bus", "core";170dmas = <&cryptobam 2>, <&cryptobam 3>;171dma-names = "rx", "tx";172iommus = <&apps_smmu 0x584 0x0011>,173<&apps_smmu 0x586 0x0011>,174<&apps_smmu 0x594 0x0011>,175<&apps_smmu 0x596 0x0011>;176};177178179