Path: blob/master/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/devfreq/event/rockchip,dfi.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Rockchip DFI78maintainers:9- Sascha Hauer <s.hauer@pengutronix.de>1011properties:12compatible:13enum:14- rockchip,rk3399-dfi15- rockchip,rk3568-dfi16- rockchip,rk3588-dfi1718clocks:19maxItems: 12021clock-names:22items:23- const: pclk_ddr_mon2425interrupts:26minItems: 127maxItems: 42829reg:30maxItems: 13132rockchip,pmu:33$ref: /schemas/types.yaml#/definitions/phandle34description:35Phandle to the syscon managing the "PMU general register files".3637required:38- compatible39- interrupts40- reg4142if:43properties:44compatible:45contains:46enum:47- rockchip,rk3399-dfi4849then:50required:51- clocks52- clock-names5354additionalProperties: false5556examples:57- |58#include <dt-bindings/interrupt-controller/arm-gic.h>59#include <dt-bindings/clock/rk3308-cru.h>6061bus {62#address-cells = <2>;63#size-cells = <2>;6465dfi: dfi@ff630000 {66compatible = "rockchip,rk3399-dfi";67reg = <0x00 0xff630000 0x00 0x4000>;68interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;69rockchip,pmu = <&pmugrf>;70clocks = <&cru PCLK_DDR_MON>;71clock-names = "pclk_ddr_mon";72};73};747576