Path: blob/master/Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml
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# SPDX-License-Identifier: GPL-2.01%YAML 1.22---3$id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-ppmu.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Samsung Exynos SoC PPMU (Platform Performance Monitoring Unit)78maintainers:9- Chanwoo Choi <cw00.choi@samsung.com>10- Krzysztof Kozlowski <krzk@kernel.org>1112description: |13The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for14each IP. PPMU provides the primitive values to get performance data. These15PPMU events provide information of the SoC's behaviors so that you may use to16analyze system performance, to make behaviors visible and to count usages of17each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC). The18Exynos PPMU driver uses the devfreq-event class to provide event data to19various devfreq devices. The devfreq devices would use the event data when20determining the current state of each IP.2122properties:23compatible:24enum:25- samsung,exynos-ppmu26- samsung,exynos-ppmu-v22728clock-names:29items:30- const: ppmu3132clocks:33maxItems: 13435reg:36maxItems: 13738events:39type: object4041patternProperties:42'^ppmu-event[0-9]+(-[a-z0-9]+){,2}$':43type: object44properties:45event-name:46description: |47The unique event name among PPMU device48$ref: /schemas/types.yaml#/definitions/string4950event-data-type:51description: |52Define the type of data which shell be counted by the counter.53You can check include/dt-bindings/pmu/exynos_ppmu.h for all54possible type, i.e. count read requests, count write data in55bytes, etc. This field is optional and when it is missing, the56driver code will use default data type.57$ref: /schemas/types.yaml#/definitions/uint325859required:60- event-name6162additionalProperties: false6364additionalProperties: false6566required:67- compatible68- reg6970additionalProperties: false7172examples:73- |74// PPMUv1 nodes for Exynos3250 (although the board DTS defines events)75#include <dt-bindings/clock/exynos3250.h>7677ppmu_dmc0: ppmu@106a0000 {78compatible = "samsung,exynos-ppmu";79reg = <0x106a0000 0x2000>;8081events {82ppmu_dmc0_3: ppmu-event3-dmc0 {83event-name = "ppmu-event3-dmc0";84};8586ppmu_dmc0_2: ppmu-event2-dmc0 {87event-name = "ppmu-event2-dmc0";88};8990ppmu_dmc0_1: ppmu-event1-dmc0 {91event-name = "ppmu-event1-dmc0";92};9394ppmu_dmc0_0: ppmu-event0-dmc0 {95event-name = "ppmu-event0-dmc0";96};97};98};99100ppmu_rightbus: ppmu@112a0000 {101compatible = "samsung,exynos-ppmu";102reg = <0x112a0000 0x2000>;103clocks = <&cmu CLK_PPMURIGHT>;104clock-names = "ppmu";105106events {107ppmu_rightbus_3: ppmu-event3-rightbus {108event-name = "ppmu-event3-rightbus";109};110};111};112113- |114// PPMUv2 nodes in Exynos5433115ppmu_d0_cpu: ppmu@10480000 {116compatible = "samsung,exynos-ppmu-v2";117reg = <0x10480000 0x2000>;118};119120ppmu_d0_general: ppmu@10490000 {121compatible = "samsung,exynos-ppmu-v2";122reg = <0x10490000 0x2000>;123124events {125ppmu_event0_d0_general: ppmu-event0-d0-general {126event-name = "ppmu-event0-d0-general";127};128};129};130131ppmu_d0_rt: ppmu@104a0000 {132compatible = "samsung,exynos-ppmu-v2";133reg = <0x104a0000 0x2000>;134};135136ppmu_d1_cpu: ppmu@104b0000 {137compatible = "samsung,exynos-ppmu-v2";138reg = <0x104b0000 0x2000>;139};140141ppmu_d1_general: ppmu@104c0000 {142compatible = "samsung,exynos-ppmu-v2";143reg = <0x104c0000 0x2000>;144};145146ppmu_d1_rt: ppmu@104d0000 {147compatible = "samsung,exynos-ppmu-v2";148reg = <0x104d0000 0x2000>;149};150151- |152// PPMUv1 nodes with event-data-type for Exynos4412153#include <dt-bindings/pmu/exynos_ppmu.h>154155ppmu@106a0000 {156compatible = "samsung,exynos-ppmu";157reg = <0x106a0000 0x2000>;158clocks = <&clock 400>;159clock-names = "ppmu";160161events {162ppmu-event3-dmc0 {163event-name = "ppmu-event3-dmc0";164event-data-type = <(PPMU_RO_DATA_CNT |165PPMU_WO_DATA_CNT)>;166};167};168};169170171