Path: blob/master/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml
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# SPDX-License-Identifier: GPL-2.01%YAML 1.22---3$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-backend.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Allwinner A10 Display Engine Backend78maintainers:9- Chen-Yu Tsai <wens@csie.org>10- Maxime Ripard <mripard@kernel.org>1112description: |13The display engine backend exposes layers and sprites to the system.1415properties:16compatible:17enum:18- allwinner,sun4i-a10-display-backend19- allwinner,sun5i-a13-display-backend20- allwinner,sun6i-a31-display-backend21- allwinner,sun7i-a20-display-backend22- allwinner,sun8i-a23-display-backend23- allwinner,sun8i-a33-display-backend24- allwinner,sun9i-a80-display-backend2526reg:27minItems: 128items:29- description: Display Backend registers30- description: SAT registers3132reg-names:33minItems: 134items:35- const: be36- const: sat3738interrupts:39maxItems: 14041clocks:42minItems: 343items:44- description: The backend interface clock45- description: The backend module clock46- description: The backend DRAM clock47- description: The SAT clock4849clock-names:50minItems: 351items:52- const: ahb53- const: mod54- const: ram55- const: sat5657resets:58minItems: 159items:60- description: The Backend reset line61- description: The SAT reset line6263reset-names:64minItems: 165items:66- const: be67- const: sat6869# FIXME: This should be made required eventually once every SoC will70# have the MBUS declared.71interconnects:72maxItems: 17374# FIXME: This should be made required eventually once every SoC will75# have the MBUS declared.76interconnect-names:77const: dma-mem7879ports:80$ref: /schemas/graph.yaml#/properties/ports8182properties:83port@0:84$ref: /schemas/graph.yaml#/properties/port85description:86Input endpoints of the controller.8788port@1:89$ref: /schemas/graph.yaml#/properties/port90description:91Output endpoints of the controller.9293required:94- port@095- port@19697required:98- compatible99- reg100- interrupts101- clocks102- clock-names103- resets104- ports105106additionalProperties: false107108if:109properties:110compatible:111contains:112const: allwinner,sun8i-a33-display-backend113114then:115properties:116reg:117minItems: 2118119reg-names:120minItems: 2121122clocks:123minItems: 4124125clock-names:126minItems: 4127128resets:129minItems: 2130131reset-names:132minItems: 2133134required:135- reg-names136- reset-names137138else:139properties:140reg:141maxItems: 1142143reg-names:144maxItems: 1145146clocks:147maxItems: 3148149clock-names:150maxItems: 3151152resets:153maxItems: 1154155reset-names:156maxItems: 1157158examples:159- |160/*161* This comes from the clock/sun4i-a10-ccu.h and162* reset/sun4i-a10-ccu.h headers, but we can't include them since163* it would trigger a bunch of warnings for redefinitions of164* symbols with the other example.165*/166167#define CLK_AHB_DE_BE0 42168#define CLK_DRAM_DE_BE0 140169#define CLK_DE_BE0 144170#define RST_DE_BE0 5171172display-backend@1e60000 {173compatible = "allwinner,sun4i-a10-display-backend";174reg = <0x01e60000 0x10000>;175interrupts = <47>;176clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,177<&ccu CLK_DRAM_DE_BE0>;178clock-names = "ahb", "mod",179"ram";180resets = <&ccu RST_DE_BE0>;181182ports {183#address-cells = <1>;184#size-cells = <0>;185186port@0 {187#address-cells = <1>;188#size-cells = <0>;189reg = <0>;190191endpoint@0 {192reg = <0>;193remote-endpoint = <&fe0_out_be0>;194};195196endpoint@1 {197reg = <1>;198remote-endpoint = <&fe1_out_be0>;199};200};201202port@1 {203#address-cells = <1>;204#size-cells = <0>;205reg = <1>;206207endpoint@0 {208reg = <0>;209remote-endpoint = <&tcon0_in_be0>;210};211212endpoint@1 {213reg = <1>;214remote-endpoint = <&tcon1_in_be0>;215};216};217};218};219220- |221#include <dt-bindings/interrupt-controller/arm-gic.h>222223/*224* This comes from the clock/sun8i-a23-a33-ccu.h and225* reset/sun8i-a23-a33-ccu.h headers, but we can't include them226* since it would trigger a bunch of warnings for redefinitions of227* symbols with the other example.228*/229230#define CLK_BUS_DE_BE 40231#define CLK_BUS_SAT 46232#define CLK_DRAM_DE_BE 84233#define CLK_DE_BE 85234#define RST_BUS_DE_BE 21235#define RST_BUS_SAT 27236237display-backend@1e60000 {238compatible = "allwinner,sun8i-a33-display-backend";239reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;240reg-names = "be", "sat";241interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;242clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,243<&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;244clock-names = "ahb", "mod",245"ram", "sat";246resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;247reset-names = "be", "sat";248249ports {250#address-cells = <1>;251#size-cells = <0>;252253port@0 {254reg = <0>;255256endpoint {257remote-endpoint = <&fe0_out_be0>;258};259};260261port@1 {262reg = <1>;263264endpoint {265remote-endpoint = <&drc0_in_be0>;266};267};268};269};270271...272273274