Path: blob/master/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-frontend.yaml
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# SPDX-License-Identifier: GPL-2.01%YAML 1.22---3$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-frontend.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Allwinner A10 Display Engine Frontend78maintainers:9- Chen-Yu Tsai <wens@csie.org>10- Maxime Ripard <mripard@kernel.org>1112description: |13The display engine frontend does formats conversion, scaling,14deinterlacing and color space conversion.1516properties:17compatible:18enum:19- allwinner,sun4i-a10-display-frontend20- allwinner,sun5i-a13-display-frontend21- allwinner,sun6i-a31-display-frontend22- allwinner,sun7i-a20-display-frontend23- allwinner,sun8i-a23-display-frontend24- allwinner,sun8i-a33-display-frontend25- allwinner,sun9i-a80-display-frontend2627reg:28maxItems: 12930interrupts:31maxItems: 13233clocks:34items:35- description: The frontend interface clock36- description: The frontend module clock37- description: The frontend DRAM clock3839clock-names:40items:41- const: ahb42- const: mod43- const: ram4445# FIXME: This should be made required eventually once every SoC will46# have the MBUS declared.47interconnects:48maxItems: 14950# FIXME: This should be made required eventually once every SoC will51# have the MBUS declared.52interconnect-names:53const: dma-mem5455resets:56maxItems: 15758ports:59$ref: /schemas/graph.yaml#/properties/ports6061properties:62port@0:63$ref: /schemas/graph.yaml#/properties/port64description: |65Input endpoints of the controller.6667port@1:68$ref: /schemas/graph.yaml#/properties/port69description: |70Output endpoints of the controller.7172required:73- port@17475required:76- compatible77- reg78- interrupts79- clocks80- clock-names81- resets82- ports8384additionalProperties: false8586examples:87- |88#include <dt-bindings/clock/sun4i-a10-ccu.h>89#include <dt-bindings/reset/sun4i-a10-ccu.h>9091fe0: display-frontend@1e00000 {92compatible = "allwinner,sun4i-a10-display-frontend";93reg = <0x01e00000 0x20000>;94interrupts = <47>;95clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,96<&ccu CLK_DRAM_DE_FE0>;97clock-names = "ahb", "mod",98"ram";99resets = <&ccu RST_DE_FE0>;100101ports {102#address-cells = <1>;103#size-cells = <0>;104105fe0_out: port@1 {106#address-cells = <1>;107#size-cells = <0>;108reg = <1>;109110fe0_out_be0: endpoint@0 {111reg = <0>;112remote-endpoint = <&be0_in_fe0>;113};114115fe0_out_be1: endpoint@1 {116reg = <1>;117remote-endpoint = <&be1_in_fe0>;118};119};120};121};122123124...125126127