Path: blob/master/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-hdmi.yaml
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# SPDX-License-Identifier: GPL-2.01%YAML 1.22---3$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-hdmi.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Allwinner A10 HDMI Controller78description: |9The HDMI Encoder supports the HDMI video and audio outputs, and does10CEC. It is one end of the pipeline.1112maintainers:13- Chen-Yu Tsai <wens@csie.org>14- Maxime Ripard <mripard@kernel.org>1516properties:17compatible:18oneOf:19- const: allwinner,sun4i-a10-hdmi20- const: allwinner,sun5i-a10s-hdmi21- const: allwinner,sun6i-a31-hdmi22- items:23- const: allwinner,sun7i-a20-hdmi24- const: allwinner,sun5i-a10s-hdmi2526reg:27maxItems: 12829interrupts:30maxItems: 13132clocks:33oneOf:34- items:35- description: The HDMI interface clock36- description: The HDMI module clock37- description: The first video PLL38- description: The second video PLL3940- items:41- description: The HDMI interface clock42- description: The HDMI module clock43- description: The HDMI DDC clock44- description: The first video PLL45- description: The second video PLL4647clock-names:48oneOf:49- items:50- const: ahb51- const: mod52- const: pll-053- const: pll-15455- items:56- const: ahb57- const: mod58- const: ddc59- const: pll-060- const: pll-16162resets:63maxItems: 16465dmas:66items:67- description: DDC Transmission DMA Channel68- description: DDC Reception DMA Channel69- description: Audio Transmission DMA Channel7071dma-names:72items:73- const: ddc-tx74- const: ddc-rx75- const: audio-tx7677ports:78$ref: /schemas/graph.yaml#/properties/ports7980properties:81port@0:82$ref: /schemas/graph.yaml#/properties/port83description: |84Input endpoints of the controller.8586port@1:87$ref: /schemas/graph.yaml#/properties/port88description: |89Output endpoints of the controller. Usually an HDMI90connector.9192required:93- port@094- port@19596required:97- compatible98- reg99- interrupts100- clocks101- clock-names102- dmas103- dma-names104105if:106properties:107compatible:108contains:109const: allwinner,sun6i-a31-hdmi110111then:112properties:113clocks:114minItems: 5115116clock-names:117minItems: 5118119required:120- resets121122additionalProperties: false123124examples:125- |126#include <dt-bindings/clock/sun4i-a10-ccu.h>127#include <dt-bindings/dma/sun4i-a10.h>128#include <dt-bindings/reset/sun4i-a10-ccu.h>129130hdmi: hdmi@1c16000 {131compatible = "allwinner,sun4i-a10-hdmi";132reg = <0x01c16000 0x1000>;133interrupts = <58>;134clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,135<&ccu CLK_PLL_VIDEO0_2X>,136<&ccu CLK_PLL_VIDEO1_2X>;137clock-names = "ahb", "mod", "pll-0", "pll-1";138dmas = <&dma SUN4I_DMA_NORMAL 16>,139<&dma SUN4I_DMA_NORMAL 16>,140<&dma SUN4I_DMA_DEDICATED 24>;141dma-names = "ddc-tx", "ddc-rx", "audio-tx";142143ports {144#address-cells = <1>;145#size-cells = <0>;146147hdmi_in: port@0 {148#address-cells = <1>;149#size-cells = <0>;150reg = <0>;151152hdmi_in_tcon0: endpoint@0 {153reg = <0>;154remote-endpoint = <&tcon0_out_hdmi>;155};156157hdmi_in_tcon1: endpoint@1 {158reg = <1>;159remote-endpoint = <&tcon1_out_hdmi>;160};161};162163hdmi_out: port@1 {164reg = <1>;165};166};167};168169...170171172