Path: blob/master/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml
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# SPDX-License-Identifier: GPL-2.01%YAML 1.22---3$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tcon.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Allwinner A10 Timings Controller (TCON)78maintainers:9- Chen-Yu Tsai <wens@csie.org>10- Maxime Ripard <mripard@kernel.org>1112description: |13The TCON acts as a timing controller for RGB, LVDS and TV14interfaces.1516properties:17"#clock-cells":18const: 01920compatible:21oneOf:22- const: allwinner,sun4i-a10-tcon23- const: allwinner,sun5i-a13-tcon24- const: allwinner,sun6i-a31-tcon25- const: allwinner,sun6i-a31s-tcon26- const: allwinner,sun7i-a20-tcon27- const: allwinner,sun8i-a23-tcon28- const: allwinner,sun8i-a33-tcon29- const: allwinner,sun8i-a83t-tcon-lcd30- const: allwinner,sun8i-a83t-tcon-tv31- const: allwinner,sun8i-r40-tcon-tv32- const: allwinner,sun8i-v3s-tcon33- const: allwinner,sun9i-a80-tcon-lcd34- const: allwinner,sun9i-a80-tcon-tv35- const: allwinner,sun20i-d1-tcon-lcd36- const: allwinner,sun20i-d1-tcon-tv3738- items:39- enum:40- allwinner,sun7i-a20-tcon041- allwinner,sun7i-a20-tcon142- const: allwinner,sun7i-a20-tcon4344- items:45- enum:46- allwinner,sun50i-a64-tcon-lcd47- const: allwinner,sun8i-a83t-tcon-lcd4849- items:50- enum:51- allwinner,sun8i-h3-tcon-tv52- allwinner,sun50i-a64-tcon-tv53- const: allwinner,sun8i-a83t-tcon-tv5455- items:56- enum:57- allwinner,sun50i-h6-tcon-tv58- const: allwinner,sun8i-r40-tcon-tv5960reg:61maxItems: 16263interrupts:64maxItems: 16566clocks:67minItems: 168maxItems: 46970clock-names:71minItems: 172maxItems: 47374clock-output-names:75description:76Name of the LCD pixel clock created.77maxItems: 17879dmas:80maxItems: 18182resets:83anyOf:84- items:85- description: TCON Reset Line8687- items:88- description: TCON Reset Line89- description: TCON LVDS Reset Line9091- items:92- description: TCON Reset Line93- description: TCON eDP Reset Line9495- items:96- description: TCON Reset Line97- description: TCON eDP Reset Line98- description: TCON LVDS Reset Line99100reset-names:101oneOf:102- const: lcd103104- items:105- const: lcd106- const: lvds107108- items:109- const: lcd110- const: edp111112- items:113- const: lcd114- const: edp115- const: lvds116117ports:118$ref: /schemas/graph.yaml#/properties/ports119120properties:121port@0:122$ref: /schemas/graph.yaml#/properties/port123description: |124Input endpoints of the controller.125126port@1:127$ref: /schemas/graph.yaml#/$defs/port-base128unevaluatedProperties: false129description: |130Output endpoints of the controller.131132patternProperties:133"^endpoint(@[0-9])$":134$ref: /schemas/graph.yaml#/$defs/endpoint-base135unevaluatedProperties: false136137properties:138allwinner,tcon-channel:139$ref: /schemas/types.yaml#/definitions/uint32140description: |141TCON can have 1 or 2 channels, usually with the142first channel being used for the panels interfaces143(RGB, LVDS, etc.), and the second being used for the144outputs that require another controller (TV Encoder,145HDMI, etc.).146147If that property is present, specifies the TCON148channel the endpoint is associated to. If that149property is not present, the endpoint number will be150used as the channel number.151152required:153- port@0154- port@1155156required:157- compatible158- reg159- interrupts160- clocks161- clock-names162- resets163- ports164165additionalProperties: false166167allOf:168- if:169properties:170compatible:171contains:172enum:173- allwinner,sun4i-a10-tcon174- allwinner,sun5i-a13-tcon175- allwinner,sun7i-a20-tcon176177then:178properties:179clocks:180minItems: 3181182clock-names:183items:184- const: ahb185- const: tcon-ch0186- const: tcon-ch1187188- if:189properties:190compatible:191contains:192enum:193- allwinner,sun6i-a31-tcon194- allwinner,sun6i-a31s-tcon195196then:197properties:198clocks:199minItems: 4200201clock-names:202items:203- const: ahb204- const: tcon-ch0205- const: tcon-ch1206- const: lvds-alt207208- if:209properties:210compatible:211contains:212enum:213- allwinner,sun8i-a23-tcon214- allwinner,sun8i-a33-tcon215216then:217properties:218clocks:219minItems: 3220221clock-names:222items:223- const: ahb224- const: tcon-ch0225- const: lvds-alt226227- if:228properties:229compatible:230contains:231enum:232- allwinner,sun8i-a83t-tcon-lcd233- allwinner,sun8i-v3s-tcon234- allwinner,sun9i-a80-tcon-lcd235- allwinner,sun20i-d1-tcon-lcd236237then:238properties:239clocks:240minItems: 2241242clock-names:243items:244- const: ahb245- const: tcon-ch0246247- if:248properties:249compatible:250contains:251enum:252- allwinner,sun8i-a83t-tcon-tv253- allwinner,sun8i-r40-tcon-tv254- allwinner,sun9i-a80-tcon-tv255- allwinner,sun20i-d1-tcon-tv256257then:258properties:259clocks:260minItems: 2261262clock-names:263items:264- const: ahb265- const: tcon-ch1266267- if:268properties:269compatible:270contains:271enum:272- allwinner,sun5i-a13-tcon273- allwinner,sun6i-a31-tcon274- allwinner,sun6i-a31s-tcon275- allwinner,sun7i-a20-tcon276- allwinner,sun8i-a23-tcon277- allwinner,sun8i-a33-tcon278- allwinner,sun8i-v3s-tcon279- allwinner,sun9i-a80-tcon-lcd280- allwinner,sun4i-a10-tcon281- allwinner,sun8i-a83t-tcon-lcd282- allwinner,sun20i-d1-tcon-lcd283284then:285required:286- "#clock-cells"287- clock-output-names288289- if:290properties:291compatible:292contains:293enum:294- allwinner,sun6i-a31-tcon295- allwinner,sun6i-a31s-tcon296- allwinner,sun8i-a23-tcon297- allwinner,sun8i-a33-tcon298- allwinner,sun8i-a83t-tcon-lcd299- allwinner,sun20i-d1-tcon-lcd300301then:302properties:303resets:304minItems: 2305306reset-names:307items:308- const: lcd309- const: lvds310311- if:312properties:313compatible:314contains:315enum:316- allwinner,sun9i-a80-tcon-lcd317318then:319properties:320resets:321minItems: 3322323reset-names:324items:325- const: lcd326- const: edp327- const: lvds328329- if:330properties:331compatible:332contains:333enum:334- allwinner,sun9i-a80-tcon-tv335336then:337properties:338resets:339minItems: 2340341reset-names:342items:343- const: lcd344- const: edp345346- if:347properties:348compatible:349contains:350enum:351- allwinner,sun4i-a10-tcon352- allwinner,sun5i-a13-tcon353- allwinner,sun6i-a31-tcon354- allwinner,sun6i-a31s-tcon355- allwinner,sun7i-a20-tcon356- allwinner,sun8i-a23-tcon357- allwinner,sun8i-a33-tcon358359then:360required:361- dmas362363examples:364- |365#include <dt-bindings/dma/sun4i-a10.h>366367/*368* This comes from the clock/sun4i-a10-ccu.h and369* reset/sun4i-a10-ccu.h headers, but we can't include them since370* it would trigger a bunch of warnings for redefinitions of371* symbols with the other example.372*/373374#define CLK_AHB_LCD0 56375#define CLK_TCON0_CH0 149376#define CLK_TCON0_CH1 155377#define RST_TCON0 11378379lcd-controller@1c0c000 {380compatible = "allwinner,sun4i-a10-tcon";381reg = <0x01c0c000 0x1000>;382interrupts = <44>;383resets = <&ccu RST_TCON0>;384reset-names = "lcd";385clocks = <&ccu CLK_AHB_LCD0>,386<&ccu CLK_TCON0_CH0>,387<&ccu CLK_TCON0_CH1>;388clock-names = "ahb",389"tcon-ch0",390"tcon-ch1";391clock-output-names = "tcon0-pixel-clock";392#clock-cells = <0>;393dmas = <&dma SUN4I_DMA_DEDICATED 14>;394395ports {396#address-cells = <1>;397#size-cells = <0>;398399port@0 {400#address-cells = <1>;401#size-cells = <0>;402reg = <0>;403404endpoint@0 {405reg = <0>;406remote-endpoint = <&be0_out_tcon0>;407};408409endpoint@1 {410reg = <1>;411remote-endpoint = <&be1_out_tcon0>;412};413};414415port@1 {416#address-cells = <1>;417#size-cells = <0>;418reg = <1>;419420endpoint@1 {421reg = <1>;422remote-endpoint = <&hdmi_in_tcon0>;423allwinner,tcon-channel = <1>;424};425};426};427};428429#undef CLK_AHB_LCD0430#undef CLK_TCON0_CH0431#undef CLK_TCON0_CH1432#undef RST_TCON0433434- |435#include <dt-bindings/interrupt-controller/arm-gic.h>436437/*438* This comes from the clock/sun6i-a31-ccu.h and439* reset/sun6i-a31-ccu.h headers, but we can't include them since440* it would trigger a bunch of warnings for redefinitions of441* symbols with the other example.442*/443444#define CLK_PLL_MIPI 15445#define CLK_AHB1_LCD0 47446#define CLK_LCD0_CH0 127447#define CLK_LCD0_CH1 129448#define RST_AHB1_LCD0 27449#define RST_AHB1_LVDS 41450451lcd-controller@1c0c000 {452compatible = "allwinner,sun6i-a31-tcon";453reg = <0x01c0c000 0x1000>;454interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;455dmas = <&dma 11>;456resets = <&ccu RST_AHB1_LCD0>, <&ccu RST_AHB1_LVDS>;457reset-names = "lcd", "lvds";458clocks = <&ccu CLK_AHB1_LCD0>,459<&ccu CLK_LCD0_CH0>,460<&ccu CLK_LCD0_CH1>,461<&ccu CLK_PLL_MIPI>;462clock-names = "ahb",463"tcon-ch0",464"tcon-ch1",465"lvds-alt";466clock-output-names = "tcon0-pixel-clock";467#clock-cells = <0>;468469ports {470#address-cells = <1>;471#size-cells = <0>;472473port@0 {474#address-cells = <1>;475#size-cells = <0>;476reg = <0>;477478endpoint@0 {479reg = <0>;480remote-endpoint = <&drc0_out_tcon0>;481};482483endpoint@1 {484reg = <1>;485remote-endpoint = <&drc1_out_tcon0>;486};487};488489port@1 {490#address-cells = <1>;491#size-cells = <0>;492reg = <1>;493494endpoint@1 {495reg = <1>;496remote-endpoint = <&hdmi_in_tcon0>;497allwinner,tcon-channel = <1>;498};499};500};501};502503#undef CLK_PLL_MIPI504#undef CLK_AHB1_LCD0505#undef CLK_LCD0_CH0506#undef CLK_LCD0_CH1507#undef RST_AHB1_LCD0508#undef RST_AHB1_LVDS509510- |511#include <dt-bindings/interrupt-controller/arm-gic.h>512513/*514* This comes from the clock/sun9i-a80-ccu.h and515* reset/sun9i-a80-ccu.h headers, but we can't include them since516* it would trigger a bunch of warnings for redefinitions of517* symbols with the other example.518*/519520#define CLK_BUS_LCD0 102521#define CLK_LCD0 58522#define RST_BUS_LCD0 22523#define RST_BUS_EDP 24524#define RST_BUS_LVDS 25525526lcd-controller@3c00000 {527compatible = "allwinner,sun9i-a80-tcon-lcd";528reg = <0x03c00000 0x10000>;529interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;530clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;531clock-names = "ahb", "tcon-ch0";532resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>, <&ccu RST_BUS_LVDS>;533reset-names = "lcd", "edp", "lvds";534clock-output-names = "tcon0-pixel-clock";535#clock-cells = <0>;536537ports {538#address-cells = <1>;539#size-cells = <0>;540541port@0 {542reg = <0>;543544endpoint {545remote-endpoint = <&drc0_out_tcon0>;546};547};548549port@1 {550reg = <1>;551};552};553};554555#undef CLK_BUS_TCON0556#undef CLK_TCON0557#undef RST_BUS_TCON0558#undef RST_BUS_EDP559#undef RST_BUS_LVDS560561- |562#include <dt-bindings/interrupt-controller/arm-gic.h>563564/*565* This comes from the clock/sun8i-a83t-ccu.h and566* reset/sun8i-a83t-ccu.h headers, but we can't include them since567* it would trigger a bunch of warnings for redefinitions of568* symbols with the other example.569*/570571#define CLK_BUS_TCON0 36572#define CLK_TCON0 85573#define RST_BUS_TCON0 22574#define RST_BUS_LVDS 31575576lcd-controller@1c0c000 {577compatible = "allwinner,sun8i-a83t-tcon-lcd";578reg = <0x01c0c000 0x1000>;579interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;580clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;581clock-names = "ahb", "tcon-ch0";582clock-output-names = "tcon-pixel-clock";583#clock-cells = <0>;584resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;585reset-names = "lcd", "lvds";586587ports {588#address-cells = <1>;589#size-cells = <0>;590591port@0 {592#address-cells = <1>;593#size-cells = <0>;594reg = <0>;595596endpoint@0 {597reg = <0>;598remote-endpoint = <&mixer0_out_tcon0>;599};600601endpoint@1 {602reg = <1>;603remote-endpoint = <&mixer1_out_tcon0>;604};605};606607port@1 {608reg = <1>;609};610};611};612613#undef CLK_BUS_TCON0614#undef CLK_TCON0615#undef RST_BUS_TCON0616#undef RST_BUS_LVDS617618- |619#include <dt-bindings/interrupt-controller/arm-gic.h>620621/*622* This comes from the clock/sun8i-r40-ccu.h and623* reset/sun8i-r40-ccu.h headers, but we can't include them since624* it would trigger a bunch of warnings for redefinitions of625* symbols with the other example.626*/627628#define CLK_BUS_TCON_TV0 73629#define RST_BUS_TCON_TV0 49630631tcon_tv0: lcd-controller@1c73000 {632compatible = "allwinner,sun8i-r40-tcon-tv";633reg = <0x01c73000 0x1000>;634interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;635clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;636clock-names = "ahb", "tcon-ch1";637resets = <&ccu RST_BUS_TCON_TV0>;638reset-names = "lcd";639640ports {641#address-cells = <1>;642#size-cells = <0>;643644port@0 {645#address-cells = <1>;646#size-cells = <0>;647reg = <0>;648649endpoint@0 {650reg = <0>;651remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;652};653654endpoint@1 {655reg = <1>;656remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;657};658};659660tcon_tv0_out: port@1 {661#address-cells = <1>;662#size-cells = <0>;663reg = <1>;664665endpoint@1 {666reg = <1>;667remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;668};669};670};671};672673#undef CLK_BUS_TCON_TV0674#undef RST_BUS_TCON_TV0675676...677678679