Path: blob/master/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml
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# SPDX-License-Identifier: GPL-2.01%YAML 1.22---3$id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Allwinner R40 TCON TOP78maintainers:9- Chen-Yu Tsai <wens@csie.org>10- Maxime Ripard <mripard@kernel.org>1112description: |13TCON TOPs main purpose is to configure whole display pipeline. It14determines relationships between mixers and TCONs, selects source15TCON for HDMI, muxes LCD and TV encoder GPIO output, selects TV16encoder clock source and contains additional TV TCON and DSI gates.1718It allows display pipeline to be configured in very different ways:1920/ LCD0/LVDS021/ [0] TCON-LCD022| \ MIPI DSI23mixer0 |24\ / [1] TCON-LCD1 - LCD1/LVDS125TCON-TOP26/ \ [2] TCON-TV0 [0] - TVE0/RGB27mixer1 | \28| TCON-TOP - HDMI29| /30\ [3] TCON-TV1 [1] - TVE1/RGB3132Note that both TCON TOP references same physical unit. Both mixers33can be connected to any TCON. Not all TCON TOP variants support all34features.3536properties:37"#clock-cells":38const: 13940compatible:41enum:42- allwinner,sun8i-r40-tcon-top43- allwinner,sun20i-d1-tcon-top44- allwinner,sun50i-h6-tcon-top4546reg:47maxItems: 14849clocks:50minItems: 251maxItems: 65253clock-names:54minItems: 255maxItems: 65657clock-output-names:58minItems: 159maxItems: 36061resets:62maxItems: 16364ports:65$ref: /schemas/graph.yaml#/properties/ports6667properties:68port@0:69$ref: /schemas/graph.yaml#/properties/port70description: |71Input endpoint for Mixer 0 mux.7273port@1:74$ref: /schemas/graph.yaml#/properties/port75description: |76Output endpoint for Mixer 0 mux7778port@2:79$ref: /schemas/graph.yaml#/properties/port80description: |81Input endpoint for Mixer 1 mux.8283port@3:84$ref: /schemas/graph.yaml#/properties/port85description: |86Output endpoint for Mixer 1 mux8788port@4:89$ref: /schemas/graph.yaml#/properties/port90description: |91Input endpoint for HDMI mux.9293port@5:94$ref: /schemas/graph.yaml#/properties/port95description: |96Output endpoint for HDMI mux9798required:99- port@0100- port@1101- port@4102- port@5103104required:105- "#clock-cells"106- compatible107- reg108- clocks109- clock-names110- clock-output-names111- resets112- ports113114additionalProperties: false115116allOf:117- if:118properties:119compatible:120contains:121const: allwinner,sun8i-r40-tcon-top122123then:124properties:125clocks:126items:127- description: The TCON TOP interface clock128- description: The TCON TOP TV0 clock129- description: The TCON TOP TVE0 clock130- description: The TCON TOP TV1 clock131- description: The TCON TOP TVE1 clock132- description: The TCON TOP MIPI DSI clock133134clock-names:135items:136- const: bus137- const: tcon-tv0138- const: tve0139- const: tcon-tv1140- const: tve1141- const: dsi142143clock-output-names:144items:145- description: TCON TV0 output clock name146- description: TCON TV1 output clock name147- description: DSI output clock name148149ports:150required:151- port@2152- port@3153154- if:155properties:156compatible:157contains:158const: allwinner,sun20i-d1-tcon-top159160then:161properties:162clocks:163items:164- description: The TCON TOP interface clock165- description: The TCON TOP TV0 clock166- description: The TCON TOP TVE0 clock167- description: The TCON TOP MIPI DSI clock168169clock-names:170items:171- const: bus172- const: tcon-tv0173- const: tve0174- const: dsi175176clock-output-names:177items:178- description: TCON TV0 output clock name179- description: DSI output clock name180181- if:182properties:183compatible:184contains:185const: allwinner,sun50i-h6-tcon-top186187then:188properties:189clocks:190items:191- description: The TCON TOP interface clock192- description: The TCON TOP TV0 clock193194clock-names:195items:196- const: bus197- const: tcon-tv0198199clock-output-names:200items:201- description: TCON TV0 output clock name202203examples:204- |205#include <dt-bindings/interrupt-controller/arm-gic.h>206207#include <dt-bindings/clock/sun8i-r40-ccu.h>208#include <dt-bindings/reset/sun8i-r40-ccu.h>209210tcon_top: tcon-top@1c70000 {211compatible = "allwinner,sun8i-r40-tcon-top";212reg = <0x01c70000 0x1000>;213clocks = <&ccu CLK_BUS_TCON_TOP>,214<&ccu CLK_TCON_TV0>,215<&ccu CLK_TVE0>,216<&ccu CLK_TCON_TV1>,217<&ccu CLK_TVE1>,218<&ccu CLK_DSI_DPHY>;219clock-names = "bus",220"tcon-tv0",221"tve0",222"tcon-tv1",223"tve1",224"dsi";225clock-output-names = "tcon-top-tv0",226"tcon-top-tv1",227"tcon-top-dsi";228resets = <&ccu RST_BUS_TCON_TOP>;229#clock-cells = <1>;230231ports {232#address-cells = <1>;233#size-cells = <0>;234235tcon_top_mixer0_in: port@0 {236reg = <0>;237238tcon_top_mixer0_in_mixer0: endpoint {239remote-endpoint = <&mixer0_out_tcon_top>;240};241};242243tcon_top_mixer0_out: port@1 {244#address-cells = <1>;245#size-cells = <0>;246reg = <1>;247248tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {249reg = <0>;250};251252tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {253reg = <1>;254};255256tcon_top_mixer0_out_tcon_tv0: endpoint@2 {257reg = <2>;258remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;259};260261tcon_top_mixer0_out_tcon_tv1: endpoint@3 {262reg = <3>;263remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;264};265};266267tcon_top_mixer1_in: port@2 {268#address-cells = <1>;269#size-cells = <0>;270reg = <2>;271272tcon_top_mixer1_in_mixer1: endpoint@1 {273reg = <1>;274remote-endpoint = <&mixer1_out_tcon_top>;275};276};277278tcon_top_mixer1_out: port@3 {279#address-cells = <1>;280#size-cells = <0>;281reg = <3>;282283tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {284reg = <0>;285};286287tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {288reg = <1>;289};290291tcon_top_mixer1_out_tcon_tv0: endpoint@2 {292reg = <2>;293remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;294};295296tcon_top_mixer1_out_tcon_tv1: endpoint@3 {297reg = <3>;298remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;299};300};301302tcon_top_hdmi_in: port@4 {303#address-cells = <1>;304#size-cells = <0>;305reg = <4>;306307tcon_top_hdmi_in_tcon_tv0: endpoint@0 {308reg = <0>;309remote-endpoint = <&tcon_tv0_out_tcon_top>;310};311312tcon_top_hdmi_in_tcon_tv1: endpoint@1 {313reg = <1>;314remote-endpoint = <&tcon_tv1_out_tcon_top>;315};316};317318tcon_top_hdmi_out: port@5 {319reg = <5>;320321tcon_top_hdmi_out_hdmi: endpoint {322remote-endpoint = <&hdmi_in_tcon_top>;323};324};325};326};327328...329330331