Path: blob/master/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)1# Copyright 2019 BayLibre, SAS2%YAML 1.23---4$id: http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#67title: Amlogic specific extensions to the Synopsys Designware HDMI Controller89maintainers:10- Neil Armstrong <neil.armstrong@linaro.org>1112allOf:13- $ref: /schemas/sound/dai-common.yaml#1415description: |16The Amlogic Meson Synopsys Designware Integration is composed of17- A Synopsys DesignWare HDMI Controller IP18- A TOP control block controlling the Clocks and PHY19- A custom HDMI PHY in order to convert video to TMDS signal20___________________________________21| HDMI TOP |<= HPD22|___________________________________|23| | |24| Synopsys HDMI | HDMI PHY |=> TMDS25| Controller |________________|26|___________________________________|<=> DDC2728The HDMI TOP block only supports HPD sensing.29The Synopsys HDMI Controller interrupt is routed through the30TOP Block interrupt.31Communication to the TOP Block and the Synopsys HDMI Controller is done32via a pair of dedicated addr+read/write registers.33The HDMI PHY is configured by registers in the HHI register block.3435Pixel data arrives in "4:4:4" format from the VENC block and the VPU HDMI mux36selects either the ENCI encoder for the 576i or 480i formats or the ENCP37encoder for all the other formats including interlaced HD formats.3839The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate40DVI timings for the HDMI controller.4142Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare43HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF44audio source interfaces.4546properties:47compatible:48oneOf:49- items:50- enum:51- amlogic,meson-gxbb-dw-hdmi # GXBB (S905)52- amlogic,meson-gxl-dw-hdmi # GXL (S905X, S905D)53- amlogic,meson-gxm-dw-hdmi # GXM (S912)54- const: amlogic,meson-gx-dw-hdmi55- enum:56- amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2)5758reg:59maxItems: 16061interrupts:62maxItems: 16364clocks:65minItems: 36667clock-names:68items:69- const: isfr70- const: iahb71- const: venci7273power-domains:74maxItems: 175description: phandle to the associated power domain7677resets:78minItems: 37980reset-names:81items:82- const: hdmitx_apb83- const: hdmitx84- const: hdmitx_phy8586hdmi-supply:87description: phandle to an external 5V regulator to power the HDMI logic8889port@0:90$ref: /schemas/graph.yaml#/properties/port91description:92A port node pointing to the VENC Input port node.9394port@1:95$ref: /schemas/graph.yaml#/properties/port96description:97A port node pointing to the TMDS Output port node.9899"#address-cells":100const: 1101102"#size-cells":103const: 0104105"#sound-dai-cells":106const: 0107108sound-name-prefix: true109110required:111- compatible112- reg113- interrupts114- clocks115- clock-names116- resets117- reset-names118- port@0119- port@1120- "#address-cells"121- "#size-cells"122123additionalProperties: false124125examples:126- |127hdmi_tx: hdmi-tx@c883a000 {128compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";129reg = <0xc883a000 0x1c>;130interrupts = <57>;131resets = <&reset_apb>, <&reset_hdmitx>, <&reset_hdmitx_phy>;132reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";133clocks = <&clk_isfr>, <&clk_iahb>, <&clk_venci>;134clock-names = "isfr", "iahb", "venci";135power-domains = <&pd_vpu>;136#address-cells = <1>;137#size-cells = <0>;138139/* VPU VENC Input */140hdmi_tx_venc_port: port@0 {141reg = <0>;142143hdmi_tx_in: endpoint {144remote-endpoint = <&hdmi_tx_out>;145};146};147148/* TMDS Output */149hdmi_tx_tmds_port: port@1 {150reg = <1>;151152hdmi_tx_tmds_out: endpoint {153remote-endpoint = <&hdmi_connector_in>;154};155};156};157158159